1. An image detector comprising:
an active matrix-type TFT array substrate having a pixel area, in which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, a data line, and a bias line;
a conversion layer, which is arranged on the TFT array substrate and converts radiation into light; and
a conductive cover, which covers the conversion layer,
wherein the thin film transistor comprises: a plurality of gate lines having a gate electrode; a semiconductor layer provided to the gate electrode via a gate insulation film; and a source electrode and a drain electrode connected to the semiconductor layer,
wherein the photoelectric conversion element, which connects with the drain electrode via a first contact hole opened through a first passivation film provided above the thin film transistor,
wherein the data line is formed on a second passivation film provided above the photoelectric conversion element and connects with the source electrode via a second contact hole opened through the first passivation film and the second passivation film,
wherein the bias line is formed on the second passivation film provided above the photoelectric conversion element and connects with the photoelectric conversion element via a third contact hole opened through the second passivation film,
wherein the TFT array substrate comprises: a gate terminal to input a driving signal to the gate electrode from an outside; a data terminal to read out charges detected in the photoelectric conversion element to the outside via the data line; and a bias terminal to input an applied voltage from the outside to the photoelectric conversion element via the bias line,
wherein the conductive cover is adhered in an adhesion area in an upper layer than an area, in which at least one of the data line and the bias line extend from the pixel area to each of the terminals, and
wherein inorganic insulation films configured by at least two layers are formed between the at least one of the data line and the bias line and the adhesion area.
2. An image detector comprising:
an active matrix-type TFT array substrate having a pixel area, in which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, a data line, and a bias line;
a conversion layer, which is arranged on the TFT array substrate and converts radiation into light; and
a conductive cover, which covers the conversion layer,
wherein the thin film transistor comprises: a plurality of gate lines having a gate electrode; a semiconductor layer provided to the gate electrode via a gate insulation film; and a source electrode and a drain electrode connected to the semiconductor layer,
wherein the photoelectric conversion element, which connects with the drain electrode via a first contact hole opened through a first passivation film provided above the thin film transistor,
wherein the data line is formed on a second passivation film provided above the photoelectric conversion element and connects with the source electrode via a second contact hole opened through the first passivation film and the second passivation film,
wherein the bias line is formed on the second passivation film provided above the photoelectric conversion element and connects with the photoelectric conversion element via a third contact hole opened through the second passivation film,
wherein the TFT array substrate comprises: a gate terminal to input a driving signal to the gate electrode from an outside; a data terminal to read out charges detected in the photoelectric conversion element to the outside via the data line; and a bias terminal to input an applied voltage from the outside to the photoelectric conversion element via the bias line,
wherein the TFT array substrate comprises further comprises a terminal extracting line that connects with at least one of the data line and the bias line via a fourth contact hole opened through at least the second passivation film,
wherein the terminal extracting line connects with the at least one of the data terminal and the bias terminal,
wherein the conductive cover is adhered in an adhesion area in an upper layer than an area, in which the at least one of the data line and the bias line extends from the pixel area to each of the terminals, and
wherein the terminal extracting line is formed below the adhesion area.
3. The image detector according to claim 2,
wherein the fourth contact hole is formed at a side closer to the pixel area than the adhesion area.
4. The image detector according to claim 2,
wherein the at least one of the data line and the bias line and the terminal extracting line are connected to each other via a contact hole opened through the first passivation film and second passivation film.
5. An image detector comprising:
an active matrix-type TFT array substrate having a pixel area, in which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, a data line, and a bias line;
a conversion layer, which is arranged on the TFT array substrate and converts radiation into light; and
a conductive cover, which covers the conversion layer,
wherein the thin film transistor comprises: a plurality of gate lines having a gate electrode; a semiconductor layer provided to the gate electrode via a gate insulation film; and a source electrode and a drain electrode connected to the semiconductor layer,
wherein the photoelectric conversion element, which connects with the drain electrode via a first contact hole opened through a first passivation film provided above the thin film transistor,
wherein the data line is formed on a second passivation film provided above the photoelectric conversion element and connects with the source electrode via a second contact hole opened through the first passivation film and the second passivation film,
wherein the bias line is formed on the second passivation film provided above the photoelectric conversion element and connects with the photoelectric conversion element via a third contact hole opened through the second passivation film,
wherein the TFT array substrate comprises: a gate terminal to input a driving signal to the gate electrode from an outside; a data terminal to read out charges detected in the photoelectric conversion element to the outside via the data line; and a bias terminal to input an applied voltage from the outside to the photoelectric conversion element via the bias line,
wherein the conductive cover is adhered in an adhesion area in an upper layer than an area, in which at least one of the data line and the bias line extend from the pixel area to each of the terminals, and
wherein an island formed of a material configuring the photoelectric conversion element is provided between neighboring wirings of at least one of the data line and the bias line below the adhesion area.
6. The image detector according to claim 1,
wherein at least one of the first passivation film and the second passivation film are removed to form a recess portion below the adhesion area of the conductive cover, and
wherein the at least one of the data line and the bias line are formed in the recess portion.
7. The image detector according to claim 2,
wherein at least one of the first passivation film and the second passivation film are removed to form a recess portion below the adhesion area of the conductive cover, and
wherein the at least one of the data line and the bias line are formed in the recess portion.
8. The image detector according to claim 5,
wherein at least one of the first passivation film and the second passivation film are removed to form a recess portion below the adhesion area of the conductive cover, and
wherein the at least one of the data line and the bias line are formed in the recess portion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory, comprising:
a memory array comprising memory cells,
an inputoutput circuit which is connected to the memory cells and which interchanges data with the memory cells,
an output register which is connected to the inputoutput circuit, the output register being used to output data via a data output,
an input register which is connected to a data input and to the inputoutput circuit, the data input and the input register being used to input data into the memory cells, wherein test data is written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode and the test data is transmitted from the input register to the inputoutput circuit, wherein the inputoutput circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and
an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the inputoutput circuit.
2. The memory as claimed in claim 1, wherein the test data are read from the memory array by the inputoutput unit and are transmitted to the output register.
3. The memory as claimed in claim 1, wherein the output register forwards the stored test data to the input register in cyclic succession in the test mode.
4. The memory as claimed in claim 1, wherein the evaluation circuit compares the data from the stipulated memory cells with comparison data and outputs an error signal if there is a discrepancy.
5. The memory as claimed in claim 1, wherein the evaluation circuit checks the data from the stipulated memory cells for a signature.
6. The memory as claimed in claim 1, wherein the evaluation circuit is connected to an error register, and wherein the evaluation circuit stores an error data item in memory if a malfunction is identified.
7. The memory as claimed in claim 1, wherein the memory is a synchronous memory which outputs the data from memory cells to the output register under the clocking of a clock signal, wherein the output register supplies the data to the input register in clocked fashion, and wherein the input register transfers the data to the inputoutput circuit in clocked fashion.
8. The memory as claimed in claim 7, wherein the memory is in the form of a dynamic RAM store.
9. The memory as claimed in claim 1, wherein the output register is in the form of a FIFO memory.
10. The memory as claimed in claim 9, wherein the FIFO memory has an input pointer which takes a clock signal as a basis for connecting the inputoutput circuit to one of a plurality of data words, wherein the FIFO memory has an output pointer which connects one of the data words to an output of the FIFO memory, and wherein in the test mode the FIFO memory outputs the test data of the data words in cyclic succession.
11. The memory as claimed in claim 1, wherein the output register is connected to the input register directly by means of data lines.
12. A process for testing a memory chip comprising (1) a memory array comprising memory cells, and (2) an inputoutput unit which is connected to an output register and to an input register, the process comprising:
writing test data from the inputoutput unit to the output register in a test mode,
forwarding the test data from the output register to the input register,
forwarding the test data from the input register to the inputoutput unit, wherein the test data is used by the inputoutput unit for a test process, and
checking result data which are obtained after the performance of the test process and which are forwarded from the inputoutput unit to the input register via the output register, wherein the checking is performed by an evaluation unit connected to the input register.
13. The process as claimed in claim 12, wherein the test data are written to the output register when the test mode is started and are then routed in succession as a serial data stream to the input register.
14. A memory module, comprising:
a memory array comprising memory cells,
an inputoutput circuit which is connected to the memory cells and which interchanges data with the memory cells,
an output register which is connected to the inputoutput circuit, wherein the output register is used to output data via a data output,
an input register which is connected to a data input and to the inputoutput circuit, wherein the data input and the input register is used to input data into the memory cells, wherein test data is written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode, the test data being transmitted from the input register to the inputoutput circuit, wherein the inputoutput circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and
an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the inputoutput circuit.
15. A computer system, comprising:
a memory array comprising memory cells,
an inputoutput circuit which is connected to the memory cells and which interchanges data with the memory cells,
an output register which is connected to the inputoutput circuit, with the output register being used to output data via a data output,
an input register which is connected to a data input and to the inputoutput circuit, wherein the data input and the input register are used to input data into the memory cells, where in test data being written to the output register in a test mode, wherein the output register is connected to the input register, wherein the output register forwards the test data to the input register in the test mode, the test data being transmitted from the input register to the inputoutput circuit, wherein the inputoutput circuit (i) writes the test data received from the input register to stipulated memory cells, (ii) reads the stipulated memory cells again and (iii) outputs them to the output register, wherein the output register supplies the data which have been read from the stipulated memory cells to the input register, and
an evaluation circuit connected to the input register, wherein the evaluation circuit checks the processing of the test data by the inputoutput circuit.