Author: claimsbot

What is claimed is:

1. A Group III nitride compound semiconductor comprising:
a triple layer structure having an emission layer sandwiched between an n-type cladding layer and a p-type cladding layer;
said emission layer satisfying the formula Alx1Gay1In1-x1-y1N, where 0x11, 0y11, and 0x1y11, and having a thickness larger then diffusion length of holes;
said n-type cladding layer satisfying the formula Alx2Gay2In1-x2-y2N, where 0x21, 0y21and 0x2y21, being doped with a donor impurity, and having a lattice constant substantially equal to a lattice constant of said emission layer: and
said p-type cladding layer satisfying the formula Alx3Gay3In1-x3-y3N, where 0x31, 0y31, and 0x3y31, being doped with an acceptor impurity, having a forbidden band sufficiently wider than a forbidden band of said emission layer to confine electrons injected into said emission layer.
2. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer comprises Gay2In1-y2N, ,where 0.92y21, and wherein said n-type cladding layer comprises gallium nitride (GaN) doped with a donor impurity.
3. The Group III nitride compound semiconductor according to claim 2, wherein said n-type cladding layer is formed on a lower n type layer comprising gallium nitride (GaN), said lower n-type layer being doped with a donor impurity and comprising a donor impurity density higher than a donor impurity density of said n-type cladding layer.
4. The Group III nitride compound semiconductor according to claim 1, wherein said donor impurity is silicon (Si).
5. The Group III nitride compound semiconductor according to claim 1, wherein said acceptor impurity is magnesium (Mg).
6. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer is doped with silicon (Si).
7. The Group III nitride compound semiconductor comprising:
a multiple layer structure including an emission layer sandwiched between an n-type layer and a p-type layer:
said emission layer comprising a semiconductor material satisfying the formula Alx1Gay1In1-x1-y1N, where 0x11, 0y11, and 0x1y11, said emission layer having a thickness significantly larger than a diffusion length of holes within said emission layer:
said n-type cladding layer satisfying the formula Alx2Gay2In1-x2-y2N, where 0x21, 0y21and 0x2y21, being doped with a donor impurity; and
said p-type layer satisfying the formula Alx3Gay3In1-x3-y3N, where 0x31, 0y31, and 0x3y31, being doped with an acceptor impurity.
8. The Group III nitride compound semiconductor according to claim 7, wherein said n-type layer has a lattice constant substantially equal to a lattice constant of said emission layer.
9. The Group III nitride compound semiconductor according to claim 8, wherein said p-type layer comprises a forbidden band sufficiently wider than a forbidden band of said emission layer to confine electrons injected into said emission layer.
10. The Group III nitride compound semiconductor according to claim 1, wherein misfit ratio between said lattice constant of said n-type cladding layer and said lattice constant of said emission layer is within 1%.
11. The Group III nitride compound semiconductor according to claim 8, wherein misfit ratio between said lattice constant of said n-type cladding layer and said lattice constant of said emission layer is within 1%.
12. The Group III nitride compound semiconductor according to claim 1, wherein said emission layer has a thickness of 0.1 m to 1.0 m.
13. The Group III nitride compound semiconductor according to claim 7, wherein said emission layer has a thickness of 0.1 m to 1.0 m.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit chip, comprising:
a plurality of trenches at least partially surrounding a perimeter of a critical portion of the integrated circuit chip;
circuitry sensitive to temperature variation located in said critical portion;
wherein said trenches are locally disconnected from each other;
one or more electrical connections passing along a portion of the integrated circuit chip where the trenches are locally disconnected from each other, said electrical connections extending between said critical portion and an outer portion of the integrated circuit chip;
one or more heating resistors placed in said circuit portion; and
a temperature sensor placed in said circuit portion.
2. The chip of claim 1, wherein the temperature sensor is a PN junction diode.
3. The chip of claim 1, wherein the heating resistors are diffused resistors.
4. The chip of claim 1, wherein said plurality of trenches comprises a double network of trenches surrounding the critical portion, the trenches of said double network of trenches being formed to define arms connecting the critical portion of the integrated circuit ship to the outer portion of the integrated circuit chip.
5. The chip of claim 1, comprising a semiconductor layer supported by, but insulated from, an underlying support layer, wherein said trenches extend to a depth which passes completely through a thickness of the semiconductor layer.
6. The chip of claim 1, wherein a bottom of said critical portion is insulated from said underlying support layer.
7. The chip of claim 1, further comprising a cap layer mounted to the outer portion of the integrated circuit chip and extending over, but insulated from, said critical portion.
8. The chip of claim 1, comprising an amplifier including a first circuit part in the outer portion of the integrated circuit chip and a second circuit part which comprises said circuitry sensitive to temperature variation in the critical portion.
9. The chip of claim 8, wherein said circuitry sensitive to temperature variation affects offset voltage of the amplifier.
10. The chip of claim 8, wherein said second circuit part which comprises said circuitry sensitive to temperature variation comprises an input stage of said amplifier.
11. A method, comprising:
defining a critical portion of an integrated circuit chip;
providing a plurality of insulating trenches at least partially surrounding a perimeter of the critical portion;
placing circuitry that is sensitive to temperature variation within the critical portion;
placing a temperature sensor within the critical portion placing heating resistor elements in critical portion.
12. The method of claim 11, further comprising:
actuating the heating resistors to subject the critical portion to temperature variation;
monitoring the temperature sensor in response to said temperature variation so as to test the integrated circuit chip at various temperatures; and
adjusting said circuitry that is sensitive to temperature variation.
13. The method of claim 11, wherein the temperature sensor is a PN junction diode.
14. The method of claim 11, wherein providing said plurality of trenches comprises forming a double network of trenches surrounding the critical portion, the trenches of said double network of trenches being formed to define arms connecting the critical portion of the integrated circuit ship to an outer portion of the integrated circuit chip.
15. The method of claim 11, further comprising forming one or more electrical connections passing along a portion of the integrated circuit chip where the trenches are locally disconnected from each other, said electrical connections extending between said critical portion and an outer portion of the integrated circuit chip.
16. The method of claim 15, further comprising mounting a cap layer to the outer portion of the integrated circuit chip and extending over, but insulated from, said critical portion.
17. The method of claim 11, wherein providing said plurality of insulating trenches comprises extending each of said wherein said trenches to a depth which passes completely through a thickness of a semiconductor layer that is supported by, but insulated from, an underlying support layer.
18. The method of claim 11, further comprising integrating an amplifier circuit for said integrated circuit chip including a first circuit part formed in an outer portion of the integrated circuit chip and a second circuit part which comprises said circuitry sensitive to temperature variation in the critical portion.
19. The method of claim 18, wherein said circuitry sensitive to temperature variation affects offset voltage of the amplifier.
20. The method of claim 18, wherein said second circuit part which comprises said circuitry sensitive to temperature variation comprises an input stage of said amplifier.
21. The method of claim 11, wherein said plurality of insulating trenches are locally disconnected from each other.

1. A method for detecting phasefrequency error in a digital phase-locked loop (PLL) comprising:
receiving compare edge of a reference clock signal and compare edge of a feedback clock signal;
maintaining a phasefrequency detector, (PFD) state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals;
recording current and previous time the PFD state machine stays in UP or DOWN states;
generating an UP or DOWN signal based on transition of PFD states and a comparison between recorded current time and recorded previous time; and
outputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal.
2. The method according to claim 1, wherein recording current and previous time the PFD state machine stays in UP or DOWN states is performed by using a current UP time counter, a previous UP time counter, a current DOWN time counter, and a previous DOWN time counter.
3. The method according to claim 2, wherein generating an UP or DOWN signal based on the recorded current and previous time comprises:
generating an UP signal if the current UP time counter is no less than the previous UP time counter when transition from UP state to IDLE state, or if the current DOWN time counter is smaller than the previous DOWN time counter when transition from DOWN state to IDLE state; and
generating an DOWN signal if the current DOWN time counter is no less than the previous DOWN time counter when transition from DOWN state to IDLE state, or if the current UP time counter is smaller than the previous UP time counter when transition from UP state to IDLE state.
4. The method according to claim 1, wherein maintaining the PFD state machine comprises:
transiting PFD state machine state from IDLE to UP when a compare edge of the reference clock signal is detected while no compare edge of the feedback clock signal is detected in IDLE state;
transiting PFD state machine state from UP to IDLE when a compare edge of the feedback clock signal is detected in UP state;
transiting PFD state machine state from IDLE to DOWN when a compare edge of the feedback clock signal is detected while no compare edge of the reference clock signal is detected in IDLE state; and
transiting PFD state machine state from DOWN to IDLE when a compare edge of the reference clock signal is detected in DOWN state.
5. The method according to claim 1, further comprising using a divider state machine to reduce an initial phase error of the compare edges of the reference and feedback clock signals.
6. The method according to claim 5, wherein using the divider state machine to reduce the initial phase error of the compare edges of the reference and feedback clock signals comprises:
setting the divider state machine into one of three states: IDLE, SYNC, and DIVIDE; and
finding a first compare edge of the feedback clock signal adjacent to a first compare edge of reference clock signal.
7. The method according to claim 1, further comprising updating an UP gain counter and a DOWN gain counter based on the UP or DOWN signal.
8. The method according to claim 7, further comprising updating an integrator by detecting overflow of the UP gain counter and the DOWN gain counter.
9. The method according to claim 1, further comprising detecting a cycle slip between the reference and feedback clock signals, wherein the cycle slip is detected if a compare edge of the reference clock signal appears in the UP state, or if a compare edge of the feedback clock signal appears in the DOWN state.
10. The method according to claim 1, wherein the compare edges may be generated based on either rising edge of the referencefeedback clock signal or falling edge of the referencefeedback clock signal.
11. A phasefrequency detector (PFD), comprising:
a phasefrequency detector state machine arranged to receive compare edges of the reference and feedback clock signals, wherein the PFD state machine is further arranged to maintain in three PFD states, UP, DOWN, and IDLE, based on the compare edges of the reference and feedback clock signals;
and wherein the PFD is arranged to:
record current and previous time the PFD state machine stays in UP or DOWN states;
generate an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and
output a digital control signal to a feedback frequency control device based on the UP or DOWN signal.
12. The phasefrequency detector according to claim 11, further comprising an UP gain counter and a DOWN gain counter receiving the UP and DOWN signals respectively.
13. The phasefrequency detector according to claim 12, further comprising an integrator receiving overflow signals from one of the UP or DOWN gain counters and arranged to output a digital control signal to a feedback frequency control device.
14. The phasefrequency detector according to claim 11, further comprising:
a first clock divider arranged to receive the reference clock signal and provide the compare edge of the reference clock signal; and
a second clock divider arranged to receive the feedback clock signal and provide the compare edge of the feedback clock signal;
wherein each of the first clock divider and the second clock divider include a divider state machine to reduce an initial phase error of the compare edges.
15. A digital phase locked loop (PLL) circuit comprising:
a reference clock signal divider receiving a reference clock signal and outputting a compare edge of the reference clock signal;
a feedback clock signal divider receiving a feedback clock signal and outputting a compare edge of the feedback clock signal;
a phasefrequency detector (PFD), receiving the compare edges of the reference and feedback clock signals and arranged to output a digital control signal related to a phasefrequency error; and
a feedback frequency control device arranged to receive the digital control signal related to a phasefrequency error from the PFD and to control a frequency of the feedback clock signal;
wherein the PFD is arranged to:
receive the compare edge of the reference clock signal;
receive the compare edge of the feedback clock signal;
maintain a PFD state machine in three PFD states, UP, DOWN, and IDLE, based on the compare edges of the reference and feedback clock signals;
record current and previous time the state machine stays in UP or DOWN states;
generate an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and
output the digital control signal to the feedback frequency control device based on the UP or DOWN signal.
16. The digital phase locked loop circuit according to claim 15, wherein the PLL is one of an all-digital PLL or a hybrid PLL.
17. The phasefrequency detector according to claim 11, further comprising a current UP time counter, a previous UP time counter, a current DOWN time counter, and a previous DOWN time counter being used for recording current and previous time that the phasefrequency detector state machine stays in UP or DOWN states.
18. The phasefrequency detector according to claim 17, wherein generating an UP or DOWN signal based on the recorded current and previous time comprises:
generating an UP signal if the current UP time counter is no less than the previous UP time counter when transition from UP state to IDLE state, or if the current DOWN time counter is smaller than the previous DOWN time counter when transition from DOWN state to IDLE state; and
generating an DOWN signal if the current DOWN time counter is no less than the previous DOWN time counter when transition from DOWN state to IDLE state, or if the current UP time counter is smaller than the previous UP time counter when transition from UP state to IDLE state.
19. The phasefrequency detector according to claim 11, wherein maintaining the PFD state machine comprises:
transiting PFD state machine state from IDLE to UP when a compare edge of the reference clock signal is detected while no compare edge of the feedback clock signal is detected in IDLE state;
transiting PFD state machine state from UP to IDLE when a compare edge of the feedback clock signal is detected in UP state;
transiting PFD state machine state from IDLE to DOWN when a compare edge of the feedback clock signal is detected while no compare edge of the reference clock signal is detected in IDLE state; and
transiting PFD state machine state from DOWN to IDLE when a compare edge of the reference clock signal is detected in DOWN state.
20. The phasefrequency detector according to claim 11, wherein the compare edges may be generated based on either rising edge of the referencefeedback clock signal or falling edge of the referencefeedback clock signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for making a smooth ceramic, comprising:
loading ceramic powder to be densified into a hot press die;
placing one or more spacers with a polished surface between a hot press punch and the ceramic powder;
placing the die and punch into a hot press and hot pressing the ceramic powder; and
after hot pressing, removing a smooth ceramic shape that requires no subsequent polishing or processing and has a surface roughness of 5 nm RMS or better.
2. The method of claim 1, wherein the smooth ceramic shape is transparent.
3. The method of claim 1, wherein the smooth ceramic shape is not transparent.
4. The method of claim 1, wherein the ceramic is spinel, magnesia, yttria, lutetia, scandia, YAG, any composites thereof, or any of their rare earth doped compounds.
5. The method of claim 1, wherein the ceramic is magnesium aluminum spinel.
6. The method of claim 1, wherein the ceramic is a glassceramic composite.
7. The method of claim 1, wherein the spacer comprises a carbide, boride, silicide, nitride, diamond, vitreous carbon, or any combination thereof.
8. The method of claim 1, wherein the spacer is not flat.
9. The method of claim 8, wherein the smooth ceramic shape is a lens.
10. The method of claim 1, wherein hot pressing is done without a sintering aid.
11. A smooth ceramic made by a process comprising the steps of:
loading ceramic powder to be densified into a hot press die;
placing one or more spacers with a polished surface between a hot press punch and the ceramic powder;
placing the die and punch into a hot press and hot pressing the ceramic powder; and
after hot pressing, removing a smooth ceramic shape that requires no subsequent polishing or processing and has a surface roughness of 5 nm RMS or better.
12. The ceramic of claim 11, wherein the smooth ceramic shape is transparent.
13. The ceramic of claim 11, wherein the smooth ceramic shape is not transparent.
14. The ceramic of claim 11, wherein the ceramic is spinel, yttria, lutetia, scandia, YAG, or any of their rare earth doped compounds.
15. The ceramic of claim 11, wherein the ceramic is magnesium aluminum spinel.
16. The ceramic of claim 11, wherein the ceramic is a glassceramic composite.
17. The ceramic of claim 11, wherein the spacer comprises a carbide, boride, silicide, nitride, diamond, vitreous carbon, or any combination thereof.
18. The ceramic of claim 11, wherein the spacer is not flat.
19. The ceramic of claim 18, wherein the smooth ceramic shape is a lens.
20. The ceramic of claim 11, wherein hot pressing is done without a sintering aid.
21. A method for making a smooth glass, comprising:
loading glass powder to be densified into a hot press die;
placing one or more spacers with a polished surface between a hot press punch and the glass powder;
placing the die and punch into a hot press and hot pressing the glass powder; and
after hot pressing, removing a smooth glass shape that requires no subsequent polishing or processing and has a surface roughness of 5 nm RMS or better.