1. A method for making a foamed polymeric panel from a solid monolithic semi-crystalline thermoplastic material sheet, the semi-crystalline thermoplastic sheet having an initial first thickness and a uniform first density level, the method comprising:
absorbing an effective amount of a plasticizing gas into the semi-crystalline thermoplastic material sheet to yield a reversibly plasticized semi-crystalline thermoplastic material sheet, wherein the plasticized semi-crystalline thermoplastic material is differentially impregnated with the plasticizing gas to define a non-uniform gas concentration gradient across the initial first thickness; and
heating the plasticized semi-crystalline thermoplastic sheet to yield the foamed polymeric panel, and wherein the foamed polymeric panel comprises (1) a second thickness that is at least about three and half times greater than the first initial thickness, and (2) a non-uniform second density level that is less than the first density level.
2. The method according to claim 1 wherein the semi-crystalline thermoplastic material sheet is selected from the group consisting of polyethylene terephthalate (PET), polyactic acid (PLA), polyethylene napthalate (PEN), polybutylterephthalate (PBT), polypropylene (PP), polyethylene (PE), polyhydroxyalkanoate (PHA), polyetherketoneketone (PEKK), polyetheretherketone (PEEK), polyphthalamide (PPA), polyphenylene sulfide (PPS), and blends thereof.
3. The method according to claim 1 wherein the semi-crystalline thermoplastic material sheet is polyactic acid (PLA).
4. The method according to claim 1 wherein the semi-crystalline thermoplastic material sheet is polyethylene terephthalate (PET).
5. The method according to claim 3 wherein the plasticizing gas is carbon dioxide (CO2).
6. The method according to claim 4 wherein the plasticizing gas is carbon dioxide (CO2).
7. The method according to claim 2 wherein the foamed polymeric panel comprises smooth outer unfoamed surface layers sandwiching one or more inner foamed layers.
8. The method according to claim 7 wherein the one or more inner foamed layers comprises a plurality of closed cells, wherein the plurality of closed cells have an average cell diameter ranging from about 5 to about 1,000 microns.
9. The method according to claim 8 wherein the plurality of closed cell are, on average, largest at the middle portion of the foamed polymeric panel.
10. The method according to claim 8 wherein the plurality of closed cell define a non-uniform average cell size gradient across the second thickness, wherein the largest average cell size occurs at the middle portion of the foamed polymeric panel.
11. The method according to claim 10 wherein the second non-uniform density level is, on average, no greater than about 20 percent of the uniform first density level.
12. The method according to claim 1 wherein the solid monolithic semi-crystalline thermoplastic material sheet is non-planar.
13. The method according to claim 1, further comprising a step of desorbing at least some of the plasticizing gas from the plasticized semi-crystalline thermoplastic material sheet, wherein the step of desorbing occurs after the step of absorbing.
14. The method according to claim 13, further comprising a step of thermoforming the plasticized semi-crystalline thermoplastic sheet, wherein the step of thermoforming occurs after the step of desorbing.
15. The method according to claim 13, further comprising a step of thermoforming the plasticized semi-crystalline thermoplastic sheet, wherein the step of thermoforming occurs at the same time as the step of heating.
16. The method according to claim 15, further comprising a step of quenching the plasticized semi-crystalline thermoplastic sheet, wherein the step of quenching occurs after the step of thermoforming.
17. The method according to claim 13, further comprising a step of thermoforming the plasticized semi-crystalline thermoplastic sheet, wherein the step of thermoforming occurs after the step of heating.
18. The method according to claim 17 wherein the foamed polymeric panel is closed cell and microcellular.
19. A method for making a foamed polymeric panel from a solid monolithic semi-crystalline thermoplastic material sheet, the semi-crystalline thermoplastic sheet having an initial first thickness, a uniform first density level, and a first volume, the method comprising:
absorbing an effective amount of a plasticizing gas into the semi-crystalline thermoplastic material sheet to yield a reversibly plasticized semi-crystalline thermoplastic material sheet, wherein the plasticized semi-crystalline thermoplastic material is differentially impregnated with the plasticizing gas to define a non-uniform gas concentration gradient across the initial first thickness; and
heating the plasticized semi-crystalline thermoplastic sheet to yield the foamed polymeric panel, and wherein the foamed polymeric panel comprises (1) a second thickness that is at least about three and half times greater than the first initial thickness, (2) a non-uniform second density level that is less than the first density level, and (3) a second volume that is at least 5 times greater than the first volume.
20. The method according to claim 19 wherein the second non-uniform density level is, on average, no greater than about 20 percent of the uniform first density level.
21. The method according to claim 20 wherein the second volume is about 5 to about 33 times greater than the first volume.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-51. (canceled)
52. A method, comprising:
creating microcode in non-volatile memory in an integrated circuit for causing an embedded processor in the integrated circuit to generate a plurality of pseudo-random test patterns to be used in testing of the integrated circuit;
creating microcode in the non-volatile memory for causing the embedded processor to move at least one of the plurality of pseudo-random test patterns to a test port register coupled to the embedded processor; and
creating microcode in the non-volatile memory for causing the embedded processor to move test responses from the test port register to the embedded processor.
53. The method of claim 52, wherein the testing of the integrated circuit comprises testing a plurality of peripheral devices, the plurality of peripheral devices having associated parallel scan registers coupled to the embedded processor.
54. The method of claim 52, further comprising creating microcode in the non-volatile memory for causing the embedded processor to compact the test responses.
55. The method of claim 52, wherein the embedded processor comprises a plurality of data paths.
56. The method of claim 55, wherein the testing comprises using the plurality of data paths in a test mode of operation.
57. The method of claim 52, wherein the test port register comprises a plurality of input ports and a plurality of output ports.
58. The method of claim 53, further comprising creating microcode in the non-volatile memory for causing the embedded processor to generate a plurality of deterministic test patterns for the plurality of peripheral devices.
59. The method of claim 54, wherein creating microcode for causing the embedded processor to compact the test responses comprises creating microcode in the non-volatile memory to cause the embedded processor to:
move a first test response into a first accumulator;
add a first signature to the first accumulator;
move a second test response into a second accumulator;
output the content of the first accumulator; and
add the output of the first accumulator into the second accumulator.
60. The method of claim 59, wherein creating microcode for causing the embedded processor to compact the test responses further comprises creating microcode in the non-volatile memory to cause the embedded processor to:
move the second test response into the first accumulator;
add a second signature into the first accumulator, the second signature comprising the first test response;
move a third test response into the second accumulator; and
add the output of the first accumulator into the second accumulator.
61. One or more computer-readable media having computer-executable instructions for performing the method of claim 52.
62. An apparatus, comprising:
means for generating pseudo-random test patterns in an integrated circuit, wherein the integrated circuit comprises an embedded processor core and a plurality of peripheral devices, the embedded processor core comprising a plurality of data paths;
means for testing the plurality of peripheral devices using the pseudo-random test patterns and the plurality of data paths; and
means for compacting peripheral device test-response data.
63. The apparatus of claim 62, wherein the embedded processor core comprises a plurality of registers, at least one multiplier, at least one adder, and at least one accumulator.
64. The apparatus of claim 62, wherein the integrated circuit further comprises a test port register, the test port register serving as an interface between the embedded processor core and at least one scan register.
65. The apparatus of claim 62, wherein the means for generating pseudo-random test patterns comprises multiplying n least significant bits of a 2n-bit pseudo-random number generated in an immediately preceding iteration and stored in a first register, with an n-bit multiplier constant stored in a second register to produce a 2n-bit product.
66. The apparatus of claim 65, wherein the means for generating pseudo-random test patterns further comprises adding the 2n-bit product to n most significant bits of the 2n-bit pseudo-random number stored in n least significant locations of an accumulator with 2n locations to produce a new 2n-bit pseudo-random number for a current iteration.
67. The apparatus of claim 66, wherein the means for generating pseudo-random test patterns further comprises outputting n least significant bits of the new 2n-bit pseudo-random number as an n-bit pseudo-random test vector for the plurality of peripheral devices.
68. The apparatus of claim 62, wherein the means for compacting peripheral device test-response data comprises:
means for moving an n-bit segment of the peripheral device performance data to a first-stage accumulator;
means for adding the n-bit segment to a signature value at the first-stage accumulator;
means for cascading the signature value to a second-stage accumulator; and
means for adding the n-bit segment to the cascaded result.
69. The apparatus of claim 68, wherein the means for cascading the signature value to the second-stage accumulator comprises a 1’s complement convention.
70. The apparatus of claim 68, wherein the means for cascading the signature value to the second-stage accumulator comprises a rotate carry scheme.
71. A method for testing integrated circuits, comprising:
a step for producing at least one two-dimensional pseudo-random test pattern in an integrated circuit, the integrated circuit having an embedded processor and a peripheral device;
a step for generating at least one two-dimensional deterministic test pattern in the integrated circuit;
a step for testing the peripheral device using the two-dimensional pseudo-random test pattern and the two-dimensional deterministic test pattern; and
a step for compacting test-response data.
72. The method of claim 71, wherein the step for testing the peripheral device comprises a step for providing the two-dimensional pseudo-random test pattern and the two-dimensional deterministic test pattern to the peripheral device via a test port register, the test port register coupled to the embedded processor and at least one scan register.
73. The method of claim 71, further comprising a step for repeating the step for testing the peripheral device until all desired test patterns have been produced and used in the testing.