Author: claimsbot

1. A procedure for wireless transmission between a wheel module (9) arranged in a tire (2) and a control device (3; 28) arranged outside the tire (2), the method comprising:
transferring a first transmission signal (S1) from an antenna (6) of the control device (3; 28) to an antenna (11) of the wheel module (9);
transmitting data via a second transmission signal (S2) from the wheel module (9) to the control device (3; 28), wherein a different frequency is provided for the first transmission signal (S1) than for the second transmission signal (S2);
receiving by the antenna (11) of the wheel module the first transmission signal (S1), during a coupling period (TK) within which when the tires (2) are rotating, an also rotating sphere of influence (15) of the antenna (11) of the wheel module (9) and a stationary sphere of influence (14) of the antenna (6) of the control device (3; 28) partially overlap; and
recognizing a beginning of the coupling period (TK) is recognised by the wheel module (9), wherein the transmission of data from the wheel module (9) to the control device (3; 28) is started after the coupling period (TK) begins, wherein a speed of the tire (2) or a size which is proportional to it is recorded and compared with a speed threshold value, and the second transmission signal (S2) can be transmitted with an extended data telegram in particular only when the speed threshold value is not reached.
2. A procedure according to claim 1, wherein the frequency (1) of the first transmission signal (S1) is lower than the frequency of the second transmission signal (S2).
3. A procedure according to claim 1, wherein power is gained from the first transmission signal in order to supply the wheel module (9).
4. A procedure according to claim 3, wherein with the power gained, a power storage unit (22) is charged and the data transmission from the wheel module (9) to the control device (3; 28) is started after a prespecified charging condition (LMAX) of the power storage unit (22) has been started.
5. A procedure according to claim 4, wherein the second transmission signal (S2) is transmitted with an extended data telegram when the power storage unit (22), assuming that a significant discharge has occurred, has achieved the prespecified charging condition (LMAX).
6. A procedure according to claim 5, wherein the second transmission signal (S2) is transmitted with a standard data telegram when a charging condition (L) of the power storage unit has not fallen below a prespecified charging condition threshold value (LMIN) since the previous data transmission from the wheel module (9) to the control device (3; 28).
7. A procedure according to claim 1, wherein the first transmission signal (S1) is transmitted from the control device (3; 28) at least partially overriding several coupling periods (TK).
8. A procedure according to claim 1, wherein data from the control device (3; 28) to the wheel module (9) is transmitted by means of the control device (3; 28);
after an at least partial reception of the second transmission signal (S2) in the first transmission signal (S1), a prespecified interruption is executed, or a prespecified zero sequence is transmitted;
the first transmission signal (S1) is then loaded with the data to be transmitted from the control device (3; 28) to the wheel module (9) and in the wheel module (9);
the interruption or zero sequence is recognised in the first transmission signal (S1); and
the first transmission signal (S1) is received with the data from the control device (3; 28).
9. A procedure according to claim 1, wherein the first and the second transmission signal (S1, S2) is transmitted or received using a ground antenna (29) of the control device (28) arranged in a road surface (30).
10. A procedure for wireless transmission between a wheel module (9) arranged in a tire (2) and a control device (3; 28) arranged outside the tire (2), the method comprising:
transferring a first transmission signal (S1) from an antenna (6) of the control device (3; 28) to an antenna (11) of the wheel module (9);
transmitting data via a second transmission signal (S2) from the wheel module (9) to the control device (3; 28), wherein a different frequency is provided for the first transmission signal (S1) than for the second transmission signal (S2);
receiving by the antenna (11) of the wheel module the first transmission signal (S1), during a coupling period (TK) within which when the tires (2) are rotating, an also rotating sphere of influence (15) of the antenna (11) of the wheel module (9) and a stationary sphere of influence (14) of the antenna (6) of the control device (3; 28) partially overlap; and
recognizing a beginning of the coupling period (TK) is recognised by the wheel module (9), wherein the transmission of data from the wheel module (9) to the control device (3; 28) is started after the coupling period (TK) begins, wherein a current measured value of at least one tire condition sensor (24, 25, 26) which is arranged in the tire (2) is transmitted using standard data telegrams which are included in the second transmission signal (S2) from the wheel module (9) to the control device (3; 28).
11. A procedure for wireless transmission between a wheel module (9) arranged in a tire (2) and a control device (3; 28) arranged outside the tire (2), the method comprising:
transferring a first transmission signal (S1) from an antenna (6) of the control device (3; 28) to an antenna (11) of the wheel module (9);
transmitting data via a second transmission signal (S2) from the wheel module (9) to the control device (3; 28), wherein a different frequency is provided for the first transmission signal (S1) than for the second transmission signal (S2);
receiving by the antenna (11) of the wheel module the first transmission signal (S1), during a coupling period (TK) within which when the tires (2) are rotating, an also rotating sphere of influence (15) of the antenna (11) of the wheel module (9) and a stationary sphere of influence (14) of the antenna (6) of the control device (3; 28) partially overlap; and
recognizing a beginning of the coupling period (TK) is recognised by the wheel module (9), wherein the transmission of data from the wheel module (9) to the control device (3; 28) is started after the coupling period (TK) begins, wherein a current measured value of at least one tire condition sensor (24, 25, 28) arranged in the tire (2) together with a set value for this measured value or with a characteristic identification of the tires (2) is transmitted using extended data telegrams included in the second transmission signal (S2) from the wheel module (9) to the control device (3; 28).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A three-dimensional (3-D) memory, comprising:
a plurality of memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and
a plurality of channels, for electrically connecting the memory dies;
wherein, in a synchronous test, one of the memory dies is selected as a master die, the BIST circuit on the master die sends an enable signal to the memory dies under test via the channels, and the BIST circuits of the memory dies test the memory banks on one same memory die or on different memory dies.
2. The 3-D memory according to claim 1, wherein when testing the memory banks on the master die, the BIST circuit on the master die tests one of the memory banks on the master die, and the BIST circuit of at least one other memory die tests another of the memory banks on the master die.
3. The 3-D memory according to claim 1, wherein when testing one of the memory banks on the master die and one of the memory banks on another memory die, the BIST circuit on the master die tests the memory bank under test on the master die, and the BIST circuit on the another memory die tests the memory bank under test on the another memory die.
4. The 3-D memory according to claim 1, wherein when testing one of the memory banks on the master die and one of the memory banks on another memory die, the BIST circuit on the master die tests the memory bank under test on the another memory die, and the BIST circuit on the another memory die tests the memory bank under test on the master die.
5. The 3-D memory according to claim 1, wherein when testing the memory banks on another memory die, the BIST circuit on the master die tests one of the memory banks under test on the other memory dies, and the BIST circuit on another memory die tests another of the memory banks on another memory die.
6. A built-in self-test (BIST) circuit of a 3-D memory, comprising:
an inter-die synchronization module, for receiving an external test command to determine whether the BIST circuit operates in a master mode or in a slave mode; and
a test pattern generator, coupled to the inter-die synchronization module, for generating a test pattern;
wherein, when the BIST circuit operates in the master mode, the BIST circuit sends an enable signal of the external test command to the BIST circuits in the slave mode of the 3-D memory, so that the BIST circuits of the 3-D memory perform a synchronous test; and
when the BIST circuit operates in the slave mode, the BIST circuit receives the enable signal sent from the BIST circuit in the master mode, so that the BIST circuits of the 3-D memory perform the synchronous test.
7. The BIST circuit according to claim 6, wherein the inter-die synchronization module comprises:
a register, for temporarily storing the enable signal;
a tri-state buffer, coupled to the register, controlled by a tri-state buffer enable signal to output the enable signal temporarily stored in the register or to be in a high-impedance state; and
a multiplexer, coupled to the tri-state buffer and the test pattern generator, for outputting a ground signal, an output signal of the tri-state buffer or the enable signal outputted by another BIST circuit.
8. The BIST circuit according to claim 7, wherein
the tri-state buffer outputs the enable signal temporarily stored in the register when the BIST circuit operates in the master mode, and
the tri-state buffer is in the high-impedance state when the BIST circuit operates in the slave mode.
9. The BIST circuit according to claim 6, wherein the test pattern generator comprises a clock-domain-crossing-aware finite state machine (CDC-aware FSM) coupled to the inter-die synchronization module, and the CDC-aware FSM has an idle state, an execution state, a done state and a wait state.
10. The BIST circuit according to claim 9, wherein:
when the enable signal is enabled, the CDC-aware FSM enters the execution state from the idle state to execute a test task;
when the test task is completed, the CDC-aware FSM enters the done state from the execution state, and reports a test result to inform that the test task is completed;
when the enable signal is still enabled, the CDC-aware FSM enters the wait state from the done state; and
in response to the enable signal changing from enabled to disabled, the CDC-aware FSM returns to the idle state from the wait state.
11. The BIST circuit according to claim 6, further comprising at least one comparator, and a number of the comparator is associated with a number of memory banks on a same die as the BIST circuit.

1. A method of forming an integrated circuit device, comprising:
providing a substrate;
forming a capacitor on the substrate, the capacitor comprising a lower electrode on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric;
forming a first hydrogen barrier insulation layer on the upper electrode and on the substrate;
forming an etch stop layer on the first hydrogen barrier insulation layer;
etching the etch stop layer and the first hydrogen barrier insulation layer so as to substantially remove the etch stop layer and the hydrogen barrier insulation layer from the substrate;
forming a second hydrogen barrier insulation layer on the etch stop layer and on the substrate; and
etching the second hydrogen barrier insulation layer so as to form a hydrogen barrier spacer on a sidewall of the capacitor.
2. The method of claim 1, wherein forming the hydrogen barrier insulation layer comprises:
forming the hydrogen barrier insulation layer on the upper electrode and on the substrate; and
etching the hydrogen barrier insulation layer so as to substantially remove the hydrogen barrier insulation layer from the substrate.
3. The method of claim 2, wherein the hydrogen barrier insulation layer is a first hydrogen barrier insulation layer and wherein forming the hydrogen barrier spacer comprises:
forming a second hydrogen barrier insulation layer on the first hydrogen barrier insulation layer and on the substrate; and
etching the second hydrogen barrier insulation layer so as to form the hydrogen barrier spacer on the sidewall of the capacitor.
4. The method of claim 3, wherein the first hydrogen barrier insulation layer comprises aluminum oxide, titanium oxide, tantalum oxide, titanium nitride, silicon oxide, andor silicon without impurities.
5. The method of claim 3, wherein the second hydrogen barrier insulation layer comprises aluminum oxide, titanium oxide, tantalum oxide, titanium nitride, silicon oxide, andor silicon without impurities.
6. The method of claim 3, wherein the first hydrogen barrier insulation layer has a thickness of about 200\u20131000 \u212b.
7. The method of claim 3, wherein the second hydrogen barrier insulation layer has a thickness of about 100\u2013500 \u212b.
8. The method of claim 3, wherein the first and second hydrogen barrier insulation layers are formed using one of atomic layer deposition (ALD) and chemical vapor deposition (CVD).
9. The method of claim 1, wherein the etch stop layer comprises a P-TEOS layer.
10. The method of claim 1, wherein the capacitor is a stack-type capacitor.
11. The method of claim 1, wherein the capacitor is a cylinder-type capacitor.
12. A method of forming an integrated circuit device, comprising:
providing a substrate;
forming a capacitor on the substrate, the capacitor comprising a lower electrode on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric;
forming the hydrogen barrier insulation layer on the upper electrode and on the substrate;
etching the hydrogen barrier insulation layer so as to substantially remove the hydrogen barrier insulation layer from the substrate;
forming a liner layer on the first hydrogen barrier insulation layer and on the substrate;
forming a second hydrogen barrier insulation layer on the liner layer; and
etching the second hydrogen barrier insulation layer and the liner layer so as to form a hydrogen barrier spacer on the sidewall of the capacitor, the hydrogen barrier spacer comprising a second hydrogen barrier insulation layer spacer on a liner layer spacer.
13. The method of claim 12, wherein the liner layer comprises silicon nitride, silicon oxide, silicon carbide, tantalum oxide, andor titanium oxide.
14. The method of claim 12, wherein the liner layer is formed to a thickness of about 50\u2013100 \u212b.
15. The method of claim 12, wherein the capacitor is a stack-type capacitor.
16. The method of claim 12, wherein the capacitor is a cylinder-type capacitor.
17. An integrated circuit device, comprising:
a substrate;
a capacitor on the substrate, the capacitor comprising a lower electrode on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric;
a hydrogen barrier insulation layer on the upper electrode;
an etch stop layer on the hydrogen barrier insulation layer; and
a hydrogen barrier spacer on a sidewall of the capacitor.
18. The device of claim 17, wherein the hydrogen barrier insulation layer comprises aluminum oxide, titanium oxide, tantalum oxide, titanium nitride, silicon oxide, andor silicon without impurities.
19. The device of claim 17, wherein the hydrogen barrier spacer comprises aluminum oxide, titanium oxide, tantalum oxide, titanium nitride, silicon oxide, andor silicon without impurities.
20. The device of claim 17, wherein the hydrogen barrier insulation layer has a thickness of about 200\u20131000 \u212b.
21. The device of claim 17, wherein the etch stop layer comprises a P-TEOS layer.
22. An integrated circuit device, comprising:
a substrate;
a capacitor on the substrate, the capacitor comprising a lower electrode on the substrate, a dielectric layer on the lower electrode, and an upper electrode on the dielectric;
a first hydrogen barrier insulation layer on the upper electrode; and
a hydrogen barrier spacer on a sidewall of the capacitor, comprising:
a liner layer; and
a second hydrogen barrier layer on the liner layer.
23. The device of claim 22, wherein the liner layer comprises silicon nitride, silicon oxide, silicon carbide, tantalum oxide, andor titanium oxide.
24. The device of claim 22, wherein the liner layer has a thickness of about 50\u2013100 \u212b.
25. A method of manufacturing a capacitor of a semiconductor device including a hydrogen barrier spacer, the method comprising:
forming a lower structure including a transistor and a bit line on a semiconductor substrate;
depositing a first interlayer dielectric on the lower structure;
planarizing the first interlayer dielectric;
forming a capacitor on the first interlayer dielectric;
forming a hydrogen barrier spacer to cover a sidewall of an upper electrode, a dielectric layer, and a lower electrode of the capacitor;
curing etching damage caused during the formation of the hydrogen barrier spacer;
depositing a second interlayer dielectric on the surface of the semiconductor substrate where the hydrogen barrier spacer is formed;
planarizing the second interlayer dielectric; and
forming a metal contact in the second interlayer dielectric;
wherein forming the hydrogen barrier spacer comprises:
depositing a first hydrogen-barrier insulating layer on the semiconductor substrate where the capacitor upper electrode is formed;
forming a layer having an etch selectivity with respect to the first hydrogen barrier layer;
etching the first hydrogen-barrier insulating layer, the upper electrode, the dielectric layer, and the lower electrode;
depositing a second hydrogen-barrier insulating layer on the semiconductor substrate where the etching process is completed; and
etching the second hydrogen-barrier insulating layer using an anisotropic etch process to form the hydrogen barrier spacer on a sidewall of the upper electrode, the dielectric layer, and the lower electrode of the capacitor while leaving at least a portion of the layer having the etch selectivity on the first hydrogen-barrier insulating layer.
26. The method of claim 25, wherein the semiconductor device is a dynamic random access memory.
27. The method of claim 25, wherein the semiconductor device is a ferroelectric random access memory.
28. The method of claim 25, further comprising forming an etching stopper on the first interlayer dielectric.
29. The method of claim 25, wherein the upper electrode comprises ruthenium, iridium, platinum, rhodium, andor osmium.
30. The method of claim 25, wherein the lower electrode comprises ruthenium, iridium, platinum, rhodium, andor osmium.
31. The method of claim 25, further comprising performing a hydrogen thermal treatment after the metal contact is formed.
32. The method of claim 25, wherein the hydrogen barrier spacer comprises aluminum oxide.
33. The method of claim 25, wherein the hydrogen barrier spacer comprises titanium oxide, tantalum oxide, titanium nitride, silicon oxide, andor silicon without impurities.
34. The method of claim 25, wherein the capacitor is a stack-type capacitor.
35. The method of claim 25, wherein the capacitor is a cylinder-type capacitor.
36. The method of claim 25, wherein the first hydrogen-barrier insulating layer comprises aluminum oxide.
37. The method of claim 25, wherein the second hydrogen-barrier insulating layer comprises aluminum oxide.
38. The method of claim 25, wherein the first hydrogen-barrier insulating layer is formed to a thickness of about 200 \u212b to 1000 \u212b.
39. The method of claim 25, wherein the second hydrogen-barrier insulating layer is formed to a thickness of about 100 \u212b to 500 \u212b.
40. The method of claim 25, wherein the layer having an etch selectivity with respect to the first hydrogen-barrier layer is a P-TEOS layer.
41. The method of claim 25, wherein the anisotropic etching process for forming the hydrogen barrier spacer is performed so as to leave the first hydrogen-barrier insulating layer at a thickness of at least 100 \u212b on the capacitor upper electrode.
42. The method of claim 25, wherein curing etching damage caused during the formation of the hydrogen barrier spacer comprises plasma processing using O2, NH3, Ar, N2, andor N2O.
43. The method of claim 42, wherein the plasma processing comprises plasma processing using O2 at a temperature of about 300\xb0 C. to 500\xb0 C. at a pressure of about 1 Torr to 5 Torr, a plasma power supply range of about 500 W to 2000 W, a flow rate of about 1500 sccm to 3000 sccm, and a processing time of about 30 seconds to 3 minutes.
44. The method of claim 25, wherein curing etching damage caused during the formation of the hydrogen barrier spacer comprises thermal processing using O2, N2, N2O, andor O3.
45. A method of manufacturing a capacitor of a semiconductor device including a hydrogen barrier spacer, the method comprising:
forming a lower structure including a transistor and a bit line on a semiconductor substrate;
depositing a first interlayer dielectric on the lower structure;
planarizing the first interlayer dielectric;
forming a capacitor on the first interlayer dielectric;
forming a hydrogen barrier spacer to cover a sidewall of an upper electrode, a dielectric layer, and a lower electrode of the capacitor;
curing etching damage caused during the formation of the hydrogen barrier spacer;
depositing a second interlayer dielectric on the surface of the semiconductor substrate where the hydrogen barrier spacer is formed;
planarizing the second interlayer dielectric; and
forming a metal contact in the second interlayer dielectric;
wherein forming the hydrogen barrier spacer comprises:
depositing a first hydrogen-barrier insulating layer on the semiconductor substrate where the capacitor upper electrode is formed;
etching the first hydrogen-barrier insulating layer, the upper electrode, the dielectric layer, and the lower electrode;
forming an etch-stop liner layer on the semiconductor substrate where the etching process is completed;
depositing a second hydrogen-barrier insulating layer on the etch-stop liner layer; and
etching the second hydrogen-barrier insulating layer using an anisotropic etch process to form the hydrogen barrier spacer on a sidewall of the capacitor upper electrode, the dielectric layer, and the lower electrode.
46. The method of claim 45, wherein the first hydrogen-barrier insulating layer comprises aluminum oxide.
47. The method of claim 45, wherein the second hydrogen-barrier insulating layer comprises aluminum oxide.
48. The method of claim 45, wherein the etch-stop liner layer comprises a SiN layer, a SiO2 layer, a SiC layer, a Ta2O5 layer, andor a TiO2 layer.
49. The method of claim 45, wherein the first hydrogen-barrier layer and the second hydrogen-barrier each have a thickness of about 100 \u212b to 500 \u212b.
50. The method of claim 45, wherein the etch-stop liner layer has a thickness of about 50 \u212b to 100 \u212b.
51. The method of claim 45, wherein the anisotropic etching process for forming the hydrogen barrier spacer is performed using a dry etch process.
52. The method of claim 45, wherein the anisotropic etch process for forming the hydrogen barrier spacer is performed so as to leave the first hydrogen-barrier insulating layer at a thickness of at least 150 \u212b on the capacitor upper electrode.
53. A capacitor of a semiconductor device, comprising:
a semiconductor substrate;
a lower structure that defines a device isolation region on the semiconductor substrate and includes a transistor and a bit line;
a first interlayer dielectric (ILD) that covers the lower structure and where a planarization process is completed;
a capacitor formed on the first interlayer dielectric;
a hydrogen barrier spacer covering a sidewall of an upper electrode, a dielectric layer, and a lower electrode of the capacitor;
a first hydrogen-barrier insulating layer disposed on the upper electrode; and
a P-TEOS layer disposed on the first hydrogen-barrier insulating layer.
54. The capacitor of claim 53, further comprising an etch stop layer between the first interlayer dielectric and the capacitor.
55. The capacitor of claim 53, wherein the capacitor is a cylinder-type capacitor.
56. The capacitor of claim 53, wherein the capacitor is a stack-type capacitor.
57. The capacitor of claim 53, wherein the upper electrode and the lower electrode comprise ruthenium, iridium, platinum, rhodium, andor osmium.
58. The capacitor of claim 53, wherein the hydrogen barrier spacer comprises Al2O3.
59. The capacitor of claim 53, wherein the hydrogen barrier spacer comprises TiO2, Ta2O5, TiN, SiO2, andor silicon without impurities.
60. A capacitor of a semiconductor device, comprising:
a semiconductor substrate;
a lower structure that defines a device isolation region on the semiconductor substrate and includes a transistor and a bit line;
a first interlayer dielectric (ILD) that covers the lower structure and where a planarization process is completed;
a capacitor formed on the first interlayer dielectric; and
a hydrogen barrier spacer covering a sidewall of an upper electrode, a dielectric layer, and a lower electrode of the capacitor;
a first hydrogen-barrier insulating layer disposed on the upper electrode; and
a liner layer disposed between sidewalls of the upper electrode, the dielectric layer, and the lower electrode of the capacitor and the hydrogen barrier spacer.
61. The capacitor of claim 60, wherein the liner layer comprises a SiN layer, a SiO2 layer, a SiC layer, a Ta2O5 layer, andor a TiO2 layer.
62. The capacitor of claim 60, wherein the liner layer has a thickness of about 50 \u212b to 100 \u212b.
63. The capacitor of claim 53, wherein the hydrogen barrier spacer is disposed directly on the exposed sidewall of the capacitor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device (24) for 3D-originated cardiac roadmapping, comprising
a processing unit (26);
an interface unit (28); and
a display (30);
wherein the interface unit (28) is adapted to provide 3D+t image data of a vascular structure of an object; and to provide 2D image data of the object, which object comprises the vascular structure, the 2D image data comprising at least one 2D image;
wherein the processing unit (26) is adapted to project the vascular structure, thereby generating a plurality of mask images on the basis of the 3D+t image data; to register the at least one 2D image with one of the plurality of the mask images; wherein the registration comprises finding the maximum of a similarity factor between the mask images and the at least one 2D image; and to generate a combination of the at least one 2D image and a projection of the vascular structure on the basis of the 3D+t image data according to the registration;
wherein the display (30) is adapted to display the combination as a guiding vessel tree projection; and
wherein an element (38) is located inside the vascular structure (202), which element is visible in the 2D image data (118); and wherein the registration is based upon the element.
2. A medical imaging system (10) for examination of an object of interest, comprising:
the device (24) for 3D-originated cardiac roadmapping according to claim 1; and
X-ray image acquisition means (12);
wherein the acquisition means (12) are adapted to acquire the 2D image data of the object, which object comprises the vascular structure, the 2D image data comprising at least one 2D image.
3. A method (100) for 3D-originated cardiac roadmapping for examination of an object of interest, the method comprising the steps of:
a) providing (112) 3D+t image data (114) of a vascular structure (202) of an object;
b) acquiring (116) 2D image data (118) of the object, which object comprises the vascular structure, the 2D image data comprising at least one 2D image;
c) projecting (120) the vascular structure, thereby generating a plurality of mask images (122) on the basis of the 3D+t image data;
d) registering (124) the at least one 2D image with one of the plurality of the mask images;
wherein the registration comprises finding (126) the maximum of a similarity factor between the mask images and the at least one 2D image;
e) generating (128) a combination (130) of the at least one 2D image and a projection of the vascular structure on the basis of the 3D+t image data according to the registration; and
f) displaying (132) the combination as a guiding vessel tree projection (134);
wherein an element (38) is located inside the vascular structure (202), which element is visible in the 2D image data (118); and wherein the registration is based upon the element.
4. (canceled)
5. Method according to claim 3, wherein the 3D+t image data comprises a phase reference signal; wherein the plurality of 2D mask images each comprises a phase indicator; and wherein for the registration of the 2D image, from the plurality of the 2D mask images only images with a corresponding phase reference are selected.
6. Method according to claim 3, wherein the 3D+t image data represents a volume comprising at least a part of the vascular structure, which vascular structure comprises a tree-like structure (212) with a plurality of sub-trees (214); and wherein before step c) the volume is divided (152) into a plurality of sub-volumes (154), each sub-volume containing a separate sub-tree (214); and wherein in step c) mask images (122\u2032) are generated (120\u2032) for at least one of the plurality of sub-volumes.
7. Method according to claim 3, wherein before step c) at least one sub-volume is selected (154\u2033); and wherein in step c) mask images (122\u2033) are generated (120\u2033) for the selected at least one sub-volume; and wherein in step d), only mask images of the selected sub-volumes are used for the registration (124\u2033).
8. Method according to claim 4, wherein the element is identified and localized in the 2D image.
9. Method according to claim 3, wherein the vascular structure with its vessel volumes is determined (158) by vessel segmentation (160) on the basis of the 3D+t image data; and wherein the 2D image is registered such that an element in the 2D image is positioned inside a vessel of the vascular structure.
10. Method according to claim 3, wherein the vascular structure with its vessel volumes is determined by generating (162) a model (164) from the 3D+t image data; and wherein the 2D image is registered such that an element in the 2D image is positioned inside a vessel of the vascular structure.
11. Method according to claim 3, wherein the volume, which is represented by the 3D+t image data and which comprises at least a part of the vascular structure, comprises a tree-like structure; and wherein a plurality of sub-trees (166) and branches (168) are determined (170); and wherein the sub-tree (166\u2032) is determined (172) in which an element is positioned; and wherein based on the determined sub-tree, a portion (174) of the vascular structure is selected and visualized (176) in the projection for the combination in step e).
12. Method according to claim 11, wherein the non-selected branch portions are pruned off and wherein the vascular structure is displayed with the selected portion only.
13. A computer program element for controlling an apparatus according to claim 1.
14. A computer readable medium having stored the program element of claim 13.