Author: claimsbot

1. A method of operation in an integrated circuit memory device that includes an array of memory cells, wherein the method comprises:
receiving an external clock signal;
receiving information that specifies that the memory device perform a memory write operation;
in response to the information, receiving a first data value after a time gap;
receiving a second data value after receiving the first data value, wherein the first and second data values are received using a set of pins;
receiving a first mask bit and a second mask bit, wherein the first and second mask bits are received in succession during a clock cycle of the external clock signal using a pin on the memory device, wherein the first mask bit indicates whether to write the first data value to the array during the memory write operation and the second mask bit indicates whether to write the second data value to the array during the memory write operation.
2. The method of claim 1, wherein:
when the first mask bit indicates that the first data value is to be written to the array, writing the first data value to the array during the memory write operation; and
when the second mask bit indicates that the second data is to be written to the array, writing the second data value to the array during the memory write operation.
3. The method of claim 1, further including:
receiving a plurality of control signals that specify that the memory device perform a row sensing operation; and
during the row sensing operation, sensing a row of the array of memory cells.
4. The method of claim 3, wherein:
when the first mask bit indicates that the first data value is to be written, writing the first data value to a first memory location in the row of memory cells; and
when the second mask bit indicates that the second data value is to be written, writing the second data value to a second memory location in the row of memory cells.
5. The method of claim 4, wherein the first memory location is identified by a column address.
6. The method of claim 1, wherein the memory device is a dynamic random access memory device.
7. The method of claim 1, further including receiving error detection and correction information on the pin.
8. The memory device of claim 1, wherein the information also specifies whether to precharge a plurality of sense amplifiers used in writing at least one of the first and second data values to the array.
9. The method of claim 8, wherein a first control value is encoded in the information to specify that the precharge operation is performed automatically following the memory write operation.
10. The method of claim 1, wherein the information is included in a request packet, wherein receiving the information further comprises receiving the request packet using the set of pins.
11. The method of claim 10, wherein the request packet includes a third mask bit and address information, wherein the third mask bit indicates whether to write a third data value to the array of memory cells.
12. The method of claim 11, further including receiving the third data value before receiving the first data value.
13. The method of claim 1, wherein:
the first data value is received during a first half of the clock cycle of the external clock signal; and
the second data value is received during a second half of the clock cycle of the external clock signal.
14. The method of claim 1, further including:
receiving a third mask bit along with the first data value, wherein the third mask bit indicates whether to write a third data value to the array; and
receiving a fourth mask bit along with the second data value wherein the fourth mask bit indicates whether to write a fourth data value to the array.
15. The method of claim 1, wherein the pin is not included in the set of pins.
16. A semiconductor memory device that includes an array of memory cells, wherein the memory device comprises:
a set of interface terminals to receive information which specifies that, after a time gap, the memory device receive a first set of data bits followed by a second set of data bits; and
a terminal to receive;
a first mask bit during a first half of a clock cycle of an external clock signal, the first mask bit indicating whether the first set of data bits is to be written to the array; and
a second mask bit during a second half of the clock cycle of the external clock signal, the second mask bit indicating whether the second set of data bits is to be written to the array.
17. The memory device of claim 16, wherein the memory cells are dynamic random access memory cells.
18. The memory device of claim 16, wherein the memory device receives error detection and correction information on the terminal.
19. The memory device of claim 16, wherein:
the first set of data bits is received at a time offset from receipt of the first mask bit; and
the second set of data bits is received at a time offset from receipt of the second mask bit.
20. The memory device of claim 16, further including a plurality of pins to receive the first set of data bits and the second set of data bits from a set of external signal lines.
21. The memory device of claim 16, wherein:
the first and second mask bits are received during a first clock cycle of the external clock signal;
the first set of data bits is received during a first half of a second clock cycle of the external clock signal; and
the second set of data bits is received during a second half of the second clock cycle of the external clock signal.
22. The memory device of claim 16, further including a plurality of pins, coupled to the set of interface terminals, to receive the information.
23. The memory device of claim 16, wherein both the first set of data bits and the second set of data bits are received on the set of interface terminals.
24. The memory device of claim 16, wherein the information is received during a first clock cycle of the external clock signal, and the first and second sets of data bits are received during a second clock cycle of the external clock signal.
25. The memory device of claim 16, wherein the terminal also receives a data bit, wherein the first mask bit, the second mask bit and the data bit are received by the terminal in a multiplexed format.
26. The memory device of claim 16, further including a set of pins to receive the first and second sets of data bits in succession during a clock cycle of the external clock signal.
27. The memory device of claim 16, wherein the information is included in a request packet.
28. The memory device of claim 27, wherein the request packet includes a third mask bit, a fourth mask bit and address information.
29. The memory device of claim 28, wherein:
the third mask bit indicates whether a third set of data bits is to be written to the array; and
the fourth mask bit indicates whether a fourth set of data bits is to be written to the array.
30. The memory device of claim 29, wherein the third and fourth mask bits are received using the set of interface terminals.
31. A method of controlling a semiconductor memory device, wherein the memory device includes an array of memory cells, wherein the method comprises:
providing a first control value to the memory device that indicates that the memory device, after a time gap, receive a first set of data bits and a second set of data bits;
after the time gap and during a first half of a clock cycle of an external clock signal, providing a first mask bit to the memory device, wherein the first mask bit indicates whether to write the first set of data bits to the array; and
during a second half of the clock cycle of the external clock signal, providing a second mask bit to the memory device, wherein the second mask bit indicates whether to write the second set of data bits to the array.
32. The method of claim 31, wherein providing the first control value further comprises encoding the first control value to indicate whether the memory device should precharge sense amplifiers used in writing at least one of the first and second sets of data bits to the array.
33. The method of claim 31, further including:
providing the first set of data bits to the memory device; and
providing the second set of data bits to the memory device.
34. The method of claim 31, further including providing information to the memory device that instructs the memory device to ignore the first and second mask bits.
35. The method of claim 34, further including providing a control signal to the memory device that causes the information to be stored in a register on the memory device.
36. The method of claim 31, wherein providing the first and second mask bits to the memory device further comprises providing the first and second mask bits to the memory device over a single signal line.
37. The method of claim 31, further including providing a second control value to the memory device, wherein the second control value indicates that the memory device is to transfer data stored in a row of the array of memory cells to a row of sense amplifiers.
38. The method of claim 31, further including:
providing a third mask bit to the memory device, wherein the third mask bit is provided concurrently with the first set of data bits and indicates whether to write a third set of data bits to the array;
providing a fourth mask bit to the memory device, wherein the fourth mask bit is provided concurrently with the second set of data bits and indicates whether to write a fourth set of data bits to the array.
39. The method of claim 38, further including:
providing the first and second sets of data bits to the memory device during a first clock cycle of the external clock signal; and
providing the third and fourth sets of data bits to the memory device during a second clock cycle of the external clock signal.
40. The method of claim 31, wherein providing the control value further comprises providing a request packet that includes the control value.
41. A semiconductor memory device, comprising:
an array of memory cells;
a plurality of pins to receive control information that specifies that, after a time gap, the memory device receive data; and
an input pin to receive:
a first mask bit during a first half of a clock cycle of an external clock signal, wherein the first mask bit indicates whether to write a first portion of the data to the array; and
a second mask bit during a second half of the clock cycle of the external clock signal, wherein the second mask bit indicates whether to write a second portion of the data to the array.
42. The memory device of claim 41, further including a plurality of pins to receive the data.
43. The memory device of claim 41, wherein the array of memory cells includes dynamic random access memory cells.
44. The memory device of claim 41, wherein the input pin further receives a bit of data, and wherein the first mask bit, the second mask bit and the bit of data are received from the input pin in a multiplexed format.
45. The memory device of claim 41, wherein the control information is included in a request packet.
46. A semiconductor memory device including an array of memory cells, wherein the memory device comprises:
means for receiving a first data value and a second data value;
means for receiving:
a first mask bit that indicates whether to write the first data value to the array during an internal memory write operation; and
a second mask bit that indicates whether to write the second data value to the array during the internal memory write operation,
wherein the first and second mask bits are received during a clock cycle of an external clock signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An isolated Scheffersomyces stipitis having been deposited with the United States Department of Agriculture, Agricultural Research Patent Culture Collection as Accession Deposit Number NRRL Y-50472.
2. A method of producing ethanol comprising culturing yeast strain NRRL Y-50472 under suitable conditions for a period of time sufficient to allow fermentation of at least a portion of feedstock to ethanol.
3. The method of claim 2 in which the feedstock includes cellobiose and glucose and the yeast strain NRRL Y-50472 is cultured under anaerobic conditions.
4. The method of claim 2 wherein the yeast strain NRRL Y-50472 is cultured under microaerophilic conditions to ferment cellobiose.
5. The method of claim 2 wherein the yeast strain NRRL Y-50472 is cultured under anaerobic or aerobic conditions to ferment cellobiose.
6. The method of claim 2 wherein the yeast strain NRRL Y-50472 is cultured under aerobic conditions to ferment a combination of xylose, cellobiose and glucose.

1. An interior part mounting clip for mounting an interior part on a panel member, comprising:
a pin portion having a smaller external diameter than He an internal diameter of a mounting hole formed in a frame-shaped mounting seat formed on the interior part.
the pin portion being inserted into and movable in the mounting hole of the frame-shaped mounting seat:
a head portion being formed at one end of the pin portion, the head portion engaging with the mounting seat and including:
at least three protrusions protruding radially outward of the pin portion; and

an outer frame mounted to be elastically displacable relative to the pin portion through a plurality of elastic portions extending radially outward from at least part of the pin portion which is positioned among the at least three protrusions an outer circumference of the outer frame abutting against an inner circumference of the frame-shaped mounting seat and engaging with a circumferential edge of the mounting hole, and
a stem portion formed at the other end of the pin portion and engaging with an engaging hole formed in the panel member.
2. The interior part mounting clip according to claim 1, wherein the protrusions of the head portion and the elastic portions are protruded radially outward through a head flange portion protruding radially outward of the pin portion.
3. The interior part mounting clip according to claim 2, wherein a height of a side of each elastic portion to face the interior part, when each elastic portion is engaged with the mounting seat, is smaller than a height of the head flange portion and the outer frame.
4. The interior part mounting clip according to claim 2, wherein a height of a side of each protrusion to face the interior part, when each protrusion is engaged with the mounting seat, is smaller than a height of the head flange portion.
5. The interior part mounting clip according to claim 3, wherein a height of a side of each protrusion to face the interior part, when each protrusion is engaged with the mounting seat, is smaller than a height of the head flange portion.
6. The interior part mounting clip according to claim 1, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat, is defined by a following expression:
L=A\u2212B+C,

wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole is defined by C.
7. The interior part mounting clip according to claim 2, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion when the head portion engages with the mounting seat is defined by a following expression:
L=A\u2212B+C.
wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole, is defined by C.
8. The interior part mounting clip according to claim 3, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat, is defined by a following expression:
L=A\u2212B+C.

wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion when each engaging portion engages with the mounting hole, is defined by C.
9. The interior part mounting clip according to claim 4, wherein a protrusion length of each protrusion radially outward from an outer circumference of the pin portion, when the head portion engages with the mounting seat is defined by a following expression:
L=A\u2212B+C.

wherein the internal diameter of the mounting hole of the mounting seat is defined by A,
wherein the external diameter of the pin portion is defined by B, and
wherein a length of each engaging portion, when each engaging portion engages with the mounting hole, is defined by C.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An integrated circuit, comprising:
a plurality of cells;
an electrical bus in electrical communication with said plurality of cells, said electrical bus designed using a current distribution modeled prior to arrangement of said plurality of cells, said electrical bus comprising:
a region; and
a first metal layer containing a plurality of first wires extending in a first direction, each of said plurality of first wires having a first width at least partially located within said region;

wherein said first widths vary as a function of said current distribution.
2. An integrated circuit according to claim 1, wherein said region is rectangular in shape and has an axis of symmetry, each of said plurality of first wires being parallel to said axis of symmetry.
3. An integrated circuit according to claim 2, wherein said first widths of said plurality of first wires generally decrease toward said axis of symmetry.
4. An integrated circuit according to claim 3, wherein said first widths decrease logarithmically toward said axis of symmetry.
5. An integrated circuit according to claim 1, further comprising a second metal layer containing a plurality of second wires extending in a second direction different from said first direction, said plurality of second wires electrically coupled to said plurality of first wires, each of said plurality of second wires having a second width at least partially located within said region, said second widths varying in proportion to said current distribution.
6. An integrated circuit according to claim 5, wherein said region is rectangular in shape and has a first axis of symmetry and a second axis of symmetry, each of said plurality of first wires being parallel to said first axis of symmetry and each of said plurality of second wires being parallel to said second axis of symmetry.
7. An integrated circuit according to claim 6 wherein said first widths generally decrease toward said first axis of symmetry and said second widths generally decrease toward said second axis of symmetry.
8. An integrated circuit according to claim 7, wherein said first widths decrease logarithmically toward said first axis of symmetry and said second widths decrease logarithmically toward said second axis of symmetry.
9. A device, comprising:
a semiconductor chip containing a plurality of cells and having at least one electrical bus designed using a current distribution modeled prior to arrangement of said plurality of cells, said semiconductor chip comprising:
an area array of electrical contacts; and
a plurality of regions defined by said area array, each of said plurality of regions containing a first metal layer having a plurality of first wires extending in a first direction and electrically coupled to said electrical contacts, each of said plurality of first wires having a first width;
wherein said first widths of said first wires vary in each of said plurality of regions as a function of said current distribution; and
a power supply in electrical communication with said semiconductor chip.
10. A device according to claim 9, wherein said plurality of first wires in a first of said plurality of regions is identical to said plurality of first wires in others of said plurality of regions.
11. A device according to claim 9, wherein said plurality of first wires are linear and each of said plurality of regions is rectangular in shape and has an axis of symmetry parallel to each of said plurality of first wires.
12. A device according to claim 11, wherein said first widths of said plurality of first wires generally decrease toward said axis of symmetry.
13. A device according to claim 12, wherein said first widths decrease logarithmically toward said axis of symmetry.
14. A device according to claim 9, wherein each of said plurality of regions further comprises a second metal layer containing a plurality of second wires extending in a second direction different from said first direction, each of said plurality of second wires electrically coupled to said electrical contacts and having a second width, said second widths varying in proportion to said current distribution.
15. A device according to claim 14, wherein each of said plurality of first wires is linear and each of said plurality of second wires is linear, each of said plurality of regions being rectangular in shape and having a first axis of symmetry parallel to each of said plurality of first wires and a second axis of symmetry parallel to each of said plurality of second wires.
16. A device according to claim 15 wherein said first widths generally decrease toward said first axis of symmetry and said second widths generally decrease toward said second axis of symmetry.
17. A device according to claim 16, wherein said first widths decrease logarithmically toward said first axis of symmetry.
18. A device according to claim 16, wherein said second widths decrease logarithmically toward said second axis of symmetry.
19. A method of laying out an electrical bus grid of an integrated circuit having a plurality of regions, comprising in sequence the steps of:
arranging at least a plurality of first wires of a first metal layer in at least one of the plurality of regions, each of said plurality of first wires having a first width;
determining a current distribution among at least said plurality of first wires;
varying at least said first widths of said plurality of first wires as a function of said current distribution; and
arranging a plurality of cells to at least partially form the integrated circuit.
20. A method according to claim 19, wherein the step of arranging said plurality of first wires includes selecting a pattern of said plurality of first wires and repeating said pattern for at least some of the plurality of regions.
21. A method according to claim 19, wherein the step of determining current distribution includes modeling said plurality of wires as resistors.
22. A method according to claim 19, wherein the area array of electrical contacts is a rectangular array such that each of said plurality of regions has an axis of symmetry, said step of arranging said plurality of wires including arranging said plurality of wires so they are parallel to said axis of symmetry and said step of varying said first widths includes decreasing said first widths toward said axis of symmetry.
23. A method according to claim 22, wherein said step of varying said first widths includes decreasing said first widths logarithmically toward said axis of symmetry.
24. A method according to claim 19, wherein the step of arranging at least a plurality of first wires further includes arranging a plurality of second wires of a second metal layer in said at least one of the plurality of regions, each of said plurality of second wires having a second width, the step of determining a current distribution among at least a plurality of first wires includes determining a current distribution among at least said plurality of first wires and said plurality of second wires, and the step of varying at least said first widths of said plurality of first wires includes varying said first widths of said plurality of first wires and said second widths of said plurality of second wires as a function of said current distribution.
25. A method according to claim 24, wherein said at least one of the plurality of regions has an axis of symmetry parallel to said plurality of first wires and the step of varying at least said first widths includes decreasing said first widths logarithmically toward said axis of symmetry.
26. A method according to claim 24, wherein said at least one of the plurality of regions has an axis of symmetry parallel to said plurality of second wires and the step of varying at least said second widths includes decreasing said second widths logarithmically toward said axis of symmetry.
27. An integrated circuit having a plurality of cells, comprising:
a plurality of electrical contacts;
an electrical bus grid formed among said plurality of electrical contacts, said bus grid comprising:
a first metal layer;
a second metal layer spaced from said first metal layer;
a plurality of first wires located in said first metal layer and extending in a first direction; and
a plurality of second wires located in said second metal layer and extending in a second direction different from said first direction so as to form a crisscross pattern with said plurality of first wires;
wherein at least one of said plurality of first wires and said plurality of second wires contain wires having widths that differ based upon current flow therein.
28. An integrated circuit according to claim 27, wherein both of said plurality of first wires and said plurality of second wires contain wires having widths that differ based upon current flow therein.
29. An integrated circuit, comprising:
an area array of electrical contacts defining a plurality of contiguous rectangular regions each having a first axis of symmetry and a second axis of symmetry transverse to said first axis of symmetry; and
an electrical bus grid formed within each of said contiguous rectangular regions, said repeatable electrical bus grid comprising:
a first metal layer electrically connected to said electrical contacts;
a plurality of first wires located in said first metal layer and extending parallel to said first axis of symmetry and spaced laterally from one another;
wherein said plurality of first wires in each of said contiguous rectangular region have first widths that generally decrease in a direction toward said first axis of symmetry.
30. An integrated circuit according to claim 29, wherein said first widths decrease logarithmically to said first axis of symmetry.
31. An integrated circuit according to claim 30, further comprising a second metal layer spaced from said first metal layer and a plurality of second wires located in said second metal layer and extending parallel to said second axis of symmetry and spaced laterally from one another, said plurality of second wires being electrically connected to said plurality of first wires and having second widths that generally decrease in a direction toward said second axis of symmetry.
32. An integrated circuit according to claim 31, wherein said first widths decrease logarithmically toward said first axis of symmetry and said second widths decrease logarithmically toward said second axis of symmetry.