Author: claimsbot

1. An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter during a first sampling period in which the reflected voltage is sampled without filtering and a second sampling period during which the reflected voltage is sampled with filtering, comprising:
a first switch for receiving the reflected voltage, said first switch being controlled to enable sampling during the first and second sampling periods;
a capacitor coupled to the first switch for holding the reflected voltage when the first switch is closed;
a resistor coupled to the first switch; and
a second switch coupled to the resistor, said second switch being controlled to disable filtering during the first sampling period and to enable sampling during the second sampling period;
wherein, during the first sampling period, the reflected voltage is sampled and held directly by the capacitor without filtering, and
wherein, during the second sampling period, the resistor and the capacitor form a filter for filtering the reflected voltage held by the capacitor.
2. The adaptive filter circuit as claimed in claim 1, wherein the first sampling period and the second sampling period are determined by turning on and turning off the first switch and the second switch.
3. The adaptive filter circuit as claimed in claim 1, wherein the second period starts after an end of the first sampling period.
4. The adaptive filter circuit as claimed in claim 1, wherein the reflected voltage is sampled to generate a feedback signal for the power converter; the reflected voltage is correlated to an output voltage of the power converter.
5. The adaptive filter circuit as claimed in claim 1, wherein the first switch is turned on during the first sampling period and the second sampling period.
6. The adaptive filter circuit as claimed in claim 1, wherein the second switch is turned off during the second sampling period.
7. The adaptive filter circuit as claimed in claim 1, wherein the second switch is coupled to the resistor in parallel.
8. The adaptive filter circuit as claimed in claim 4, wherein the feedback signal is a voltage-feedback signal.
9. An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter during a first sampling period in which the reflected voltage is sampled without filtering and a second sampling period during which the reflected voltage is sampled with filtering, comprising:
a sample-and-hold circuit coupled to sample the reflected voltage; and
a filter coupled to the sample-and-hold circuit;
wherein during a first period of the reflected voltage, the reflected voltage is sampled by the sample-and-hold circuit without filtering by the filter; and
wherein, during a second period of the reflected voltage, the reflected voltage is sampled by sample-and-hold circuit and filter by the filter.
10. The adaptive filter circuit as claimed in claim 9, wherein the second period starts after an end of the first period.
11. The adaptive filter circuit as claimed in claim 9, wherein the filter is enabled during the second period.
12. The adaptive filter circuit as claimed in claim 9, wherein the filter is disabled during the first period.
13. The adaptive filter circuit as claimed in claim 9, wherein the filter is connected to a first switch and a second switch, said first switch being controlled to enable sampling during the first and second sampling periods, and said second switch being controlled to disable filtering during the first sampling period and to enable sampling during the second sampling period.
14. The adaptive filter circuit as claimed in claim 13, wherein the filter further comprises a resistor and a capacitor, and the resistor is coupled in parallel to the second switch.
15. The adaptive filter circuit as claimed in claim 13, wherein the first switch is turned on in the first period and in the second period, and the second switch is turned on in the first period and turned off in the second period.
16. An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter during a first sampling period in which the reflected voltage is sampled without filtering and a second sampling period during which the reflected voltage is sampled with filtering, comprising:
a first switch for receiving the reflected voltage, said first switch being controlled to enable sampling during the first and second sampling periods;
a filter coupled to the first switch and comprising a resistor and a capacitor for sampling the reflected voltage; and
a second switch coupled to the resistor in parallel such said second switch controls whether said filter filters the reflected voltage during said first and second sampling periods;
wherein the reflected voltage is sampled without filtering by the filter in a first period during a discharge period of the transformer; and the reflected voltage is sampled with filtering by the filter in a second period during the discharge period of the transformer.
17. The adaptive filter circuit as claimed in claim 16, wherein the first period and the second period are determined by the first switch and the second switch.
18. The adaptive filter circuit as claimed in claim 16, wherein the first switch is turned on during the first period and the second period.
19. The adaptive filter circuit as claimed in claim 16, wherein the second switch is turned off during the second period.
20. A method for sampling a reflected voltage of a transformer of a power converter, comprising:
receiving the reflected voltage after a switching signal is disabled;
disabling a ringing signal filtering module in a first period, wherein during the first period the sampled reflected voltage comprises ringing signals;
enabling the ringing signal filtering module to filter the ringing signals in a second period, wherein during the second period the ringing signals of the sampled reflected voltage are eliminated;
wherein the ringing signal filtering module is coupled to receive the reflected voltage, and the switching signal is used for switching the transformer.
21. The method as claimed in claim 20, wherein the ringing signal filtering module comprises a filter circuit coupled to the reflected voltage, and a sample-and-hold circuit coupled to the filter.
22. The method as claimed in claim 21, wherein the filter circuit comprises a filter, and a switch coupled to the filter.
23. The method as claimed in claims in 21, wherein disabling a ringing elimination module in a first period comprises disabling the filter circuit.
24. The method as claimed in claim 23, wherein disabling the filter circuit comprises controlling a switch connected in parallel with a resistor in the filter circuit.
25. The method as claimed in claims in 21, wherein enabling the ringing elimination module in a second period comprises enabling the filter circuit.
26. The method as claimed in claim 25, wherein enabling the filter circuit comprises controlling a switch connected in parallel with a resistor in the filter circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A current perpendicular-to-the-plane magnetoresistance (CPP-MR) read head having a stacked structure, comprising:
a spin valve arrangement;
a transverse bias means for providing a transverse bias to the spin valve arrangement.
2. The CPP-MR read head of claim 1, wherein said transverse bias means is an in-stack anti-parallel bias (AP-bias) layer.
3. The CPP-MR read head of claim 2, wherein said in-stack AP-bias layer includes first and second ferromagnetic layers having magnetization directions arranged to be opposite from each other.
4. The CPP-MR read head of claim 1, further comprising:
a longitudinal bias means for providing a longitudinal bias to the spin valve arrangement.
5. The CPP-MR read head of claim 4, wherein said longitudinal bias means is an in-stack conductive spacer layer.
6. The CPP-MR read head of claim 5, wherein said in-stack conductive spacer layer is composed of a material that causes a strong spin memory loss for conduction electrons passing through the CPP-MR read head.
7. The CPP-MR read head of claim 4, wherein said longitudinal bias means is an out-of-stack layer coupled to the spin valve arrangement to provide a longitudinal biasing to the spin valve arrangement.
8. The CPP-MR read head of claim 4, wherein said longitudinal bias means is a permanent magnet arrangement.
9. The CPP-MR read head of claim 4, wherein said longitudinal bias means is a structure that is placed in an overlaid arrangement with respect to the spin valve arrangement.
10. A magnetoresistance read head having a stacked structure, comprising:
a fixed layer having a magnetization direction pinned in a particular direction;
a free layer having a magnetization that is free to rotate in varying directions;
an in-stack transverse bias arrangement providing a transverse bias to the free layer.
11. The read head of claim 10, wherein said in-stack transverse bias arrangement is an anti-parallel bias (AP-bias) layer.
12. The read head of claim 11, wherein said AP-bias layer includes first and second ferromagnetic layers having magnetization directions arranged to be opposite from each other.
13. The read head of claim 10, further comprising:
a longitudinal bias arrangement providing a longitudinal bias to the free layer.
14. The read head of claim 13, wherein said longitudinal bias arrangement is an in-stack conductive spacer layer.
15. The read head of claim 14, wherein said in-stack conductive spacer layer is composed of materials that cause a strong spin memory loss for conduction electrons passing through the read head.
16. The read head of claim 13, wherein said longitudinal bias arrangement is an out-of-stack layer coupled to the free layer to provide a longitudinal biasing to the free layer.
17. The read head of claim 16, wherein said longitudinal bias arrangement is a permanent magnet arrangement.
18. The read head of claim 16, wherein said longitudinal bias arrangement is a structure that is placed in an overlaid arrangement with respect to the free layer.
19. The read head of claim 10, further comprising:
a magnetoresistance (MR) promoting layer composed of high resistivity materials and situated adjacent to the fixed layer.
20. The read head of claim 19, further comprising:
a second magnetoresistance (MR) promoting layer composed of high resistivity materials and situated adjacent to the free layer.
21. The read head of claim 10, further comprising:
a magnetoresistance (MR) promoting layer composed of high resistivity materials and situated within the fixed layer.
22. The read head of claim 21, further comprising:
a second magnetoresistance (MR) promoting layer composed of high resistivity materials and situated within the free layer.
23. The read head of claim 10, wherein the free layer is wider than the pinned layer in a direction of a track to be read by the read head.
24. A method of magnetically biasing a current perpendicular-to-the-plane magnetoresistance (CPP-MR) read head having a stacked structure, comprising:
generating a current in a spin valve structure in the CPP-MR read head;
magnetically biasing a free layer of the spin valve structure; and
magnetically counter-biasing the free layer with an in-stack transverse bias arrangement.
25. The method of claim 24, wherein the in-stack transverse bias arrangement used in the step of magnetically counter-biasing a free layer is an anti-parallel bias (AP-bias) layer.
26. The method of claim 25, wherein the AP-bias layer used in the step of magnetically counter-biasing a free layer includes first and second ferromagnetic layers having magnetization directions arranged to be opposite from each other.
27. The method of claim 24, further comprising:
magnetically biasing the free layer of the spin valve structure in a longitudinal direction with a longitudinal bias arrangement.
28. The method of claim 27, wherein the longitudinal bias arrangement used in the step of magnetically biasing the free layer is an in-stack conductive spacer layer.
29. The method of claim 28, wherein the in-stack conductive spacer layer is composed of a material that causes a strong spin memory loss for conduction electrons passing through the CPP-MR read head.
30. The method of claim 27, wherein the longitudinal bias arrangement used in the step of magnetically biasing the free layer is provided as an out-of-stack layer coupled to the spin valve structure to provide a longitudinal biasing to the free layer of the spin valve structure.
31. The method of claim 27, wherein the longitudinal bias arrangement is a permanent magnet arrangement.
32. The method of claim 27, wherein the longitudinal bias arrangement is situated in an overlaid arrangement with respect to the spin valve structure.
33. The method of claim 24, further comprising:
providing at least one magnetoresistance (MR) promoting layer composed of high resistivity materials within the stacked structure of the read head.
34. The method of claim 26, wherein the first and second ferromagnetic layers of the AP-bias layer have respective saturation magnetic moments that differ from each other, so that an APnet value of the AP-bias layer is not zero.

1. A position sensor system, comprising:
a first set of magnets, each magnet in the first set of magnets spaced apart from at least one other magnet in the first set of magnets by a first linear distance;
a first sensor associated with and movable relative to the first set of magnets, the first sensor configured to sense a preset linear distance and generate a first sensor linear output signal in response to relative linear movement between the first sensor and the first set of magnets, wherein the first sensor linear output signal repeats each time the first sensor travels the first linear distance;
a second set of magnets, each magnet in the second set of magnets spaced apart from at least one other magnet in the second set of magnets by a second linear distance, the second linear distance unequal to the first linear distance;
a second sensor associated with and movable relative to the second set of magnets, the second sensor configured to sense the preset linear distance and generate a second sensor linear output signal in response to relative linear movement between the second sensor and the second set of magnets, wherein the second sensor linear output signal repeats each time the second sensor travels the second linear distance; and
a processor coupled to receive the first and second sensor linear output signals and configured, in response thereto, to generate a position signal.
2. The system of claim 1, wherein the processor is configured to:
determine a difference between the first and second sensor linear output signals; and
generate the position signal based on the first sensor linear output signal and the difference between the first and second sensor linear output signals.
3. The system of claim 1, wherein the second linear distance is greater than the first linear distance.
4. The system of claim 1, wherein the first and second sensor each comprise:
a plurality of magnetoresistive (MR) sensors, each MR sensor configured to supply an MR sensor output that varies relative thereto; and
one or more sensor processors coupled to receive the MR sensor outputs.
5. The system of claim 1, wherein:
each magnet of the magnets in the first set of magnets are identical; and
each of the magnets in the second set of magnets are identical.
6. The system of claim 1, further comprising:
a third sensor coupled to the first sensor, the third sensor associated with and movable relative to the first set of magnets, the third sensor configured to sense the preset linear distance and generate a third sensor linear output signal in response to relative linear movement between the third sensor and the first set of magnets;
a fourth sensor coupled to the second sensor, the fourth sensor associated with and movable relative to the second set of magnets, the fourth sensor configured to sense the preset linear distance and generate a fourth sensor linear output signal in response to relative linear movement between the fourth sensor and the second set of magnets.
7. The system of claim 6, wherein:
the third sensor is offset from the first sensor by a first predetermined distance; and
the fourth sensor is offset from the second sensor by a second predetermined distance.
8. The system of claim 7, wherein the first and second predetermined distances are equal.
9. The system of claim 6, wherein the processor is further coupled to receive the third and fourth sensor linear output signals and is further configured, in response thereto, to generate the position signal.
10. The system of claim 9, wherein the processor is further configured to:
combine the first and third sensor linear output signals to generate a first combined signal;
combine the second and fourth sensor linear output signals to generate a second combined signal;
determine a difference between the first and second combined signals; and
generate the position signal based on the difference between the first and second combined signals.
11. A position sensor system, comprising:
a first set of magnets, each magnet in the first set of magnets spaced apart from at least one other magnet in the first set of magnets by a first linear distance;
a first sensor associated with and movable relative to the first set of magnets, the first sensor configured to generate a first sensor output signal in response to relative movement between the first sensor and the first set of magnets;
a second set of magnets, each magnet in the second set of magnets spaced apart from at least one other magnet in the second set of magnets by a second linear distance, the second linear distance greater than the first linear distance;
a second sensor associated with and movable relative to the second set of magnets, the second sensor configured to generate a second sensor output signal in response to relative movement between the second sensor and the second set of magnets; and
a processor coupled to receive the first and second sensor output signals and configured, in response thereto, to:
determine a difference between the first and second sensor output signals; and
generate a position signal based on the first sensor output signal and the difference between the first and second sensor output signals.
12. The system of claim 11, wherein:
each magnet of the magnets in the first set of magnets are identical; and
each of the magnets in the second set of magnets are identical.
13. The system of claim 11, further comprising:
a third sensor coupled to the first sensor, the third sensor associated with and movable relative to the first set of magnets, the third sensor configured to generate a third sensor output signal in response to relative movement between the third sensor and the first set of magnets;
a fourth sensor coupled to the second sensor, the fourth sensor associated with and movable relative to the second set of magnets, the fourth sensor configured to generate a fourth sensor output signal in response to relative movement between the fourth sensor and the second set of magnets.
14. The system of claim 13, wherein:
the third sensor is offset from the first sensor by a first predetermined distance; and
the fourth sensor is offset from the second sensor by a second predetermined distance.
15. The system of claim 14, wherein the first and second predetermined distances are equal.
16. The system of claim 13, wherein the processor is further coupled to receive the third and fourth sensor output signals and is further configured, in response thereto, to:
combine the first and third sensor output signals to generate a first combined signal;
combine the second and fourth output signals to generate a second combined signal;
determine a difference between the first and second combined signals; and
generate the position signal based on the difference between the first and second combined signals.
17. The system of claim 13, wherein the first, second, third, and fourth sensors each comprise:
a plurality of magnetoresistive (MR) sensors, each MR sensor configured to supply an MR sensor output that varies relative thereto; and
one or more sensor processors coupled to receive the MR sensor outputs.
18. A position sensor system, comprising:
a first set of magnets, each magnet in the first set of magnets spaced apart from at least one other magnet in the first set of magnets by a first linear distance;
a second set of magnets, each magnet in the second set of magnets spaced apart from at least one other magnet in the second set of magnets by a second linear distance, the second linear distance unequal to the first linear distance;
a first sensor associated with and movable relative to the first set of magnets, the first sensor configured to generate a first sensor output signal in response to relative movement between the first sensor and the first set of magnets;
a second sensor associated with and movable relative to the second set of magnets, the second sensor configured to generate a second sensor output signal in response to relative movement between the second sensor and the second set of magnets;
a third sensor coupled to the first sensor, the third sensor associated with and movable relative to the first set of magnets, the third sensor configured to generate a third sensor output signal in response to relative movement between the third sensor and the first set of magnets;
a fourth sensor coupled to the second sensor, the fourth sensor associated with and movable relative to the second set of magnets, the fourth sensor configured to generate a fourth sensor output signal in response to relative movement between the fourth sensor and the second set of magnets; and
a processor coupled to receive the first, second, third, and fourth sensor output signals and configured, in response thereto, to:
combine the first and third sensor output signals to generate a first combined signal;
combine the second and fourth output signals to generate a second combined signal;
determine a difference between the first and second combined signals; and
generate a position signal based on the first combined signal and the difference between the first and second combined signals.
19. The system of claim 18, wherein:
the third sensor is offset from the first sensor by a first predetermined distance; and
the fourth sensor is offset from the second sensor by a second predetermined distance.
20. The system of claim 18, wherein:
each magnet of the magnets in the first set of magnets are identical;
each of the magnets in the second set of magnets are identical;
the first and second predetermined distances are equal; and
the first, second, third, and fourth sensors each comprise:
a plurality of magnetoresistive (MR) sensors, each MR sensor configured to supply an MR sensor output that varies relative thereto; and
one or more sensor processors coupled to receive the MR sensor outputs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A data storage device comprising:
a casing having an opening through which a data storage cartridge is inserted;
a door coupled to said casing, said door covering said opening when said data storage cartridge is not installed in said device, said door forming a load-bearing structural element of said device.
2. The data storage device of claim 1, wherein said door is coupled to said casing such that said door rotates upon an insertion of said data storage cartridge into said data storage device.
3. The data storage device of claim 2, further comprising a spring, said spring biasing said door toward a closed position.
4. The data storage device of claim 2, wherein said door rotates towards an interior of said casing.
5. The data storage device of claim 2, wherein said door rotates through an arc of about 90 degrees.
6. The data storage device of claim 1, wherein an upper surface of said door substantially abuts said casing.
7. The data storage device of claim 1, wherein a lower surface of said door substantially abuts said casing.
8. The data storage device of claim 1, wherein said door forms a planar surface which guides said data storage cartridge during an insertion of said data storage cartridge into said data storage device.
9. The data storage device of claim 2, wherein said door is forcibly rotated by said data storage cartridge during said insertion of said data storage cartridge.
10. The data storage device of claim 1, wherein said door comprises a plurality of mounting pins integrally formed in said door.
11. The data storage device of claim 10, further comprising a door attachment piece coupled to said casing and said door mounting pins.
12. The data storage device of claim 11, wherein said door attachment piece is hinged to said door mounting pins.
13. The data storage device of claim 11, wherein said door attachment piece is coupled to a lower half of said casing.
14. The data storage device of claim 1, wherein a height of said door is about 5 mm.
15. The data storage device of claim 1, wherein a thickness of said door is about xx mm. CHECK WITH INVENTOR
16. The data storage device of claim 1, wherein said door spans substantially an entire width of said device.
17. The data storage device of claim 1, wherein said door is made of a plastic material.
18. The data storage device of claim 17, wherein said door comprises a metallic insert.
19. The data storage device of claim 1, wherein said door is made of a metallic material.
20. The data storage device of claim 1, wherein one or more edges of said door are rounded.
21. The data storage device of claim 1, further comprising a frame mounted within said casing.
22. The data storage device of claim 21, wherein said frame comprises a bend in a longitudinal end of said frame, and said door is positioned between said frame bend and a proximal longitudinal end of said casing when said data storage cartridge is installed in said data storage device.
23. The data storage device of claim 22, wherein said door forms a planar surface of about the same height as said frame bend when said data storage cartridge is installed in said device.
24. The data storage device of claim 21, further comprising:
a disk-drive motor which causes a storage medium located inside of said data storage cartridge to rotate;
a readwrite head which stores and reads information to and from said storage medium; and
a head-drive motor which moves said readwrite head to and from a location proximate said storage medium, said disk-drive motor, readwrite head, and head drive motor coupled to said frame.
25. The data storage device of claim 1, wherein said casing has the shape and dimensions conforming to the PCMCIA Type-II form factor.