Author: claimsbot

1. An image recording device, comprising:
a support member configured and arranged to support a sheet-shaped print medium;
a print head configured and arranged to move between a print position, at which printing of an image onto the print medium is executed, and a retracted position, at which a tension of the print medium is altered, the retracted position being farther away from the support member than the print position, while also facing the support member, with the print medium interposed therebetween;
a tension adjustment unit configured and arranged to adjust the tension of the print medium being supported by the support member; and
a control unit operatively coupled to the print head and the tension adjustment unit, the control unit being configured to control the print head to move to the retracted position and to control the tension adjustment unit to alter the tension of the print medium while the print head is positioned at the retracted position, and the control unit being further configured to control the print head to move to the print position and to execute printing by the print head while the print head is positioned at the print position with the tension of the print medium being adjusted to a print tension by the tension adjustment unit.
2. The image recording device as set forth in claim 1, wherein:
the control unit elevates the tension of the print medium to the print tension in the state where the print head has been positioned at the retracted position, and thereafter moves the print head to the print position to execute printing.
3. The image recording device as set forth in claim 1, wherein:
when the printing by the print head is concluded, the control unit moves the print head to the retracted position and thereafter reduces the tension of the print medium from the print tension.
4. The image recording device as set forth in claim 1, further comprising:
a conveyor unit for conveying the print medium,
wherein:
the control unit executes the printing on the print medium being conveyed by the conveyor unit.
5. The image recording device as set forth in claim 4, wherein:
the control unit positions the print head at the retracted position whenever the conveyor unit is to change the conveyance speed of the print medium.
6. The image recording device as set forth in claim 5, further comprising:
a tension detection unit for detecting the tension of the print medium,
wherein:
the control unit confirms, by a detection result from the tension detection unit, that the tension of the print medium after the conveyance speed has been changed has stabilized, and thereafter moves the print head to the print position to execute printing.
7. The image recording device as set forth in claim 6, wherein:
when the printing by the print head is concluded, the control unit moves the print head to the retracted position, and thereafter causes the conveyor unit to reduce the conveyance speed of the print medium.
8. The image recording device as set forth in claim 5, wherein:
the control unit positions the print head at the retracted position while the conveyance speed is being changed, and also moves the print head to the print position to execute printing once the conveyance speed of the print medium, after the conveyance speed has been changed, has stabilized.
9. The image recording device as set forth in claim 8, wherein:
the support member is a cylindrical-shaped support drum for supporting the print medium while the print medium is wound therearound, and rotates while being driven by the print medium being conveyed by the conveyor unit.
10. The image recording device as set forth in claim 9, further comprising:
a rotation detection unit for detecting the rotation of the support drum,
wherein:
the control unit confirms, by a detection result from the rotation detection unit, that the conveyance speed of the print medium has stabilized, and thereafter moves the print head to the print position to execute printing.
11. An image recording method comprising:
orienting a print head, having been positioned at a print position, so as to face a support member, with a sheet-shaped print medium supported by the support member being interposed therebetween, and then causing the print head to execute printing of an image onto the print medium; and
altering a tension of the print medium, either before or after the print step, in a state where the print head has been positioned at a retracted position while also facing the support member with the print medium interposed therebetween, at which a tension of the print medium is altered, the retracted position being farther away from the support member than the print position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacturing a thin film transistor substrate comprising thin film transistors,
each of the thin film transistors comprising:
a semiconductor film portion formed on an insulating substrate;
a gate insulating film portion laminated on the semiconductor film portion;
a gate made of a metal film portion formed on the gate insulating film portion; and
a channel formed in a region covered by the gate, which is formed of the semiconductor film portion,

the thin film transistor substrate comprising:
an n-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which n-type impurities are doped, the regions becoming a source and a drain;
a p-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which p-type impurities are doped, the regions becoming a source and a drain; and
a capacitor including:
a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion;
an upper capacitor electrode made of a metal film portion; and
another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode,
the method comprising:
processing the gate of the n-type thin film transistor, the gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask; and
changing impurity concentrations of semiconductor film portions located in regions which become the channel of the n-type thin film transistor, the source and the drain of the n-type thin film transistor, the channel of the p-type thin film transistor, the source and the drain of the p-type thin film transistor, and the lower capacitor electrode, by using a pattern of the first mask and a pattern of the second mask,
the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region,
the second mask having a transparent region and an opaque region,

wherein boundaries between the channel of the n-type thin film transistor and the source and the drain of the n-type thin film transistor, and boundaries between the channel of the p-type thin film transistor and the source and the drain of the p-type thin film transistor are defined by boundaries other than a boundary between the opaque region and the semitransparent region of the half-tone mask or a boundary between the opaque region and the transparent region of the half-tone mask.
2. A method for manufacturing a thin film transistor substrate comprising thin film transistors,
each of the thin film transistors comprising:
a semiconductor film portion formed on an insulating substrate;
a gate insulating film portion laminated on the semiconductor film portion;
a gate made of a metal film portion formed on the gate insulating film portion; and
a channel formed in a region covered by the gate, which is formed of the semiconductor film portion,

the thin film transistor substrate comprising:
an n-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which n-type impurities are doped, the regions becoming a source and a drain;
a p-type thin film transistor having regions of the semiconductor film portion, which are not covered by the gate and to which p-type impurities are doped, the regions becoming a source and a drain; and
a capacitor including:
a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion;
an upper capacitor electrode made of a metal film portion; and
another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode,
the method comprising:
processing the gate of the n-type thin film transistor, the gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask;
forming the channel of the n-type thin film transistor and the channel of the p-type thin film transistor in regions which are half-exposed with the first mask and unexposed with the second mask;
forming the source and the drain of the n-type thin film transistor in regions which are half-exposed with the first mask and exposed with the second mask;
forming the source and the drain of the p-type thin film transistor in regions which are exposed with the first mask and unexposed with the second mask; and
forming the lower capacitor electrode in a region which is unexposed with the first mask and exposed with the second mask,
the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region,
the second mask having a transparent region and an opaque region.
3. A method for manufacturing a thin film transistor substrate comprising thin film transistors,
each of the thin film transistors comprising:
a semiconductor film portion formed on an insulating substrate; and
a gate insulating film portion laminated on the semiconductor film portion,

the thin film transistor substrate comprising:
an n-type thin film transistor including:
a first gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the first gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the first gate and to which n-type impurities are doped;

a p-type thin film transistor including:
a second gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the second gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the second gate and to which p-type impurities are doped; and

a capacitor including:
a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion;
an upper capacitor electrode made of a metal film portion; and
another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode,
the method comprising:
processing the first gate of the n-type thin film transistor, the second gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask;
forming the channel of the n-type thin film transistor in a region which is half-exposed with the first mask and unexposed with the second mask;
forming the source and the drain of the n-type thin film transistor in regions which are half-exposed with the first mask and exposed with the second mask;
forming the channel of the p-type thin film transistor in a region which is exposed with the first mask and unexposed with the second mask;
forming the source and the drain of the p-type thin film transistor in regions which are exposed with the first mask and exposed with the second mask; and
forming the lower capacitor electrode in a region which is unexposed with the first mask and exposed with the second mask,
the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region,
the second mask having a transparent region and an opaque region.
4. A method for manufacturing a thin film transistor substrate comprising thin film transistors,
each of the thin film transistors comprising:
a semiconductor film portion formed on an insulating substrate; and
a gate insulating film portion laminated on the semiconductor film portion,

the thin film transistor substrate comprising:
an n-type thin film transistor including:
a first gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the first gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the first gate and to which n-type impurities are doped;

a p-type thin film transistor including:
a second gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the second gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the second gate and to which p-type impurities are doped; and

a capacitor including:
a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion;
an upper capacitor electrode made of a metal film portion; and
another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode,
the method comprising:
processing the first gate of the n-type thin film transistor, the second gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask;
forming the channel of the n-type thin film transistor in a region which is unexposed with the first mask and unexposed with the second mask;
forming the source and the drain of the n-type thin film transistor in regions which are unexposed with the first mask and exposed with the second mask;
forming the channel of the p-type thin film transistor in a region which is half-exposed with the first mask and unexposed with the second mask;
forming the source and the drain of the p-type thin film transistor in regions which are half-exposed with the first mask and exposed with the second mask; and
forming the lower capacitor electrode in a region which is exposed with the first mask and unexposed with the second mask,
the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region,
the second mask having a transparent region and an opaque region.
5. A method for manufacturing a thin film transistor substrate comprising thin film transistors,
each of the thin film transistors comprising:
a semiconductor film portion formed on an insulating substrate; and
a gate insulating film portion laminated on the semiconductor film portion,

the thin film transistor substrate comprising:
an n-type thin film transistor including:
a first gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the first gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the first gate and to which n-type impurities are doped;

a p-type thin film transistor including:
a second gate made of a metal film portion formed on the gate insulating film portion;
a channel formed in a region covered by the second gate, which is formed of the semiconductor film portion; and
a source and a drain formed in regions of the semiconductor film portion, which are not covered by the second gate and to which p-type impurities are doped; and

a capacitor including:
a lower capacitor electrode formed in a region of another semiconductor film portion, to which the n-type impurities are doped, the another semiconductor film portion being formed on the same layer as the semiconductor film portion;
an upper capacitor electrode made of a metal film portion; and
another insulating film portion formed on the same layer as the gate insulating film portion to be interposed between the lower capacitor electrode and the upper capacitor electrode,
the method comprising:
processing the first gate of the n-type thin film transistor, the second gate of the p-type thin film transistor, and the upper capacitor electrode by using a first mask and a second mask;
forming the channel of the n-type thin film transistor in a region which is half-exposed with the first mask and unexposed with the second mask;
forming the source and the drain of the n-type thin film transistor in regions which are half-exposed with the first mask and exposed with the second mask;
forming the channel of the p-type thin film transistor in a region which is unexposed with the first mask and unexposed with the second mask;
forming the source and the drain of the p-type thin film transistor in regions which are unexposed with the first mask and exposed with the second mask; and
forming the lower capacitor electrode in a region which is exposed with the first mask and unexposed with the second mask,
the first mask being a half-tone mask having a transparent region, an opaque region, and a semitransparent region,
the second mask having a transparent region and an opaque region.

1. A method of generating ranges of Internet Protocol (IP) addresses comprising:
applying a mask to a plurality of IP addresses to generate a plurality of groups of IP addresses; and
generating a range of IP addresses for each of the plurality of groups when the plurality of groups is less than or equal to a predetermined number of groups.
2. The method of claim 1 comprising:
applying another mask to the plurality of groups of IP addresses to generate another plurality of groups of IP addresses when the plurality of groups is greater than the predetermined number of groups; and
generating ranges of IP addresses using the another plurality of groups when the another plurality of groups is less than the predetermined number of groups.
3. The method of claim 2, wherein the mask identifies a first portion of an IP address to be masked and the another mask identifies a second portion of the IP address to be masked, wherein the second portion includes the first portion.
4. The method of claim 1 comprising:
selecting a range of IP addresses from the plurality of ranges of IP addresses; and
displaying network nodes associated with the selected range.
5. The method of claim 1, wherein applying the mask comprises:
performing a logical AND operation between each of the plurality of IP addresses and the mask to generate a resultant IP address, wherein the resultant IP address identifies one of the plurality of groups of IP addresses.
6. The method of claim 1, wherein applying the mask comprises:
applying the mask to the plurality of IP addresses to generate a plurality of masked IP addresses; and
grouping masked IP addresses to generate the plurality of groups of IP addresses.
7. The method of claim 6, wherein the mask identifies a first portion of an IP address to be masked and a second portion of the IP address, and wherein the masked IP addresses are grouped based upon the second portion of the IP addresses.
8. A management station for generating ranges of Internet Protocol (IP) addresses comprising:
a memory which stores a plurality of IP addresses; and
a processor which receives the plurality of IP addresses and applies a mask to the plurality of IP addresses to generate a plurality of groups of IP addresses, and which generates a range of IP addresses for each of the plurality of groups when the plurality of groups is less than or equal to a predetermined number of groups.
9. The management station of claim 8 wherein the processor applies another mask to the plurality of groups of IP addresses to generate another plurality of groups of IP addresses when the plurality of groups is greater than the predetermined number of groups, and generates ranges of IP addresses using the another plurality of groups when the another plurality of groups is less than the predetermined number of groups.
10. The management station of claim 9, wherein the mask identifies a first portion of an IP address to be masked and the another mask identifies a second portion of the IP address to be masked, wherein the second portion includes the first portion.
11. The management station of claim 8 comprising:
an input which receives a selection of a range of IP addresses from the plurality of ranges of IP addresses; and
a display which displays network nodes associated with the selected range.
12. The management station of claim 8, wherein the application of the mask includes the processor performing a logical AND operation between each of the plurality of IP addresses and the mask to generate a resultant IP address, wherein the resultant IP address identifies one of the plurality of groups of IP addresses.
13. The management station of claim 8, wherein the application of the mask includes applying the mask to the plurality of IP addresses to generate a plurality of masked IP addresses, and grouping masked IP addresses to generate the plurality of groups of IP addresses.
14. The management of claim 13, wherein the mask identifies a first portion of an IP address to be masked and a second portion of the IP address, and wherein the masked IP addresses are grouped based upon the second portion of the IP addresses.
15. A computer readable medium containing a computer program for generating ranges of Internet Protocol (IP) addresses, the method comprising:
applying a mask to a plurality of IP addresses to generate a plurality of groups of IP addresses; and
generating a range of IP addresses for each of the plurality of groups when the plurality of groups is less than or equal to a predetermined number of groups.
16. The method of claim 15 comprising:
applying another mask to the plurality of groups of IP addresses to generate another plurality of groups of IP addresses when the plurality of groups is greater than the predetermined number of groups; and
generating ranges of IP addresses using the another plurality of groups when the another plurality of groups is less than the predetermined number of groups.
17. The method of claim 16, wherein the mask identifies a first portion of an IP address to be masked and the another mask identifies a second portion of the IP address to be masked, wherein the second portion includes the first portion.
18. The method of claim 15 comprising:
selecting a range of IP addresses from the plurality of ranges of IP addresses; and
displaying network nodes associated with the selected range.
19. The method of claim 15, wherein the applying the mask comprises:
performing a logical AND operation between each of the plurality of IP addresses and the mask to generate a resultant IP address, wherein the resultant IP address identifies one of the plurality of groups of IP addresses.
20. The method of claim 15, wherein the applying the mask comprises:
applying the mask to the plurality of IP addresses to generate a plurality of masked IP addresses; and
grouping masked IP addresses to generate the plurality of groups of IP addresses.
21. The method of claim 20, wherein the mask identifies a first portion of an IP address to be masked and a second portion of the IP address, and wherein the masked IP addresses are grouped based upon the second portion of the IP addresses.
22. An apparatus for generating ranges of Internet Protocol (IP) addresses comprising:
means for storing a plurality of IP addresses; and
means for applying a mask to the plurality of IP addresses to generate a plurality of groups of IP addresses, and for generating a range of IP addresses for each of the plurality of groups when the number of groups is less than or equal to a predetermined number.
23. The apparatus of claim 22, wherein the means for applying and generating applies another mask to the plurality of groups of IP addresses to generate another plurality of groups of IP addresses when the plurality of groups is greater than the predetermined number, and generates ranges of IP addresses using the another plurality of groups when the another plurality of groups is less than the predetermined number.
24. The apparatus of claim 23, wherein the mask identifies a first portion of an IP address to be masked and the another mask identifies a second portion of the IP address to be masked, wherein the second portion includes the first portion.
25. The apparatus of claim 22 comprising:
means for selecting a range of IP addresses from the plurality of ranges of IP addresses; and
means for displaying network nodes associated with the selected range.
26. The apparatus of claim 22, wherein applying the mask comprises:
performing a logical AND operation between each of the plurality of IP addresses and the mask to generate a resultant IP address, wherein the resultant IP address identifies one of the plurality of groups of IP addresses.
27. The apparatus of claim 22, wherein applying the mask comprises:
applying the mask to the plurality of IP addresses to generate a plurality of masked IP addresses; and
grouping masked IP addresses to generate the plurality of groups of IP addresses.
28. The apparatus of claim 27, wherein the mask identifies a first portion of an IP address to be masked and a second portion of the IP address, and wherein the masked IP addresses are grouped based upon the second portion of the IP addresses.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A microlens array comprising:
a plurality of first microlenses; and
a plurality of elliptically-shaped second microlenses, wherein said plurality of first and second microlenses are arranged adjacent to each other.
2. The microlens array of claim 1, wherein said microlens array is substantially gapless
3. The microlens array of claim 1, wherein said second microlenses have a longitudinal axis which is offset by an angle from a vertical axis of said microlens array.
4. The microlens array of claim 1, wherein each of the plurality of first microlenses has a different shape than each of said plurality of second microlenses.
5. The microlens array of claim 1, wherein each of the plurality of first microlenses has an elliptical shape.
6. The microlens array of claim 5, wherein each of the plurality of first microlenses has a longitudinal axis which is offset by a same angle from the vertical axis of said microlens array as a longitudinal axis of each of the plurality of second microlenses.
7. The microlens array of claim 5, wherein each of the plurality of first microlenses has a longitudinal axis which is offset by a different angle from the vertical axis of said microlens array as a longitudinal axis of each of the plurality of second microlenses.
8. The microlens array of claim 1, further comprising a plurality of third microlenses.
9. The microlens array of claim 8, wherein said third microlenses are elliptically-shaped.
10. The microlens array of claim 8, wherein said first, second, and third microlenses are arranged in a radial configuration about a center point.
11. An imager comprising:
a pixel array formed in a substrate, said pixel array having an array of at least first and second photosensitive areas; and
a first set of microlenses over said pixel array, said first set of microlenses having first and second focal lengths.
12. The imager of claim 11, wherein said first set of microlenses is elliptically-shaped.
13. The imager of claim 12, wherein said elliptically-shaped microlenses have longitudinal axes which are offset from a vertical axis of said first microlens array by an angle.
14. The imager of claim 11, further comprising a second set of microlenses.
15. The imager of claim 14, wherein said second set of microlenses is substantially square-shaped.
16. The imager of claim 14, wherein each microlens of said second set of microlenses is located between two microlenses of said first set of microlenses.
17. The imager of claim 11, wherein at least said first photosensitive areas are asymmetrical.
18. The imager of claim 14, wherein said microlens array is arranged in a checkerboard pattern.
19. The imager of claim 14, wherein said microlens array is arranged in a radial pattern.
20. The imager of claim 14, further comprising a third set of microlenses, wherein each microlens of said third set of microlenses is located between two microlenses of said first and second set of microlenses.
21. A method of forming an imaging device comprising:
providing a pixel array having at least one asymmetrical photosensitive area;
patterning a first set of microlens material over said pixel array;
reflowing the first set of microlens material under first reflow conditions;
curing the first set of microlens material to form a first set of microlenses;
patterning a second set of microlens material over said pixel array;
reflowing the second set of microlens material under second reflow conditions; and
curing the second set of microlens material to form a second set of microlenses, wherein the first set of microlens material is patterned such that said first set of microlens material forms an elliptical shape under said first reflow conditions.
22. The method of claim 21, wherein said first reflow conditions are different from said second reflow conditions.
23. The method of claim 21, wherein said step of patterning the first set of microlens material comprises patterning the first set of microlens material into a first plurality of portions arranged in a checkerboard pattern, the checkerboard pattern including spaces between said portions.
24. The method of claim 23, wherein said step of patterning the second set of microlens material comprises patterning the second set of microlens material into second plurality of portions arranged in a complimentary checkerboard pattern filling in at least some of said spaces between the first plurality of portions.
25. The method of claim 21, wherein said step of patterning the first set of microlens material comprises patterning the first set of microlens material into a first plurality of portions arranged in a radial pattern having spaces between said first plurality of portions.
26. The method of claim 25, wherein said step of patterning the second set of microlens material comprises patterning the second set of microlens material into a second plurality of portions filling at least some of said spaces between said first plurality of portions.
27. The method of claim 21, further comprising the steps of:
patterning a third set of microlens material over said pixel array;
reflowing the third set of microlens material under third reflow conditions; and
curing the third set of microlens material to form a third set of microlenses,
28. The method of claim 27, wherein said third reflow conditions are different from said first and second reflow conditions.
29. The method of claim 28, wherein the third set of microlens material is patterned such that said third set of microlens material forms an elliptical shape under said third reflow conditions.