Author: claimsbot

1. A sealed joint structure comprising:
a valve with a thin wall extension which forms an angled structure to retain
a flared tube with the flare extending radially outward and forward from the tube,
an elastomeric seal, typically an o-ring which seals both the outside wall of the tube and the inside wall of the valve and a spacer, angularly shaped at one side of the front surface which contacts the flared portion of the tube, angularly shaped at the opposite side of the front surface which contacts and compresses the seal and shaped flat at the rear surface facing the tube and thin wall extension.
2. A sealed joint structure according to claim 1, wherein the valve is an unvalved fitting with a thin wall extension.
3. A sealed joint structure according to claim 1, wherein the valve is a port with a thin wall extension.
4. A sealed joint structure according to claim 1, wherein the flare on the tube is a single flare.
5. A sealed joint structure according to claim 1, wherein the flare on the tube is angularly shaped.
6. A sealed joint structure according to claim 1, wherein the thin wall extension is a flat face surface of a threaded fitting.
7. A sealed joint structure according to claim 1, wherein the backup spacer is the front face of a threaded fitting, angularly shaped at one side of the front surface which contacts the flared portion of the tube and angularly shaped at the opposite side of the front surface which contacts and compresses the seal into the inside recess.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
a processor;
at least one hardware monitor to measure circuit delays associated with the processor;
a power supply to provide power to the processor;
a voltage regulator to regulate a voltage level provided by the power supply;
a look-up table having target voltage values and target circuit delay values each corresponding to one or more conditions; and
a controller to control the voltage regulator, the controller at various time points controlling the voltage regulator based on target voltage values obtained from the look-up table, and in between the time points, the controller controlling the voltage regulator based on differences between target circuit delay values and measured circuit delay values.
2. The apparatus of claim 1 in which the controller obtains new target voltage values and target circuit delay values from the look-up table when the conditions change.
3. The apparatus of claim 1 in which the one or more conditions comprise at least one of clock frequency or temperature.
4. The apparatus of claim 1 in which the controller calculates a step voltage based on the difference between the target circuit delay value and the measured circuit delay value, and provides the step voltage to the voltage regulator for use in incremental adjustment of the power supply output voltage level.
5. The apparatus of claim 4 in which the controller, after providing the step voltage to the voltage regulator, waits an amount of time that is determined based on the step voltage before sampling the measured circuit delay value again.
6. The apparatus of claim 4, comprising a stability controller to reduce overshoot and undershoot of the output voltage of the power supply as the voltage regulator incrementally adjusts the power supply output voltage based on the step voltages provided by the controller.
7. The apparatus of claim 1 in which the circuit delays measured by the hardware monitor are associated with at least one critical path in the processor.
8. The apparatus of claim 1 in which entries in the look-up table are sorted in ascending or descending order, and the controller searches the look-up table using a binary search when attempting to obtain values from the look-up table.
9. An apparatus comprising:
a circuit;
a hardware monitor to measure circuit delays associated with the circuit;
a regulated power supply to provide power to the circuit;
a look-up table having target voltage values and target circuit delay values; and
a controller to control the regulated power supply based on open loop control and closed feedback loop control, in which for the open loop control the controller sets the regulated power supply voltage based on target voltage values obtained from the look-up table, and for the closed feedback loop control, the controller continuously adjusts the regulated power supply voltage based on differences between target circuit delay values and measured circuit delay values.
10. The apparatus of claim 9 in which the circuit comprises a processor.
11. The apparatus of claim 9 in which in the closed feedback loop control, the controller calculates a step voltage based on the difference between the target circuit delay value and the measured circuit delay value, and adjusts the regulated power supply voltage based on the step voltage.
12. The apparatus of claim 11 in which the controller, after adjusting the regulated power supply voltage based on the step voltage, waits an amount of time that is determined based on the step voltage before sampling the measured circuit delay value again.
13. The apparatus of claim 1, further comprising:
a bus, wherein the at least one hardware monitor is coupled to the bus, and
wherein the controller polls the at least one hardware monitor and receives measured circuit delay values from the hardware monitors through the bus.
14. The apparatus of claim 13 in which each hardware monitor has a unique identifier, the controller polls a particular hardware monitor by sending the unique identifier on the data bus, and the particular hardware monitor responds to the controller upon identifying the unique identifier on the data bus.
15. The apparatus of claim 13 in which the voltage regulator is coupled to the data bus, and the controller sends commands for increasing or decreasing voltage to the voltage regulator through the bus.
16. The apparatus of claim 13 in which the processor is coupled to the bus, and the processor accesses resources coupled to the bus.
17. The apparatus of claim 13 in which the controller polls at least one hardware monitors to obtain at least one measured circuit delay value, calculates a step voltage based on a difference between a target circuit delay value and the at least one measured circuit delay value, provides the step voltage to the voltage regulator for use in adjusting the power supply voltage level, and waits an amount of time that is determined based on the step voltage before polling a hardware monitor to request a new measured circuit delay value.
18. A method comprising:
transmitting data on a bus to a processor;
measuring circuit delays associated with the processor using hardware monitors coupled to the bus;
sending, from a controller, requests to the hardware monitors through the bus, the requests requesting measured circuit delay values;
receiving, at the controller, measured circuit delay values from the hardware monitors through the bus; and
controlling, using the controller, an output voltage level of a power supply that provides power to the processor according to the measured circuit delay values.
19. The method of claim 18, comprising reducing the amount of traffic on the bus associated with the hardware monitors by having the controller wait an amount of time before sending another request to the hardware monitors, the amount of time being determined based on a step voltage used to incrementally adjust the output voltage level of the power supply.
20. The method of claim 19 in which the controller waits for a longer period of time when the step voltage is larger.

1. An electrode mixture comprising
a lithium mixed metal oxide having a BET specific surface area of 2 to 30 m2g,
a water-soluble polymer having an acid functional group,
water and
an electrically conductive material.
2. The electrode mixture according to claim 1, wherein the lithium mixed metal oxide is represented by the following formula (1):
Liz(Ni1-(x+y)MnxMy)O2\u2003\u2003(1)

wherein x is not less than 0.3 and less than 1,
y is not less than 0 and less than 0.7,
x+y is not less than 0.3 and less than 1,
z is not less than 0.5 and not more than 1.5 and
M represents one or more elements selected from the group consisting of Co, Al, Ti, Mg and Fe.
3. The electrode mixture according to claim 1, wherein the acid functional group is one or more groups selected from the group consisting of carboxyl group, sulfo group, thiol group and phosphate group.
4. The electrode mixture according to claim 1, wherein the water-soluble polymer having an acid functional group contains one or more compounds selected from the group consisting of carboxymethyl starch, starch phosphate, algic acid, polyacrylic acid, polymethacrylic acid and polystyrene sulfonate.
5. The electrode mixture according to claim 1, further comprising one or more materials selected from the group consisting of an aqueous emulsion and an aqueous dispersion.
6. The electrode mixture according to claim 5, wherein the aqueous emulsion is one or more emulsions selected from the group consisting of an emulsion of vinyl-based polymer and an emulsion of acrylic-based polymer.
7. The electrode mixture according to claim 5, wherein the aqueous dispersion is a polytetrafluoroethylene-based dispersion.
8. The electrode mixture according to claim 1, further comprising a thickening agent.
9. The electrode mixture according to claim 8, wherein the thickening agent contains one or more compounds selected from the group consisting of methyl cellulose, carboxymethyl cellulose, polyethylene glycol, sodium polyacrylate, polyvinyl alcohol and polyvinyl pyrrolidone.
10. The electrode mixture according to claim 1, wherein the electrically conductive material contains a carbonaceous material.
11. An electrode produced by applying the electrode mixture according to claim 1 on an electrode current collector, and then drying the applied current collector.
12. A lithium secondary battery comprising the electrode according to claim 11 as a positive electrode.
13. The lithium secondary battery according to claim 12, further comprising a separator.
14. The lithium secondary battery according to claim 13, wherein the separator is a laminate film in which a heat resistant porous layer and a porous film are stacked on each other.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming at least one through via in a semiconductor substrate comprising:
providing a semiconductor substrate having an active surface including a plurality of discrete conductive elements thereon, an opposing back surface, and at least one active region;
removing at least one first portion of the semiconductor substrate underlying at least one of the plurality of discrete conductive elements to form at least one first partial via extending from the active surface partially through the semiconductor substrate to at least a junction depth of the at least one active region, wherein forming the at least one first partial via is effected at a temperature sufficiently low to prevent redistribution of dopant in the at least one active region; and
removing at least one second portion of the semiconductor substrate to form at least one second partial via extending from the back surface partially through the semiconductor substrate.
2. The method according to claim 1, further comprising forming an aperture through the at least one of the plurality of discrete conductive elements prior to removing the at least one first portion of the semiconductor substrate thereunder.
3. The method according to claim 2, wherein forming the aperture is effected by at least one of wet etching, dry etching, and laser drilling.
4. The method of claim 2, wherein removing the at least one first portion of the semiconductor substrate comprises removing material from the semiconductor substrate in a direction from the active surface toward the back surface to form the at least one first partial via.
5. The method according to claim 4, further comprising forming the at least one first partial via to extend beneath the active surface to a depth of between about 5 \u03bcm and about 20 \u03bcm.
6. The method according to claim 4, further comprising forming the at least one first partial via to extend beneath the active surface to a depth of between about 5 \u03bcm and about 10 \u03bcm.
7. The method according to claim 4, further comprising forming the at least one first partial via to extend from the active surface to a depth beyond the depth of the at least one active region.
8. The method according to claim 4, wherein removing the at least one first portion of the semiconductor substrate is effected by at least one of wet etching, dry etching, and laser drilling.
9. The method according to claim 4, wherein removing the at least one second portion of the semiconductor substrate comprises removing material from the semiconductor substrate in a direction from the back surface toward the active surface to form the at least one second partial via.
10. The method according to claim 9, wherein removing the at least one second portion of the semiconductor substrate occurs after removing the at least one first portion of the semiconductor substrate.
11. The method according to claim 9, wherein removing the at least one second portion of the semiconductor substrate is effected by laser drilling.
12. The method according to claim 11, further comprising:
selectively applying a pulse of laser energy to the semiconductor substrate at a location of the at least one first partial via to partially form the at least one second partial via;
selectively applying a pulse of laser energy to the semiconductor substrate in another location to partially form at least one additional second partial via in alignment with at least one additional first partial via; and
alternating applications of pulses of laser energy between at least the location of the at least one first partial via and the another location to form the at least one second partial via and the at least one additional second partial via.
13. The method according to claim 1, wherein removing the at least one second portion of the semiconductor substrate occurs before removing the at least one first portion of the semiconductor substrate.
14. The method according to claim 13, wherein removing the at least one second portion of the semiconductor substrate comprises removing material from the semiconductor substrate in a direction from the back surface toward the active surface to form the at least one second partial via.
15. The method according to claim 14, further comprising forming the at least one second partial via to extend from the back surface to about at least the depth of the at least one active region.
16. The method according to claim 14, further comprising forming the at least one second partial via to extend from the back surface to a depth from the active surface greater than the depth of the at least one active region.
17. The method according to claim 14, further comprising forming the at least one second partial via to terminate within about 25 \u03bcm or more from the at least one active region.
18. The method according to claim 14, wherein removing the at least one second portion of the semiconductor substrate is effected by laser drilling.
19. The method according to claim 18, further comprising:
selectively applying a pulse of laser energy to the semiconductor substrate at a location to partially form the at least one second partial via;
selectively applying a pulse of laser energy to the semiconductor substrate in another location to partially form at least one additional second partial via; and
alternating applications of pulses of laser energy between at least the location and the another location to form the at least one second partial via and the at least one additional second partial via.
20. The method according to claim 14, wherein removing the at least one first portion of the semiconductor substrate comprises removing material from the semiconductor substrate between a terminus of the at least one second partial via within the semiconductor substrate
and the at least one of the plurality of discrete conductive elements in a direction from the back surface toward the active surface to form the at least one first partial via.
21. The method according to claim 20, wherein removing the at least one first portion of the semiconductor substrate comprises dry etching.
22. The method according to claim 21, wherein the dry etching comprises a deep reactive ion etch employing an etchant plasma and a passivant plasma.
23. The method according to claim 14, further comprising forming an aperture in the at least one of the plurality of discrete conductive elements prior to removing the at least one first portion of the semiconductor substrate.
24. The method according to claim 23, wherein the forming the aperture is effected by at least one of wet etching, dry etching, and laser drilling.
25. The method of claim 22, wherein removing the at least one first portion of the semiconductor substrate comprises removing material from the semiconductor substrate in a direction from the active surface toward the back surface to form the at least one first partial via.
26. The method according to claim 25, further comprising forming the at least one first partial via to extend beneath the active surface to a depth of between about 5 \u03bcm and about 20 \u03bcm.
27. The method according to claim 25, further comprising forming the at least one first partial via to extend beneath the active surface to a depth of between about 5 \u03bcm and about 10 \u03bcm.
28. The method according to claim 25, further comprising forming the at least one first partial via to extend from the active surface to a greater depth than the depth of the at least one active region.
29. The method according to claim 24, wherein removing the at least one first portion of the semiconductor substrate is effected by at least one of wet etching, dry etching, and laser drilling.