Author: claimsbot

What is claimed is:

1. An aromatic diaminearomatic dicarboxylate of the following formula (I)
NH2Ar1NH2.HOOCAr2COOH(I)
wherein Ar1 is a group of the following formula (a) or (b)

3
wherein each Z is independently an oxygen atom or a sulfur atom, and
Ar2 is a group of any of the following formulas (c)-(f)

4
wherein R1 and R2 are each independently a hydrogen atom, a methyl group or a hydroxyl group,
which is in the form of particles having a median diameter of 5-100 m and whiteness of not less than 75.
2. The aromatic diaminearomatic dicarboxylate of claim 1, which has a water content of not more than 3000 ppm.
3. The aromatic diaminearomatic dicarboxylate of claim 1, which comprises tin(II) or iron(II) in a proportion of 0.1-5.0 mol %.
4. A production method of aromatic diaminearomatic dicarboxylate of claim 1, which comprises adding, for mixing, an aqueous solution of aromatic diamine hydrochloride of the following formula (II)
NH2Ar1NH2.2HCl(II)
wherein Ar1 is as defined in claim 1, to an aqueous solution of alkali metal aromatic dicarboxylate of the following formula (III)
MOOCAr2COOM(III)
wherein Ar2 is as defined in claim 1 and M is an alkali metal, under the following conditions (1) and (2):
(1) 1.0-1.2 moles of the aromatic diamine hydrochloride is used per 1 mole of the alkali metal aromatic dicarboxylate, and
(2) a temperature during the addition is not less than 70 C. and not more than 100 C.
5. A production method of polybenzazole, which comprises using the aromatic diaminearomatic dicarboxylate of claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for directing communication, the method comprising:
receiving a request from an Internet user for a specific website;
relaying the request to an ISP DNS server to determine the Internet address for the website;
responding to the request by providing an Internet address when the requested Internet address for the website is located;
if an Internet address for the requested website is not located:
determining if the request is a request other than one associated with the hypertext transfer protocol (HTTP);
if the request is not associated with HTTP, forwarding to the Internet user the response from the Internet infrastructure;
for all other requests:
directing the Internet user to a predetermined search network;
choosing at least one appropriate target through the search network and sending a request for information from that target; and
providing a result page to the Internet user, the result page being a culmination of information received from the at least one target.
2. The method of claim 1, wherein directing the Internet user to a predetermined search network when the requested Internet address is not located comprises intercepting, by a DNS based proxy, the request at a name level to return a contrived IP address for a web server landing page in place of an unresolved domain name request.
3. The method of claim 1, wherein the targets are predetermined partners and associated with the ISP DNS.
4. The method of claim 1, wherein all steps occur within an Internet structure.
5. The method of claim 1, wherein the Internet user may opt-out of failed lookup redirection.
6. The method of claim 1, which is a method of controlling communication traffic, wherein said method provides one or more of the following services: DNS forwarding, URL filtering, DDOS attack detection, and SPAM source identification.
7. The method of claim 1, which is a method of controlling access by a user to an undesirable website, wherein said method further comprises:
identifying an IP address, a URL, or both, corresponding to the undesirable website, wherein the IP address is provided by a DNS server connected to the Internet; and
supplying to the user a different IP address than the IP address corresponding to the undesirable website,
wherein the different IP address corresponds to a web page that provides the user content that is relevant to the query that resulted in return of the undesirable website IP address.
8. The method of claim 7, which is a method of URL filtering.
9. A computer system for direction of communication traffic, said system comprising:
a DNS server;
a first device that:
receives and analyzes communications from a computer user and the DNS server; and
determines if a communication is associated with a protocol other than HTTP,
wherein, if the communication is not associated with a protocol other than HTTP, communicating with a second device when an unresolved, unwanted, unused, improper, or incorrect is encountered; and
a second device that creates a landing page for the computer user based on information supplied to it by the first device,
wherein the information supplied by the first device is information indicating that the communication from the user was unresolved, unwanted, unused, improper, or incorrect.
10. The computer system of claim 9, wherein the first device is interposed, within the communication pathway, between the user and the DNS, and wherein the first device is capable of intercepting and analyzing communications between the user and the DNS.
11. The computer system of claim 9, wherein the system comprises two or more second devices.
12. The computer system of claim 9, further comprising a computer used by the computer user, said computer comprising an Internet browser application and a browser plug-in that communicates with the first device to supply information regarding the computer used by the computer user, the computer user, or both.
13. The computer system of claim 9, wherein the first device and second device are not personal computers used by the computer user.
14. The computer system of claim 9, wherein the system is implemented at the ISPDNS level of the Internet architecture, and not at the user level or the registry level.
15. The computer system of claim 9, wherein the first device is a general services server that can implement one or more computer applications.
16. The computer system of claim 9, wherein the first device and the DNS are the same device.
17. The computer system of claim 9, which provides one or more of the following services: DNS forwarding, URL filtering, DDOS attack detection, and SPAM source identification.

I claim:

1. A display system for storing and displaying merchandise, the display system comprising:
one or more vertical display columns having of opposed sidewalls with each sidewall having a bracket affixed thereto;
each said bracket having aligned terraced slots for receiving one or more cassettes;
each said cassette having one or more compartments for receiving merchandise.
2. The display system of claim 1 wherein said bracket further comprises a discrete metal strip.
3. The display system of claim 1 wherein each said bracket slot has a cross-sectional L shape.
4. The display system of claim 1 wherein said cassette further comprises a front cover which extends over said one or more compartments to return merchandise in said compartments.
5. The display system of claim 1 wherein said cassette further comprises:
an outer backing having a plurality of retaining clips and one or more spacers on an inner surface to cooperate with and front cover to form said compartments for containing merchandise; and
said front cover having outer flanges for reception into said retaining clips.
6. The display system of claim 1 wherein said cassette further comprises means for adjusting the depth of the compartment.
7. The display system of claim 1 wherein said cassette further comprises:
an adjustment clip having a receptacle for supporting merchandise and a clip end for reception into one or more vertically arranged slots said outer backing.
8. A display system for storing and displaying generally cylindrical articles, the display system comprising:
a plurality of roll trays vertically arranged for supporting generally cylindrical objects generally horizontally within said roll trays;
each said roll tray having a front portion comprised of a transparent material sufficient for viewing an exterior surface of said cylindrical objects.
9. The display system of claim 8 wherein said front portions of said roll trays are generally curved to conform to outer surfaces of the generally cylindrical objects.
10. The display system of claim 8 wherein said roll trays are angled toward a front side of the display system.
11. The roll trays of claim 10 further comprising a pocket on an exterior surface of said front portion.
12. A display system for storing and displaying generally cylindrical articles the display system comprising:
a plurality of roll trays for supporting generally cylindrical objects arranged in one or more vertical columns and affixed to a frame;
each said roll tray having support trays which can be adjusted to support cylindrical articles of different widths.
13. The display system of claim 12 further comprising a plurality of roll trays for supporting cylindrical objects with each said roll tray having a front portion comprised of a transparent material to expose an exterior surface of said cylindrical objects, and further having a pocket mounted on an exterior surface of said front portion.
14. The display system of claim 12 further comprising a rotatable elongate member mounted on a front portion of said display system for displaying merchandise on first and second sides of the elongate member.
15. An adjustable tray assembly for supporting two or more types of cylindrical objects of the same or differing widths comprising:
a first and second pair of support trays slidably mounted on a panel having a track with spaced teeth and grooves between the teeth; and
each of said support trays having a resilient flap with a ratchet member positionable in one of said grooves.
16. The support trays of claim 15 comprising fasteners which secure the support trays in a fixed position upon the panel.
17. The tray of claim 15 wherein said panel has edges for being slidably received in hooked ends of each of said support trays.
18. A fin assembly for displaying and storing merchandise, the fin assembly comprising:
a pivotally mounted elongate mounting panel having a first side and a second side;
the first side and second side each having an outer display compartment for displaying merchandise and an interior compartment having one or more pockets for storing merchandise.
19. The fin assembly of claim 18 further comprising a plurality of stepped spacers mounted on each side of said panel;
a plurality of separator clips mounted in between said spacers and forming an outer display compartment and one or more inner compartments.
20. The fin assembly of claim 18 wherein said inner compartment of said sample separator clip further comprises friction pins on an exterior surface for insertion into holes in said stepped spacers.
21. The assembly of claim 18 wherein said sample separator clip comprises flanges in said outer compartment and a resilient member for securing a clear cover over said outer compartment.
22. A product display structure comprising:
a plurality of rigid panels arranged to extend radially outward from a vertical axis;
a flexible panel extending between adjacent radial ends of said rigid panels to form a concave display surface; and
said panels being rotatably mounted upon a base.
23. The carousel display spinner of claim 22 wherein each rigid panel is generally perpendicular to adjacent rigid panels.
24. The carousel display spinner of claim 22 wherein an outer radial end of each of said rigid panels comprises a flange, and said flexible panel being retained by said flanges.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor integrated circuit to be mounted in a motor drive controller for driving a motor to move a magnetic head of a hard disk drive unit, the semiconductor integrated circuit being operable to make flow a non-zero current which is substantially not a zero current through the motor, in a calibration operation for a loading operation which moves the magnetic head from a ramp mechanism to a surface of a disk medium or an unloading operation which moves the magnetic head from the surface of the disk medium to the ramp mechanism,
wherein the non-zero current presses an arm mounting the magnetic head against an outer circumference stopper at the time of the calibration operation for the loading operation or presses the arm mounting the magnetic head against an inner circumference stopper at the time of the calibration operation for the unloading operation, so as to bring the arm into a fixed state,
wherein the semiconductor integrated circuit comprises:
a motor driver circuit operable to drive the motor;
a back EMF (electromotive force) detector circuit operable to detect a back electromotive force generated in the motor; and
an adjustment unit operable to adjust the gain of an internal amplifier of the back EMF detector circuit,
wherein, at the time of the calibration operation, a back EMF (electromotive force) detection signal is generated from the back EMF detector circuit, in response to the motor driver circuit making the non-zero current flow through the motor,
wherein the semiconductor integrated circuit generates a comparison reference value corresponding to the back EMF detection signal generated from the back EMF detector circuit, in the fixed state of the arm and the state where a zero current substantially with a zero current value flows through the motor by the calibration operation,
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets the back EMF detection signal generated from the back EMF detector circuit as a first value and a second value, in response to the non-zero current flowing through the motor,
wherein, at the time of the calibration operation, the semiconductor integrated circuit calculates the comparison reference value from the back EMF detection signal as the first value and the back EMF detection signal as the second value,
wherein the adjustment unit of the semiconductor integrated circuit adjusts the gain of the internal amplifier of the back EMF detector circuit by the calibration operation, and the back EMF detector circuit to which the adjusted gain is reflected generates the back EMF detection signal as a comparison input value, and
wherein the adjustment unit of the semiconductor integrated circuit adjusts the gain of the internal amplifier of the back EMF detector circuit so as to reduce the difference of the comparison input value and the comparison reference value by the calibration operation.
2. The semiconductor integrated circuit according to claim 1,
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets the back EMF detection signal generated from the back EMF detector circuit as the first value and the second value, respectively, by setting the non-zero current flowing through the motor as a first current value and a second current value, respectively.
3. The semiconductor integrated circuit according to claim 1,
wherein the back EMF detector circuit comprises as the internal amplifier:
an inverting amplifier in a preceding stage; and
a subtraction amplifier in a subsequent stage,
wherein the inverting amplifier in the preceding stage of the back EMF detector circuit and the subtraction amplifier in the subsequent stage amplify an inter-terminal voltage of the motor and an inter-terminal voltage of a current sensing resistor coupled in series with the motor, and the back EMF detection signal is generated from the back EMF detector circuit, and
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets a subtraction gain value of the subtraction amplifier in the subsequent stage as a first subtraction gain value and a second subtraction gain value, respectively, and sets the back EMF detection signal generated from the back EMF detector circuit as the first value and the second value, respectively.
4. The semiconductor integrated circuit according to claim 1,
wherein the back EMF detection signal as an analog back EMF detection signal is generated from the back EMF detector circuit, and
wherein a maximum value of the analog back EMF detection signal is controlled to an allowable maximum voltage lower than an operation power voltage of the semiconductor integrated circuit, and a minimum value of the analog back EMF detection signal is controlled to an allowable minimum voltage higher than a ground voltage of the semiconductor integrated circuit.
5. The semiconductor integrated circuit according to claim 1 further comprising:
a digital-to-analog converter; and
an analog-to-digital converter,
wherein an output terminal of the digital-to-analog converter is coupled to an input terminal of the motor driver circuit, and
wherein the analog back EMF detection signal as the back EMF detection signal generated by the back EMF detector circuit is supplied to an input terminal of the analog-to-digital converter, and a digital back EMF detection signal is generated from an output terminal of the analog-to-digital converter.
6. The semiconductor integrated circuit according to claim 5 further comprising:
a first detection register;
a second detection register;
a third detection register;
a fourth detection register;
a calculation unit; and
a comparator,
wherein, at the time of the calibration operation, the digital back EMF detection signal of the analog-to-digital converter, corresponding to the first value of the back EMF detection signal generated from the back EMF detector circuit in response to the non-zero current flowing through the motor, is stored in the third detection register,
wherein, at the time of the calibration operation, the digital back EMF detection signal of the analog-to-digital converter, corresponding to the second value of the back EMF detection signal generated from the back EMF detector circuit in response to the non-zero current flowing through the motor, is stored in the fourth detection register,
wherein the calculation unit calculates the comparison reference value from the first information stored in the third detection register and the second information stored in the fourth detection register, and stores the calculated comparison reference value in the first detection register,
wherein the digital back EMF detection signal of the analog-to-digital converter, corresponding to the comparison input value generated in response to the gain adjusted by the calibration operation, is stored in the second detection register,
wherein the comparator compares the comparison reference value stored in the first detection register with the digital back EMF detection signal of the analog-to-digital converter stored in the second detection register corresponding to the comparison input value, and
wherein the adjustment unit adjusts the gain of the internal amplifier of the back EMF detector circuit by the calibration operation in response to the comparison result of the comparator.
7. The semiconductor integrated circuit according to claim 6,
wherein the calculation unit comprises
a subtractor;
a divider; and
an adder,
wherein the first information stored in the third detection register is supplied to one input terminal of the subtractor, the second information stored in the fourth detection register is supplied to the other input terminal of the subtractor, and a subtraction result is generated from an output terminal of the subtractor,
wherein the subtraction result of the subtractor is supplied to one input terminal of the divider, a division indicating value is supplied to the other input terminal of the divider, and a division result is generated from an output terminal of the divider, and
wherein the first information stored in the third detection register is supplied to one input terminal of the adder, the division result of the divider is supplied to the other input terminal of the adder, and the comparison reference value as the addition result is generated from an output terminal of the adder.
8. The semiconductor integrated circuit according to claim 7 further comprising:
a state control unit operable to set the back EMF detection signal, generated from the back EMF detector circuit in response to the non-zero current flowing through the motor at the time of the calibration operation, as the first value and the second value,
wherein the state control unit comprises at least:
a multiplier; and
a selector,
wherein a ratio indicating value is supplied to one input terminal of the multiplier, a motor input current indicating value is supplied to the other input terminal of the multiplier, and a multiplication result is generated from an output terminal of the multiplier,
wherein the multiplication result of the multiplier is supplied to one input terminal of the selector, the motor input current indicating value is supplied to the other input terminal of the selector, and a selection instruction signal is supplied to a selection control terminal of the selector,
wherein, when a selection instruction signal supplied to a selection control terminal of the selector is in a first state, the motor input current indicating value supplied to the other input terminal of the selector is generated from an output terminal of the selector as a motor current indicating value,
wherein, when the selection instruction signal supplied to the selection control terminal of the selector is in a second state, the multiplication result of the multiplier supplied to the one input terminal of the selector is generated from the output terminal of the selector as the motor current indicating value,
wherein the motor current indicating value generated from the output terminal of the selector in response to the selection instruction signal as the first state sets the back EMF detection signal as the first value,
wherein the motor current indicating value generated from the output terminal of the selector in response to the selection instruction signal as the second state sets the back EMF detection signal as the second value,
wherein the state control unit generates the division indicating value depending on the ratio indicating value supplied to the one input terminal of the multiplier, and
wherein the division indicating value generated from the state control unit is supplied to the other input terminal of the divider of the calculation unit.
9. The semiconductor integrated circuit according to claim 8,
wherein the state control unit further comprises:
a subtractor,
wherein the ratio indicating value is supplied to one input terminal of the subtractor, \u201c1\u201d is supplied to the other input terminal of the subtractor, and the division indicating value as a subtraction result is generated from the output terminal of the subtractor,
wherein the division indicating value generated from the output terminal of the subtractor of the state control unit is the subtraction result in which \u201c1\u201d has been subtracted from the ratio indicating value, and
wherein the ratio indicating value ADJ_RATIO satisfies the conditions of ADJ_RATIO=2n+1 (n is an integer), and the divider of the calculation unit is comprised of a shift register which shifts the bit data of the ratio indicating value rightward in response to the division indicating value.
10. The semiconductor integrated circuit according to claim 3 further comprising:
a state control unit operable to set the back EMF detection signal generated from the back EMF detector circuit as the first value and the second value, in response to the non-zero current flowing through the motor, at the time of the calibration operation,
wherein the state control unit comprises at least:
a multiplier; and
a selector,
wherein a ratio indicating value is supplied to one input terminal of the multiplier, a gain indicating value is supplied to the other input terminal of the multiplier, and a multiplication result is generated from an output terminal of the multiplier,
wherein the multiplication result of the multiplier is supplied to one input terminal of the selector, the gain indicating value is supplied to the other input terminal of the selector, and a selection instruction signal is supplied to a selection control terminal of the selector,
wherein, when the selection instruction signal supplied to the selection control terminal of the selector is in a first state, the gain indicating value supplied to the other input terminal of the selector is generated from an output terminal of the selector as the subtraction gain value of the subtraction amplifier,
wherein, when the selection instruction signal supplied to the selection control terminal of the selector is in a second state, the multiplication result of the multiplier supplied to the one input terminal of the selector is generated from the output terminal of the selector as the subtraction gain value of the subtraction amplifier,
wherein the subtraction gain value of the subtraction amplifier generated from the output terminal of the selector in response to the selection instruction signal as the first state sets the back EMF detection signal as the first value,
wherein the subtraction gain value of the subtraction amplifier generated from the output terminal of the selector in response to the selection instruction signal as the second state sets the back EMF detection signal as the second value,
wherein the state control unit generates the division indicating value depending on the ratio indicating value supplied to the one input terminal of the multiplier, and
wherein the division indicating value generated from the state control unit is supplied to the other input terminal of the divider of the calculation unit.
11. The semiconductor integrated circuit according to claim 10,
wherein the state control unit further comprises:
a subtractor,
wherein the ratio indicating value is supplied to one input terminal of the subtractor, \u201c1\u201d is supplied to the other input terminal of the subtractor, and the division indicating value as the subtraction result is generated from an output terminal of the subtractor,
wherein the division indicating value generated from the output terminal of the subtractor of the state control unit is the subtraction result in which \u201c1\u201d has been subtracted from the ratio indicating value, and
wherein the ratio indicating value satisfies the conditions of ADJ_RATIO=2n+1 (n is an integer), and the divider of the calculation unit is comprised of a shift register which shifts the bit data of the ratio indicating value rightward in response to the division indicating value.
12. The semiconductor integrated circuit according to claim 4,
wherein the state control unit controls the maximum value and the minimum value of the analog back EMF detection signal to the allowable maximum voltage and the allowable minimum voltage, respectively,
wherein the state control unit further comprises:
a first comparator;
a second comparator;
an OR circuit; and
a limiter,
wherein the digital back EMF detection signal of the analog-to-digital converter is supplied in common to one input terminal of the first comparator and one input terminal of the second comparator,
wherein the allowable maximum voltage is supplied to the other input terminal of the first comparator, and the allowable minimum voltage is supplied to the other input terminal of the second comparator,
wherein a comparison output signal of the first comparator and a comparison output signal of the second comparator are supplied respectively to one input terminal and the other input terminal of the OR circuit,
wherein the ratio indicating value and an output signal generated from the OR circuit are supplied to the limiter,
wherein, when the digital back EMF detection signal supplied in common to the one input terminal of the first comparator and the one input terminal of the second comparator is higher than the allowable maximum voltage or lower than the allowable minimum voltage, the limiter generates a limit ratio indicating value, and
wherein the limit ratio indicating value generated by the limiter is set as a value smaller than the ratio indicating value, and supplied to the one input terminal of the subtractor of the state control unit.
13. The semiconductor integrated circuit according to claim 1,
wherein the motor driver circuit drives a voice coil motor as the motor to move the magnetic head of the hard disk drive unit.
14. The semiconductor integrated circuit according to claim 13,
wherein the semiconductor integrated circuit integrates a voice coil motor driver for driving the voice coil motor and a spindle motor driver for driving the spindle motor to turn the disk medium.
15. An operating method of a semiconductor integrated circuit to be mounted in a motor drive controller for driving a motor to move a magnetic head of a hard disk drive unit,
wherein the semiconductor integrated circuit is operable to make flow a non-zero current which is substantially not a zero current through the motor, in a calibration operation for a loading operation which moves the magnetic head from a ramp mechanism to a surface of a disk medium or an unloading operation which moves the magnetic head from the surface of the disk medium to the ramp mechanism,
wherein the non-zero current presses an arm mounting the magnetic head against an outer circumference stopper at the time of the calibration operation for the loading operation or presses the arm mounting the magnetic head against an inner circumference stopper at the time of the calibration operation for the unloading operation, so as to bring the arm into a fixed state,
wherein the semiconductor integrated circuit comprises
a motor driver circuit operable to drive the motor;
a back EMF (electromotive force) detector circuit operable to detect a back electromotive force generated in the motor; and
an adjustment unit operable to adjust the gain of an internal amplifier of the back EMF detector circuit,
wherein, at the time of the calibration operation, aback EMF (electromotive force) detection signal is generated from the back EMF detector circuit, in response to the motor driver circuit making the non-zero current flow through the motor,
wherein the semiconductor integrated circuit generates a comparison reference value corresponding to the back EMF detection signal generated from the back EMF detector circuit, in the fixed state of the arm and the state where a zero current substantially with a zero current value flows through the motor by the calibration operation,
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets the back EMF detection signal generated from the back EMF detector circuit as a first value and a second value, in response to the non-zero current flowing through the motor,
wherein, at the time of the calibration operation, the semiconductor integrated circuit calculates the comparison reference value from the back EMF detection signal as the first value and the back EMF detection signal as the second value,
wherein the adjustment unit of the semiconductor integrated circuit adjusts the gain of the internal amplifier of the back EMF detector circuit by the calibration operation, and the back EMF detector circuit to which the adjusted gain is reflected generates the back EMF detection signal as a comparison input value, and
wherein the adjustment unit of the semiconductor integrated circuit adjusts the gain of the internal amplifier of the back EMF detector circuit so as to reduce the difference of the comparison input value and the comparison reference value by the calibration operation.
16. The operating method of the semiconductor integrated circuit according to claim 15,
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets the back EMF detection signal generated from the back EMF detector circuit as the first value and the second value, respectively, by setting the non-zero current flowing through the motor as a first current value and a second current value, respectively.
17. The operating method of the semiconductor integrated circuit according to claim 15,
wherein the back EMF detector circuit comprises as the internal amplifier
an inverting amplifier in a preceding stage; and
a subtraction amplifier in a subsequent stage,
wherein the inverting amplifier in the preceding stage of the back EMF detector circuit and the subtraction amplifier in the subsequent stage amplify an inter-terminal voltage of the motor and an inter-terminal voltage of a current sensing resistor coupled in series with the motor, and the back EMF detection signal is generated from the back EMF detector circuit, and
wherein, at the time of the calibration operation, the semiconductor integrated circuit sets a subtraction gain value of the subtraction amplifier in the subsequent stage as a first subtraction gain value and a second subtraction gain value, respectively, and sets the back EMF detection signal generated from the back EMF detector circuit as the first value and the second value, respectively.
18. The operating method of the semiconductor integrated circuit according to claim 15,
wherein the back EMF detection signal as an analog back EMF detection signal is generated from the back EMF detector circuit, and
wherein a maximum value of the analog back EMF detection signal is controlled to an allowable maximum voltage lower than an operation power voltage of the semiconductor integrated circuit, and a minimum value of the analog back EMF detection signal is controlled to an allowable minimum voltage higher than a ground voltage of the semiconductor integrated circuit.
19. The operating method of the semiconductor integrated circuit according to claim 15,
wherein the semiconductor integrated circuit comprises
a digital-to-analog converter; and
an analog-to-digital converter,
wherein an output terminal of the digital-to-analog converter is coupled to an input terminal of the motor driver circuit, and
wherein the analog back EMF detection signal as the back EMF detection signal generated by the back EMF detector circuit is supplied to an input terminal of the analog-to-digital converter, and a digital back EMF detection signal is generated from an output terminal of the analog-to-digital converter.
20. The operating method of the semiconductor integrated circuit according to claim 19,
wherein the semiconductor integrated circuit further comprises
a first detection register;
a second detection register;
a third detection register;
a fourth detection register;
a calculation unit; and
a comparator,
wherein, at the time of the calibration operation, the digital back EMF detection signal of the analog-to-digital converter, corresponding to the first value of the back EMF detection signal generated from the back EMF detector circuit in response to the non-zero current flowing through the motor, is stored in the third detection register,
wherein, at the time of the calibration operation, the digital back EMF detection signal of the analog-to-digital converter, corresponding to the second value of the back EMF detection signal generated from the back EMF detector circuit in response to the non-zero current flowing through the motor, is stored in the fourth detection register,
wherein the calculation unit calculates the comparison reference value from the first information stored in the third detection register and the second information stored in the fourth detection register, and stores the calculated comparison reference value in the first detection register,
wherein the digital back EMF detection signal of the analog-to-digital converter, corresponding to the comparison input value generated in response to the gain adjusted by the calibration operation, is stored in the second detection register,
wherein the comparator compares the comparison reference value stored in the first detection register with the digital back EMF detection signal of the analog-to-digital converter stored in the second detection register corresponding to the comparison input value, and
wherein the adjustment unit adjusts the gain of the internal amplifier of the back EMF detector circuit by the calibration operation in response to the comparison result of the comparator.