Author: claimsbot

What is claimed is:

1. A connection detecting connector, comprising:
first and second housings (10, 20; 50, 20) connectable with and separable from each other along a connecting direction (CD), the first housing (20) comprising a slider (40; 60) movable in a direction (SD) oblique to the connecting direction (CD) and a biasing member (30) for biasing the slider (40; 60) forward with respect to the connecting direction (CD), wherein:
a pushing portion (12; 51) provided at the second housing (10, 50) for contacting and pushing a pushable portion (42; 61) of the slider (40; 60) while the housings (10, 20; 50, 20) are being connected, and for moving the slider (40; 60) backward with respect to the connecting direction (CD) while accumulating a force in the biasing member (30), and
the pushing portion (12; 51) and the pushable portion (42; 61) disengaging when the housings (10, 20; 50, 20) substantially reach a properly connected state (FIG. 6; 10), whereby the biasing member (30) is at least partly restored while moving the slider (40; 60) forward with respect to the connecting direction (CD).
2. The connection detecting connector of claim 1, wherein, when the biasing member (30) is restored in the properly connected state (FIG. 6, 10), a lock (42; 61) of the slider (40; 60) engages a rear side of an engaging portion (12; 51) of the second housing (10; 50) with respect to the connecting direction (CD) to lock the two housings (10, 20; 50, 20) together.
3. The connection detecting connector of claim 2, wherein the lock (42; 61) and the engaging portion (12; 51) both comprise a slanted surface (12B, 42B; 51B, 61B) substantially extending along a moving direction (SD) of the slider (40; 60), the lock (42; 61) and the engaging portion (12; 51) being engageable with each other while the slanted surfaces (12B, 42B; 51B, 61B) are held substantially in contact.
4. The connection detecting connector of claim 3, wherein the engaging portion (51) comprises a recess (51) formed on a surface of the second housing (10, 50).
5. The connection detecting connector of claim 4, wherein the pushable portion (42; 61) also acts as the locking portion (42; 61) and the pushing portion (12; 51) also acts as the engaging portion (12; 51).
6. The connection detecting connector of claim 1, wherein the slider (40; 60) is accommodated in the first housing (20) and comprises an unlocking projection (43) for moving the slider (40; 60) backward with respect to the connecting direction (CD).
7. The connection detecting connector of claim 6, wherein the unlocking projection (43) is in a groove (29) formed in the surface of the first housing (20) so as not to project out of the groove (29).
8. The connection detecting connector of claim 1, wherein the pushing portion (12) comprises a projection (12) laterally projecting from the second housing (10).
9. The connection detecting connector of claim 1, wherein the slider (40; 60) comprises at least one guide (41; 61) to interact with at least one corresponding mating guide (27) in the first housing (10) for guiding a movement of the slider (40; 60) along its movement direction (SD).
10. The connection detecting connector of claim 1, wherein the slider (40; 60) comprises at least one for stopping a forward movement of the slider (40; 60) at a front-stop position (FIG. 1, 7; 8, 11).
11. A connection detecting connector, comprising:
first and second housings (10, 20; 50, 20) having front ends that are connectable with one another by moving said housings (10, 20; 50, 20) along a connecting direction (CD);
a slider (40; 60) mounted in the first housing (20) for movement in a moving direction (SD) oblique to the connecting direction (CD), the slider (40; 60) having a pushable surface (42; 61) facing towards the front end of the first housing (20);
a biasing member (30) for biasing the slider (40; 60) toward the front end of the first housing (20);
a pushing surface (12; 51) formed on the second housing (10, 50) and aligned for contacting the pushable surface (42; 61) of the slider (40; 60) while the housings (10, 20; 50, 20) are being connected, and for moving the slider (40; 60) along the moving direction (SD) while accumulating a force in the biasing member (30), and
the pushable portion (42; 61) disengaging from the pushing portion (12; 51) when the housings (10, 20; 50, 20) substantially reach a properly connected state (FIG. 6; 10) such that the biasing member (30) is at least partly restored and returns the slider (40; 60) towards the front end of the first housing (20).
12. The connection detecting connector of claim 11, wherein the biasing member (30) biases the slider (40; 60) into a position for engaging the second housing (10; 50) to lock the two housings (10, 20; 50, 20) together.
13. The connection detecting connector of claim 12, wherein the slider (40; 60) and the second housing (10; 50) both comprise a slanted surface (12B, 42B; 51B, 61B) substantially extending along the moving direction (SD) of the slider (40; 60), the slanted surfaces (12B, 42B; 51B, 61B) being held in contact for locking the housings (10, 20; 50, 20) together.
14. The connection detecting connector of claim 13, wherein the slider (40; 60) is accommodated in the first housing (20) and comprises an unlocking projection (43) for moving the slider (40; 60) backward with respect to the connecting direction (CD).

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An implantable medical device for coupling to a heart having a right atrium (RA), a left atrium (LA), a sinoatrial (SA) node, and an atrial septum through one or more leads including a first electrode for placement near the SA node, a second electrode for placement near the atrial septum, and a third electrode for placement in the LA, the implantable medical device comprising:
a sensing circuit configured to sense a plurality of atrial electrograms using the plurality of atrial electrodes;
an arrhythmia detection circuit configured to detect tachyarrhythmia; and
an arrhythmia classification circuit configured to classify the detected tachyarrhythmia, the arrhythmia classification circuit including:
an atrial signal mapping module configured to map an atrial activation sequence using the sensed plurality of atrial electrograms, the atrial activation sequence indicative of an order of regional depolarizations during an atrial depolarization; and
an atrial pattern analyzer configured to classify the detected tachyarrhythmia using the atrial activation sequence.
2. The implantable medical device of claim 1, wherein the sensing circuit is configured to sense an RA electrogram through the first electrode, an LA electrogram through the third electrode, and an atrial septal electrogram through the second electrode, and the atrial signal mapping module is configured to map an atrial activation sequence using the RA electrogram, the LA electrogram, and the atrial septal electrogram.
3. The implantable medical device of claim 2, further comprising:
an event detection circuit configured to detect an RA event from the RA electrogram and an LA event from the LA electrogram during an atrial depolarization;
an inter-atrial interval measurement circuit configured to measure an inter-aerial interval being a time interval between the RA event and the LA event; and
one or more of an atrial enlargement detection circuit and an atrial conduction disturbance detection circuit, the atrial enlargement detection circuit configured to detect abnormal enlargement of at least one of the RA and LA using the inter-atrial interval, the atrial conduction disturbance detection circuit configured to detect atrial conduction disturbance using the inter-atrial interval.
4. The implantable medical device of claim 3, further comprising the atrial enlargement detection circuit, and the atrial enlargement detection circuit comprises a comparator including a first input to receive the inter-atrial interval, a second input to receive a predetermined threshold interval, and an output to indicate the abnormal enlargement of at least one atrium when the inter-atrial interval exceeds the predetermined threshold interval.
5. The implantable medical device of claim 3, further comprising the atrial conduction disturbance detection circuit, and the atrial conduction disturbance detection circuit is configured to detect a variance of the inter-atrial interval and comprises a comparator including a first input to receive the variance of the inter-atrial interval, a second input to receive a predetermined threshold variance, and an output to indicate the atrial conduction disturbance when the variance of the inter-atrial interval exceeds the predetermined threshold variance.
6. The implantable medical device of claim 1, wherein the atrial pattern analyzer comprises at least two of:
a right atrial pattern matching module configured to detect a supraventricular tachyarrhythmia of a right atrial origin by comparing the atrial activation sequence to a predetermined right atrial pattern template sequence;
a left atrial pattern matching module configured to detect an supraventricular tachyarrhythmia of a left atrial origin by comparing the atrial activation sequence to a predetermined left atrial pattern template sequence; and
an atrial septal pattern matching module configured to detect one of a supraventricular tachyarrhythmia of atrial septal origin and a ventricular tachyarrhythmia by comparing the atrial activation sequence to a predetermined atrial septal pattern template sequence.
7. A cardiac rhythm management system coupled to a heart having a right atrium (RA) connected to a superior vena cava, a left atrium (LA), a left ventricle (LV), a sinoatrial (SA) node, an atrial septum, a coronary sinus, and a coronary vein, the system comprising:
one or more leads including a plurality of atrial electrodes; and
an implantable medical device coupled to the one or more leads, the implantable medical device including:
a sensing circuit configured to sense a plurality of atrial electrograms using the plurality of atrial electrodes;
an arrhythmia detection circuit configured to detect tachyarrhythmia; and
an arrhythmia classification circuit configured to classify the detected tachyarrhythmia, the arrhythmia classification circuit including:
an atrial signal mapping module configured to map an atrial activation sequence using the sensed plurality of atrial electrograms, the atrial activation sequence indicative of an order of regional depolarization during an atrial depolarization; and
an atrial pattern analyzer configured to classify the detected tachyarrhythmia using the atrial activation sequence.
8. The system of claim 7, wherein the one or more leads comprises a first lead including:
an LA electrode configured for placement in the coronary sinus or coronary vein near the LA;
an atrial septal electrode configured for placement in the coronary sinus near the atrial septum; and
a high RA (HRA) electrode configured for placement in the RA or the superior vena cava near the SA node,
wherein the sensing circuit is configured to sense an RA electrogram via the HRA electrode, an LA electrogram via the LA electrode, and an atrial septal electrogram via the atrial septal electrode, and wherein the atrial signal mapping module is configured to map an atrial activation sequence using the RA electrogram, the LA electrogram, and the atrial septal electrogram.
9. The system of claim 8, wherein the implantable medical device comprises:
an event detection circuit configured to detect an RA event from the RA electrogram and an LA event from the LA electrogram during an atrial depolarization; and
an inter-atrial interval measurement circuit configured to measure an inter-atrial interval being a time interval between the RA event and the LA event.
10. The system of claim 9, wherein the implantable medical device further comprises one or more of an atrial enlargement detection circuit and an atrial conduction disturbance detection circuit, the atrial enlargement detection circuit configured to detect abnormal enlargement of at least one of the RA and LA using the inter-atrial interval, the atrial conduction disturbance detection circuit configured to detect atrial conduction disturbance using the inter-atrial interval.
11. The system of claim 10, wherein the implantable medical device comprises the atrial enlargement detection circuit, and the atrial enlargement detection circuit comprises a comparator including a first input to receive the inter-atrial interval, a second input to receive a predetermined threshold interval, and an output to indicate the abnormal enlargement of at least one atrium when the inter-atrial interval exceeds the predetermined threshold interval.
12. The system of claim 10, wherein the implantable medical device comprises the atrial conduction disturbance detection circuit, and the atrial conduction disturbance detection circuit is configured to detect a variance of the inter-atrial interval and comprises a comparator including a first input to receive the variance of the inter-atrial interval, a second input to receive a predetermined threshold variance, and an output to indicate the atrial conduction disturbance when the variance of the inter-atrial interval exceeds the predetermined threshold variance.
13. The system of claim 8, wherein the first lead further comprises an LV electrode configured for placement in the coronary vein over the LV, the sensing circuit is further configured to sense an LV electrogram via the LV electrode, and the atrial pattern analyzer is configured to classify the tachyarrhythmia using the atrial activation sequence and the LV electrogram.
14. The system of claim 9, wherein the one or more leads comprises a first lead and a second lead, the first lead including a high RA (HRA) electrode configured for placement in the RA or the superior vena cava near the SA node and a second RA electrode configured for placement in the RA, the second lead including an LA electrode configured for placement in the coronary sinus or coronary vein near the LA, wherein the sensing circuit is configured to sense an RA electrogram via the HRA electrode, an LA electrogram via the LA electrode, and an atrial septal electrogram via the second atrial electrode, and wherein the atrial signal mapping module is configured to map an atrial activation sequence using the RA electrogram, the LA electrogram, and the atrial septal electrogram.
15. The system of claim 14, wherein the implantable medical device further comprises:
an event detection circuit configured to detect an RA event from the RA electrogram and an LA event from the LA electrogram during an atrial depolarization; and
an inter-atrial interval measurement circuit configured to measure a time interval between the RA event and the LA event.
16. The system of claim 15, wherein the implantable medical device further comprises one or more of an atrial enlargement detection circuit and an atrial conduction disturbance detection circuit, the atrial enlargement detection circuit configured to detect abnormal enlargement of at least one atrium using the inter-atrial interval, the atrial conduction disturbance detection circuit configured to detect atrial conduction disturbance using the inter-atrial interval.
17. The system of claim 16, wherein the implantable medical device comprises the atrial enlargement detection circuit, and the atrial enlargement detection circuit comprises a comparator including a first input to receive the inter-atrial interval, a second input to receive a predetermined threshold interval, and an output to indicate the abnormal enlargement of at least one atrium when the inter-atrial interval exceeds the predetermined threshold interval.
18. The system of claim 16, wherein the implantable medical device comprises the atrial conduction disturbance detection circuit, and the atrial conduction disturbance detection circuit is configured to detect a variance of the inter-atrial interval and comprises a comparator including a first input to receive the variance of the inter-atrial interval, a second input to receive a predetermined threshold variance, and an output to indicate the atrial conduction disturbance when the variance of the inter-atrial interval exceeds the predetermined threshold variance.
19. The system of claim 14, wherein the second lead further comprises an LV electrode configured for placement in the coronary vein over the LV, wherein the sensing circuit is further configured to sense an LV electrogram via the LV electrode, and wherein the atrial pattern analyzer is configured to classify the tachyarrhythmia using the atrial activation sequence and the LV electrogram.
20. The system of claim 7, wherein the atrial pattern analyzer comprises at least two of:
a right atrial pattern matching module configured to detect a supraventricular tachyarrhythmia of a right atrial origin by comparing the atrial activation sequence to a predetermined right atrial pattern template sequence;
a left atrial pattern matching module configured to detect an supraventricular tachyarrhythmia of a left atrial origin by comparing the atrial activation sequence to a predetermined left atrial pattern template sequence; and
an atrial septal pattern matching module configured to detect one of a supraventricular tachyarrhythmia of atrial septal origin and a ventricular tachyarrhythmia by comparing the atrial activation sequence to a predetermined atrial septal pattern template sequence.

1. A semiconductor package, comprising:
a first semiconductor package including,
a first package substrate,
first and second memory chips on the first package substrate, the first and second memory chips spaced apart from each other in a first direction,
third and fourth memory chips on the first and second memory chips, respectively, and
first and second jumper chips on the first and second memory chips, respectively, the first and second jumper chips spaced apart from the third and fourth memory chips, respectively, in a second direction crossing the first direction; and
a second semiconductor package, the first semiconductor package on the second semiconductor package, the second semiconductor package including,
a second package substrate, and
a logic chip on the second package substrate.
2. The semiconductor package of claim 1, wherein
the first package substrate includes first and second edges facing each other,
each of the first to fourth memory chips include memory data pads and memory commandaddress pads, which are electrically connected to the logic chip, the memory data pads and the memory commandaddress pads in each of the first to fourth memory chips, respectively, are spaced apart from each other in the second direction, and
the memory data pads and the memory commandaddress pads in each of the first to fourth memory chips, respectively, are arranged parallel to the first edge.
3. The semiconductor package of claim 2, wherein
the second package substrate includes first DQ coupling pads, second DQ coupling pads, first CA coupling pads, and second CA coupling pads,
the first DQ coupling pads and the first CA coupling pads face each other and are electrically connected to the first and third memory chips,
the second DQ coupling pads and the second CA coupling pads face each other and are electrically connected to the second and fourth memory chips, and
when viewed in a plan view,
the first and second DQ coupling pads are adjacent to the memory data pads of the first to fourth memory chips, and
the first and second CA coupling pads are adjacent to the memory commandaddress pads of the first to fourth memory chips.
4. The semiconductor package of claim 3, wherein
the logic chip includes first data pads, second data pads, first commandaddress pads, and second commandaddress pads,
the first data pads and the first commandaddress pads are electrically connected to the first and third memory chips,
the first data pads and the first commandaddress pads face each other,
the second data pads and the second commandaddress pads are electrically connected to the second and fourth memory chips,
the second data pads and the second commandaddress pads face each other,
the first and second data pads are adjacent to the first and second DQ coupling pads, respectively, and
the first and second commandaddress pads are adjacent to the first and second CA coupling pads, respectively.
5. The semiconductor package of claim 3, wherein
the logic chip includes first data pads, second data pads, first commandaddress pads, second commandaddress pads, a first side surface, and a second side surface,
the first data pads and the first commandaddress pads are electrically connected to the first and third memory chips,
the first data pads and the first commandaddress pads face each other,
the second data pads and the second commandaddress pads are electrically connected to the second and fourth memory chips,
the second data pads and the second commandaddress pads face each other,
the first and second side surfaces are adjacent to each other,
the first data pads are adjacent to the first side surface,
the second data pads are adjacent to the second side surface, and
when viewed in a plan view, the second data pads are adjacent to the memory data pads of the first to fourth memory chips.
6. The semiconductor package of claim 2, wherein
the second package substrate includes first to fourth DQ coupling pads, first CA coupling pads, and second CA coupling pads along one side surface of the second package substrate,
the first DQ coupling pads, the second DQ coupling pads, and the first CA coupling pads are electrically connected to the first and third memory chips,
the third DQ coupling pads, the fourth DQ coupling pads, and the second CA coupling pads are electrically connected to the second and fourth memory chips,
the first CA coupling pads are between the first and second DQ coupling pads, and
the second CA coupling pads are between the third and fourth DQ coupling pads.
7. The semiconductor package of claim 6, wherein
the logic chip includes first to fourth data pads, first commandaddress pads, and second commandaddress pads along one side surface of the logic chip,
the first data pads, the second data pads, and the first commandaddress pads are electrically connected to the first and third memory chips,
the third data pads, the fourth data pads, and the second commandaddress pads are electrically connected to the second and fourth memory chips,
the first to fourth data pads are adjacent to the first to fourth DQ coupling pads, respectively, and
the first and second commandaddress pads are adjacent to the first and second CA coupling pads, respectively.
8. The semiconductor package of claim 1, wherein
each of the first to fourth memory chips include first to fourth memory data pads, first memory commandaddress pads, and second memory commandaddress pads,
the first memory data pads, the second memory data pads, and the first memory commandaddress pads are adjacent to a side of the semiconductor package,
the third memory data pads, the fourth memory data pads, and the second memory commandaddress pads are adjacent to an opposite side of the semiconductor package, the first memory commandaddress pads are between the first and second memory data pads, and the second memory commandaddress pads are between the third and fourth memory data pads.
9. The semiconductor package of claim 8, wherein
the second package substrate includes first to eighth DQ coupling pads, and first to fourth CA coupling pads,
the first to fourth DQ coupling pads, the first CA coupling pads, and the second CA coupling pads are electrically connected to the first and third memory chips,
the fifth to eighth DQ coupling pads, the third CA coupling pads, and the fourth CA coupling pads are electrically connected to the second and fourth memory chips, and
when viewed in a plan view,
the first DQ coupling pads, the second DQ coupling pads, and the first CA coupling pads are adjacent to the first memory data pads, the second memory data pads, and the first memory commandaddress pads, respectively, of the first memory chip,
the third DQ coupling pads, the fourth DQ coupling pads, and the second CA coupling pads are adjacent to the third memory data pads, the fourth memory data pads, and the second memory commandaddress pads, respectively, of the first memory chip,
the fifth DQ coupling pads, the sixth DQ coupling pads, and the third CA coupling pads are adjacent to the first memory data pads, the second memory data pads, and the first memory commandaddress pads, respectively, of the second memory chip, and
the seventh DQ coupling pads, the eighth DQ coupling pads, and the fourth CA coupling pads are adjacent to the third memory data pads, the fourth memory data pads, and the second memory commandaddress pads, respectively, of the second memory chip.
10. The semiconductor package of claim 9, wherein
the logic chip includes first to eighth data pads, and first to fourth commandaddress pads,
the first to the fourth data pads, the first commandaddress pads, and the second commandaddress pads are electrically connected to the first and third memory chips; and
the fifth to the eighth data pads, the third commandaddress pads, and the fourth commandaddress pads are electrically connected to the second and fourth memory chips,
the first to eighth data pads are adjacent to the first to eighth DQ coupling pads, respectively, and
the first to fourth commandaddress pads are adjacent to the first to fourth CA coupling pads, respectively.
11. The semiconductor package of claim 9, wherein
the logic chip includes first to eighth data pads, first to fourth commandaddress pads, and first to fourth side surfaces,
the first to fourth data pads, the first commandaddress pads, and the second commandaddress pads are connected to the first and third memory chips,
the fifth to eighth data pads, the third commandaddress pads, and the fourth commandaddress pads are connected to the second and fourth memory chips,
the first and the second side surfaces of the logic chip are adjacent to each other,
the third and the fourth side surfaces of the logic chip face the first and second side surfaces, respectively, of the logic chip,
the first data pads, the second data pads, and the first commandaddress pads are adjacent to the first side surface of the logic chip,
the third data pads, the fourth data pads, and the second commandaddress pads are adjacent to the second side surface of the logic chip,
the fifth data pads, the sixth data pads, and the third commandaddress pads are adjacent to the third side surface of the logic chip, and
the seventh data pads, the eighth data pads, and the fourth commandaddress pads are adjacent to the fourth side surface of the logic chip.
12. The semiconductor package of claim 1, further comprising:
wires, wherein
each of the first and second jumper chips include first and second wire bonding pads spaced apart from each other in the second direction,
the first and second wire bonding pads are arranged along the first direction, and
the first wire bonding pads are connected to the third and fourth memory chips through the wires.
13. The semiconductor package of claim 1, wherein a memory capacity of each of the first and second memory chips is twice a memory capacity of each of the third and fourth memory chips.
14. A semiconductor package, comprising:
a package substrate;
a logic chip on the package substrate;
first and second memory chips on the package substrate, the first and second memory chips electrically connected to the logic chip, the first and second memory chips spaced apart from the logic chip in a first direction, the first and second memory chips spaced apart from each other in a second direction crossing the first direction;
third and fourth memory chips on the first and second semiconductor chips, respectively, the third and fourth memory chips electrically connected to the logic chip, a memory capacity of the first and second memory chips being twice a memory capacity of the third and fourth memory chips; and
first and second jumper chips on the first and second semiconductor chips, respectively, the first and second jumper chips spaced apart from the third and fourth memory chips, respectively, in the first direction.
15. The semiconductor package of claim 14, further comprising:
wires, wherein
the logic chip includes first to fourth data pads, first commandaddress pads, and second commandaddress pads along one side surface of the logic chip,
the first commandaddress pads are between the first and second data pads,
the second commandaddress pads are between the third and fourth data pads,
each of the first to fourth memory chips includes memory data pads and memory commandaddress pads spaced apart from each other in the first direction,
the memory data pads are arranged along and adjacent to the one side surface of the logic chip,
each of the first and second jumper chips includes first wire bonding pads and second wire bonding pads spaced apart from each other in the first direction, and
the first and second wire bonding pads are arranged parallel to the memory data pads, and
the first wire bonding pads are connected to the third and fourth memory chips through the wires.
16. A semiconductor package, comprising:
a first substrate;
a logic chip on the first substrate, the logic chip including a first number of data pads and a second number of communication pads;
a second substrate on the logic chip;
first memory chips spaced apart from each other in a first direction on the second substrate, the first memory chips including a first quantity of first memory data pads and a second quantity of first memory commandaddress pads, which are electrically connected to the logic chip;
second memory chips on the first memory chips, the second memory chips including a third of quantity of second memory data pads and a fourth quantity of second memory commandaddress pads, which are electrically connected to the logic chip; and
jumper chips on the first memory chips, the jumper chips spaced apart from the second memory chips in a second direction crossing the first direction, the jumper chips including a fifth quantity of first wire bond pads and second wire bond pads, respectively, which are electrically connected to the logic chip.
17. The semiconductor package of claim 16, wherein
a number of the first memory chips equals a number of the second memory chips,
a number of the jumper chips equals the number of first memory chips, and
a memory capacity of the first memory chips is greater than a memory capacity of the second memory chips.
18. The semiconductor package of claim 16, wherein the data pads and the communication pads in the logic chip are not on a same side of the logic chip.
19. The semiconductor package of claim 16, wherein a portion of the data pads and a portion of the communication pads in the logic chip are arranged on at least one same side of the logic chip.
20. The semiconductor package of claim 16, wherein
the first memory data pads and the first memory commandaddress pads are not on a same side of the first memory chips, and
the second memory data pads and the second memory commandaddress pads are not on a same side of the second memory chips.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A permanently closed containment pant comprising,
an elastically extensible chassis defining a waist opening, a first leg opening, and a second leg opening, the waist opening comprising a front waist region joined with a back waist region, wherein the chassis has a transverse elongation of between 125% and 175% at 2000 g*f and a longitudinal elongation of between 125% and 175% at 2000 g*f, and
a sling positioned within the chassis and being joined to the front waist region and the back waist region, wherein the sling comprises a fluid-impervious base sheet and a containment flap joined with the base sheet to create a fluid-impervious pouch, the sling further comprising a first transition and a second transition that are elastically extensible in a longitudinal direction and in a transverse direction, wherein the base sheet is a fabric to define a first fabric surface and the containment flap is a fabric to define a second fabric surface wherein the base sheet is joined with the containment flap, wherein the base sheet has a transverse elongation of between 10% and 40% at 1400 g*f and a longitudinal elongation of between 10% and 40% at 1400 g*f;
wherein the base sheet is a first fabric laminated with polyurethane to define a polyurethane surface and a fabric surface and the containment flap is a second fabric laminated with polyurethane to define a second fabric surface and a second polyurethane surface wherein the first polyurethane surface is joined with the second polyurethane surface.
2. The permanently closed containment pant of claim 1 wherein the sling further comprises the first transition and the second transition that are elastically extensible in a longitudinal direction and in a transverse direction.
3. The permanently closed containment pant of claim 2 wherein the base sheet is a woven polyester fabric laminated with a polyurethane sheet.
4. The permanently closed containment pant of claim 3 wherein the first transition is a discrete piece of material joined between the pouch and the waist elastic in the front waist region and wherein the second transition is a discrete piece of material joined between the pouch and the waist elastic in the back waist region.
5. The permanently closed containment pant of claim 3 wherein the chassis includes a shell material and wherein the first transition is an integral part of and a distinct projection of the shell material joined between the pouch and the waist elastic in the front waist region and wherein the second transition is a discrete piece of material joined between the pouch and the waist elastic in the back waist region.
6. The permanently closed containment pant of claim 1 wherein the sling is attached to the chassis in a crotch region with a tab and wherein
the tab is a discrete piece of material and is ultrasonically bonded to the pouch and is sewed with thread to the chassis; or
the tab is an integral part of the containment flap, is a distinct projection of the containment flaps, and is sewed with thread to the chassis; or
the tab is an integral part of the base sheet, is a distinct projection of the base sheet, and is sewed with thread to the chassis.
7. The permanently closed containment pant of claim 1 wherein the fluid-impervious pouch defines a pouch floor having a first end section, a second end section, and a central section extending between the first end section and the second end section, wherein the first end section defines a maximum width, the second end section defines a maximum width equal to the maximum width of the first end section, and the central section defines a maximum width that is less than 70% the maximum width of the first and second end sections.
8. The permanently closed containment pant of claim 1 wherein the chassis comprises a shell material made of cotton and 2-25% spandex.
9. The permanently closed containment pant of claim 1 further comprising
a waistband extending around 100% of the waist opening and being cantilevered relative to a shell material and
a first leg elastic extending around 100% of the first leg opening and a second leg elastic extending around 100% of the second leg opening, wherein the first leg elastic and the second leg elastic are cantilevered relative to the shell material.
10. A permanently closed containment pant comprising,
an elastically extensible chassis defining a waist opening, a first leg opening, and a second leg opening, the waist opening comprising a front waist region joined with a back waist region, wherein a peak load of the chassis in the transverse direction and in the longitudinal direction is between about 10,000 grams force and about 30,000 grams force, and
a sling positioned within the chassis and being joined to the front waist region and the back waist region, wherein the sling comprises a fluid-impervious base sheet and a containment flap joined with the base sheet to create a fluid-impervious pouch, the sling further comprising a first transition and a second transition that are elastically extensible in a longitudinal direction and in a transverse direction, wherein the base sheet is a fabric

and a first fabric surface and the containment flap is a fabric to define a second fabric surface wherein the first fabric surface is joined with the second fabric surface, and wherein a peak load of the base sheet in the transverse direction and in the longitudinal direction is between about 10,000 grams force and about 30,000 grams force;
wherein the fluid-impervious pouch defines a pouch floor having a first end section, a second end section, and a central section extending between the first end section and the second end section, wherein the first end section defines a maximum width, the second end section defines a maximum width equal to the maximum width of the first end section, and the central section defines a maximum width that is less than 70% the maximum width of the first and second end sections.
11. The permanently closed containment pant of claim 10 wherein the first transition is made of a first material, the second transition is made of the same first material, and the chassis is made of the same first material, wherein the first material is 75-98% cotton and 2-25% spandex, the base sheet is a polyester fabric laminated with polyurethane, and the containment flap is a polyester fabric laminated with polyurethane.
12. The permanently closed containment pant of claim 10 wherein the sling further comprises the first transition and the second transition that are elastically extensible in a longitudinal direction and in a transverse direction.
13. The permanently closed containment pant of claim 12 wherein the base sheet is a woven polyester fabric laminated with a polyurethane sheet.
14. The permanently closed containment pant of claim 13 wherein the first transition is a discrete piece of material joined between the pouch and the waist elastic in the front waist region and wherein the second transition is a discrete piece of material joined between the pouch and the waist elastic in the back waist region.
15. The permanently closed containment pant of claim 13 wherein the chassis includes a shell material and wherein the first transition is an integral part of and a distinct projection of the shell material joined between the pouch and the waist elastic in the front waist region and wherein the second transition is a discrete piece of material joined between the pouch and the waist elastic in the back waist region.
16. A permanently closed containment pant comprising,
an elastically extensible chassis defining a waist opening and a pair of leg openings, the chassis comprising a waist elastic joined proximate to and encircling the waist opening and a pair of leg elastics joined proximate to and encircling the leg openings, the waist opening defining a front waist region and a back waist region, wherein the chassis has a breathability of between about 10,000 and about 35,000 grams(m2-24 hours), and
a sling comprising a fluid-impervious pouch joined between a first transition and a second transition, wherein the sling is joined with the waist elastic in the front waist region via the first transition and is joined with the waist elastic in the back waist region via the second transition, wherein the first transition and the second transition are elastically extensible in a transverse direction, wherein the fluid-impervious pouch comprises a polyester and polyurethane laminate, wherein the base sheet has a breathability of between about 500 and about 2500 grams(m2-24 hours);
wherein the fluid-impervious pouch comprises a base sheet and a containment flap bonded to the base sheet wherein the base sheet is a polyester fabric laminated with polyurethane to define a polyurethane surface and a polyester fabric surface and the containment flap is a second polyester fabric laminated with polyurethane to define a second polyester fabric surface and a second polyurethane surface wherein the first polyurethane surface is joined with the second polyurethane surface via an ultrasonic bond, thermal bond, or pressure bond.
17. The permanently closed containment pant of claim 16 wherein the containment flap defines a proximal portion and a distal portion having a distal edge, wherein the proximal portion is joined with the base sheet and the distal portion includes a flap elastic folded over the distal edge of the flap, wherein the flap elastic defines a first tension zone, a second tension zone, and a third tension zone along a length of the containment flap, wherein the second tension zone is located between the first tension zone and the third tension zone and wherein the flap elastic has a greater tension in the second tension zone than in the first tension zone or the third tension zone.
18. The containment pant of claim 16 wherein the fluid-impervious pouch defines a pouch floor having a first end section, a second end section, and a central section extending between the first end section and the second end section, wherein the first end section defines a maximum width, the second end section defines a maximum width equal to the maximum width of the first end section, and the central section defines a maximum width that is less than 70% the maximum width of the first and second end sections.