Author: claimsbot

1. A temperature controlled stroller blanket comprising:
a top side;
a bottom side, the bottom side comprising a layer of waterproof material backed with a layer of water-absorbent material such that the layer of water-absorbent material is integral with and affixed to the layer of waterproof material;
an insulating batting disposed between the top side and the bottom side; and
a plurality of pockets formed on the bottom side, the pockets each having a pocket wall connected to the bottom side to form the pocket, the pocket wall having a water-absorbent inner surface and a waterproof outer surface, such that each pocket comprises an interior area defined by the water-absorbent inner surface of the pocket wall and a portion of the waterproof material of the bottom side,
wherein the plurality of pockets are disposed about substantially all of the bottom side.
2. The temperature controlled stroller blanket of claim 1 wherein the waterproof outer surface of the pocket wall comprises vinyl.
3. The temperature controlled stroller blanket of claim 1 wherein the plurality of pockets are sealable.
4. The temperature controlled stroller blanket of claim 1 wherein the plurality of pockets are resealable.
5. The temperature controlled stroller blanket of claim 4 wherein the plurality of pockets further comprise a hook-and-loop type closure.
6. The temperature controlled stroller blanket of claim 1 further comprising a plurality of slits formed in the top side and the bottom side, and extending between the top side and the bottom side.
7. The temperature controlled stroller blanket of claim 1 wherein the plurality of pockets are configured to store a temperature pack.
8. The temperature controlled stroller blanket of claim 1 further comprising at least one temperature pack disposed in at least one of the plurality of pockets.
9. The temperature controlled stroller blanket of claim 1 wherein the waterproof material of the bottom side comprises vinyl.
10. The temperature controlled stroller blanket of claim 1 wherein the insulating batting is comprised of cotton.
11. The temperature controlled stroller blanket of claim 1 wherein the insulating batting is comprised of polyester.
12. The temperature controlled stroller blanket of claim 1 wherein the top side is comprised of fleece.
13. The temperature controlled stroller blanket of claim 1 wherein the top side and the bottom side are quilted together.
14. The temperature controlled stroller blanket of claim 13 further comprising a piping disposed about a perimeter of the blanket.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A microprocessor-based system for generating an electronic document, the microprocessor-based system comprising:
a program memory configured to store an instruction node comprising at least one microprocessor-readable instruction;
a cache memory configured to store a cache key value and a data item associated with the stored cache key value;
a requester subsystem configured to receive the instruction node from the program memory; and
an interpreter subsystem configured to
if the instruction node is eligible for caching, compare a cache key value associated with the instruction node with a cache key value stored in a cache memory and associated with a data item, and
if the cache key value associated with the instruction node matches the cache key value stored in the cache memory, retrieve the data item with the cache key value stored in the cache memory, and generate at least a portion of the electronic document as a function of the retrieved data item,

whereby the interpreter subsystem generates portions of the electronic document that are associated with instruction nodes associated with stored cache key values by retrieving data items from the cache memory rather than executing such instruction nodes.
2. The microprocessor-based system of claim 1, wherein the interpreter subsystem is further configured to calculate the cache key value associated with the instruction node.
3. The microprocessor-based system of claim 1, wherein the cache key value associated with the instruction node is encoded in the instruction node.
4. The microprocessor-based system of claim 1, wherein the interpreter subsystem is further configured to, when the cache key value associated with the instruction node does not match the stored cache key value:
execute the at least one microprocessor-readable instruction of the instruction node to obtain a result;
generate at least a portion of the electronic document as a function of the result; and
store the result as a data item in the cache memory.
5. The microprocessor-based system of claim 1, wherein the interpreter subsystem is further configured to identify the instruction node as not eligible for caching if the instruction node contains a microprocessor-readable instruction designating the instruction node as not eligible for caching.
6. The microprocessor-based system of claim 5, wherein the interpreter subsystem is further configured to, in response to identifying the instruction node as not eligible for caching:
execute the at least one microprocessor-readable instruction of the instruction node to obtain a result; and
generate at least a portion of the electronic document as a function of the result without storing the result as a data item in the cache memory.
7. The microprocessor-based system of claim 1, wherein the instruction node comprises at least one child instruction node.
8. The microprocessor-based system of claim 1, wherein the microprocessor-based system is configured to execute a plurality of instruction nodes using a multi-threaded execution technique.
9. A method for generating an electronic document as a function of a set of microprocessor-readable instructions, the method comprising:
receiving an instruction node comprising at least one microprocessor-readable instruction from the set of microprocessor-readable instructions;
if the instruction node is eligible for caching, comparing a cache key value associated with the instruction node with a cache key value stored in a cache memory and associated with a data item;
if the cache key value associated with the instruction node matches the cache key value stored in the cache memory, retrieving the data item with the cache key value stored in the cache memory; and
generating at least a portion of the electronic document as a function of the retrieved data item.
10. The method of claim 9, further comprising calculating the cache key value associated with the instruction node.
11. The method of claim 9, wherein the cache key value associated with the instruction node is encoded in the instruction node.
12. The method of claim 9, further comprising, when the cache key value associated with the instruction node does not match the stored cache key value:
executing the at least one microprocessor-readable instruction of the instruction node to obtain a result;
generating at least a portion of the electronic document as a function of the result; and
storing the result as a data item in the cache memory.
13. The method of claim 9, further comprising identifying the instruction node as not eligible for caching if the instruction node contains a microprocessor-readable instruction designating the instruction node as not eligible for caching.
14. The method of claim 13, further comprising, in response to identifying the instruction node as not eligible for caching:
executing the at least one microprocessor-readable instruction of the instruction node to obtain a result; and
generating at least a portion of the electronic document as a function of the result without storing the result as a data item in the cache memory.
15. The method of claim 9, wherein the instruction node comprises at least one child node.
16. The method of claim 9, further comprising:
receiving a plurality of instruction nodes each comprising at least one microprocessor-readable instruction from the set of microprocessor-readable instructions; and
executing the instruction nodes using a multi-threaded execution technique.
17. A microprocessor-readable medium containing microprocessor-readable instructions that, when executed using a microprocessor-based system, cause the microprocessor-based system to perform a method for generating an electronic document, the method comprising:
receiving an executable instruction node from a program memory;
if the executable instruction node is eligible for caching, comparing a cache key value associated with the executable instruction node with a cache key value stored in a cache memory and associated with a data item;
if the cache key value associated with the executable instruction node matches the cache key value stored in the cache memory, retrieving the data item with the cache key value stored in the cache memory; and
generating at least a portion of the electronic document as a function of the retrieved data item.
18. The microprocessor-readable medium of claim 17, containing further microprocessor-readable instructions that, when executed using the microprocessor-based system, cause the microprocessor-based system to calculate the cache key value associated with the instruction node.
19. The microprocessor-readable medium of claim 17, wherein the cache key value associated with the instruction node is encoded in the instruction node.
20. The microprocessor-readable medium of claim 17, containing further microprocessor-readable instructions that, when executed using the microprocessor-based system, cause the microprocessor-based system to, when the cache key value associated with the instruction node does not match the stored cache key value:
execute the at least one microprocessor-readable instruction of the instruction node to obtain a result;
generate at least a portion of the electronic document as a function of the result; and
store the result as a data item in the cache memory.
21. The microprocessor-readable medium of claim 17, containing further microprocessor-readable instructions that, when executed using the microprocessor-based system, cause the microprocessor-based system to identify the instruction node as not eligible for caching if the instruction node contains a microprocessor-readable instruction designating the instruction node as not eligible for caching.
22. The microprocessor-readable medium of claim 21, containing further microprocessor-readable instructions that, when executed using the microprocessor-based system, cause the microprocessor-based system to, in response to identifying the instruction node as not eligible for caching:
execute the at least one microprocessor-readable instruction of the instruction node to obtain a result; and
generate at least a portion of the electronic document as a function of the result without storing the result as a data item in the cache memory.
23. The microprocessor-readable medium of claim 17, wherein the executable instruction node comprises at least one child node.
24. The microprocessor-readable medium of claim 17, containing further microprocessor-readable instructions that, when executed using the microprocessor-based system, cause the microprocessor-based system to:
receive a plurality of executable instruction nodes from the program memory; and
execute the instruction nodes using a multi-threaded execution technique.

1. An optical deflector element comprising:
a light incoming surface into which enters a light emitted from a light-emitting face of a light guide having a light-incident face into which a light emitted from a primary light source enters; and
a light outgoing surface which is positioned on a side opposite to the light incoming surface and from which the light is emitted,
wherein plural elongated prisms are arrayed in parallel with each other on the light incoming surface, and each of the elongated prisms is constituted by a top end flat face having an inclination angle of 1 to 50 degrees and positioned at a top end part of the elongated prism, a first prism face positioned on one side of the top end flat face, and a second prism face positioned on another side of the top end flat face,
wherein the first prism face is a flat face and the second prism face is a curve face.
2. The optical deflector element as set forth in claim 1, wherein the top end flat face has a size of 0.008P to 0.088P in a cross section perpendicular to an elongated direction of the elongated prism where P is pitch of the elongated prism.
3. The optical deflector element as set forth in claim 1, wherein at least one of the first and second prism faces is constituted by a convex curve face.
4. The optical deflector element as set forth in claim 3, wherein the convex curve face has a cross-section perpendicular to the elongated direction of the elongated prism, the cross-section having an arc-like shape.
5. The optical deflector element as set forth in claim 4, wherein a ratio rP of a curvature radius r of the convex curve face to the pitch P of the elongated prisms is 2 to 50.
6. The optical deflector element as set forth in claim 3, wherein the prism face constituted by the convex curve face has a ratio dP of a maximum distance d between the prism face and a virtual plane connecting a top edge and a bottom edge to the pitch P of the elongated prisms, the ratio dP being 0.1 to 5%.
7. The optical deflector element as set forth in claim 1, wherein at least one of the first and second prism faces is constituted by plural faces, and each of the plural faces is constituted by a flat face or convex curve face.
8. The optical deflector element as set forth in claim 7, wherein the plural faces include a flat face adjacent to the top end flat face, and a convex curve face adjacent to the flat face.
9. The optical deflector element as set forth in claim 8, wherein the convex curve face has a cross-section perpendicular to the elongated direction of the elongated prism, the cross-section having an arc-like shape.
10. The optical deflector element as set forth in claim 9, wherein a ratio rP of a curvature radius r of the convex curve face to the pitch P of the elongated prisms is 2 to 50.
11. The optical deflector element as set forth in claim 7, wherein any of the first and second prism faces that is constituted by plural faces has a ratio dP of a maximum distance d between the prism face and a virtual plane connecting a top edge and a bottom edge to the pitch P of the elongated prisms, the ratio dP being 0.1 to 5%.
12. A light source device comprising:
a primary light source;
a light guide having a light-incident face into which light emitted from the primary light source enters, and a light-emitting face from which guided light is emitted; and
the optical deflector element as set forth in any one of claims 1 to 11 provided adjacent to the light guide on a side of the light-emitting face thereof.
13. The light source device as set forth in claim 12, wherein an inclination angle of the top end flat face of the optical deflector element is an angle at which peak light in light emitted from the light-emitting face of the light guide does not enter into the optical deflector element through the top end flat face of the optical deflector element.
14. The light source device as set forth in claim 13, wherein the peak light is emitted from the light-emitting face in a direction at an angle of 10\xb0 to 40\xb0 with respect to the light-emitting face.
15. The light source device as set forth in claim 12, wherein the first prism face of the elongated prism is positioned closer to the primary light source than the second prism face, the first prism face is constituted by a flat face, the second prism face is constituted by a convex curve face or plural faces, and each of the plural faces is constituted by a flat face or a convex curve face.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image sensor, comprising:
a gate structure on a semiconductor layer of a first conductive type;
a first impurity region of the first conductive type aligned with one side of the gate structure and extending to a first depth from a surface portion of the semiconductor layer;
a first spacer formed on each sidewall of the gate structure;
a second impurity region of the first conductive type, aligned with the first spacer and extending to a second depth that is larger than the first depth from the surface portion of the semiconductor layer;
a second spacer formed on each sidewall of the first spacer;
a third impurity region of the first conductive type aligned with the second spacer and extending to a third depth that is larger than the second depth from the surface portion of the semiconductor layer; and
a fourth impurity region of a second conductive type beneath the third impurity region.
2. The image sensor of claim 1, wherein the second spacer has a thickness ranging from approximately 500 \u212b to approximately 1,000 \u212b.
3. The image sensor of claim 1, wherein the first spacer and the second spacer include one of an oxide-based material and a nitride-based material.
4. The image sensor of claim 1, further including a floating diffusion region of the second conductive type aligned with the other side of the gate structure and extending to a predetermined depth from another surface portion of the semiconductor layer.
5. The image sensor of claim 1, wherein the semiconductor layer includes:
a highly-doped first conductive type substrate; and
a first conductive type epi layer formed on the highly-doped first conductive type substrate.
6. An image sensor, comprising:
a gate structure on a semiconductor layer of a first conductive type;
a first impurity region of the first conductive type aligned with one side of the gate structure and extending to a first depth from a surface portion of the semiconductor layer;
a spacer formed on each sidewall of the gate structure;
a second impurity region of the first conductive type aligned with the spacer and extending to a second depth that is larger than the first depth from the surface portion of the semiconductor layer;
a screening insulation layer formed over the spacer and the semiconductor layer;
a third impurity region of the first conductive type aligned with an upper structure where the spacer is overlaid with the screening insulation layer and extending to a third depth that is larger than the second depth from the surface portion of the semiconductor layer; and
a fourth impurity region of a second conductive type beneath the third impurity region.
7. The image sensor of claim 6, wherein the spacer includes one of an oxide-based material and a nitride-based material and the screening insulation layer includes an oxide-based material.
8. The image sensor of claim 6, further including a floating diffusion region of the second conductive type aligned with the other side of the gate structure and extending to a predetermined depth from another surface portion of the semiconductor layer.
9. The image sensor of claim 6, wherein the semiconductor layer includes a highly doped first conductive type substrate and a first conductive type epi layer on the highly doped first conductive type substrate.
10. The image sensor of claim 6, wherein the screening insulation layer has a thickness ranging from approximately 500 \u212b to approximately 1,000 \u212b.