1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate having PFET areas and NFET areas;
selectively forming first silicide contacts from a first metal in the PFET areas; and
selectively forming second silicide contacts from a second metal in the NFET areas, wherein the second metal is different from the first metal.
2. The method of claim 1 wherein selectively forming first silicide contacts from a first metal in the PFET areas comprises:
selectively forming the first metal overlying the semiconductor substrate in the PFET areas; and
annealing the first metal overlying the semiconductor substrate in the PFET areas to form the first silicide contacts.
3. The method of claim 2 wherein selectively forming the first metal overlying the semiconductor substrate in the PFET areas comprises:
etching a dielectric material overlying the PFET areas and the NFET areas to expose the PFET areas and the NFET areas;
depositing the first metal over the semiconductor substrate in the PFET areas and the NFET areas; and
removing the first metal from the semiconductor substrate in the NFET areas before annealing the first metal.
4. The method of claim 3 further comprising removing non-silicided portions of the first metal from the PFET areas after annealing the first metal.
5. The method of claim 2 wherein selectively forming the first metal overlying the semiconductor substrate in the PFET areas comprises:
etching a dielectric material overlying the PFET areas and the NFET areas to expose the PFET areas; and
depositing the first metal over the semiconductor substrate in the PFET areas and over the dielectric material in the NFET areas.
6. The method of claim 5 further comprising removing non-silicided portions of the first metal from the PFET areas and from the NFET areas after annealing the first metal.
7. The method of claim 1 wherein selectively forming second silicide contacts from a second metal in the NFET areas comprises:
depositing the second metal over the semiconductor substrate in the PFET areas and the NFET areas, wherein the first silicide contacts form a barrier between the second metal and the semiconductor substrate in the PFET areas; and
annealing the second metal to form the second silicide contacts in the NFET areas.
8. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate with a gate structure interposed between sourcedrain regions formed in a PFET area and a gate structure interposed between sourcedrain regions formed in an NFET area;
forming a first metal layer on the sourcedrain regions in the PFET area;
siliciding the first metal layer to form first silicide contacts on the sourcedrain regions in the PFET area;
depositing a second metal layer over the gate structure and sourcedrain regions in the NFET area; and
annealing the second metal layer to form second silicide contacts on the sourcedrain regions in the NFET area.
9. The method of claim 8 wherein a dielectric material overlies the semiconductor substrate, and wherein forming a first metal layer on the sourcedrain regions in the PFET area comprises:
etching the dielectric material to expose the gate structure and the sourcedrain regions in the PFET area and the gate structure and the sourcedrain regions in the NFET area; and
depositing the first metal layer over the gate structure and the sourcedrain regions in the PFET area and the gate structure and the sourcedrain regions in the NFET area.
10. The method of claim 9 wherein forming a first metal layer on the sourcedrain regions in the PFET area further comprises:
forming a mask over the gate structure and the sourcedrain regions in the PFET area; and
etching the first metal layer overlying the gate structure and the sourcedrain regions in the NFET area.
11. The method of claim 10 further comprising removing non-silicided portions of the first metal layer from the PFET area after siliciding the first metal layer to form the first silicide contacts.
12. The method of claim 8 wherein a dielectric material overlies the semiconductor substrate, and wherein forming a first metal layer on the sourcedrain regions in the PFET area comprises:
etching the dielectric material to expose the gate structure and the sourcedrain regions in the PFET area; and
depositing the first metal layer over the gate structure and the sourcedrain regions in the PFET area and over the dielectric material overlying the NFET area.
13. The method of claim 12 further comprising removing non-silicided portions of the first metal layer from the PFET area and the NFET area after siliciding the first metal layer to form first silicide contacts.
14. The method of claim 13 further comprising selectively etching, relative to the first silicide contacts, the dielectric material overlying the gate structure and the sourcedrain regions in the NFET area before depositing the second metal layer over the gate structure and sourcedrain regions in the NFET area.
15. The method of claim 13 further comprising:
forming a mask over the gate structure and the sourcedrain regions in the PFET area; and
etching the dielectric material overlying the gate structure and the sourcedrain regions in the NFET area before depositing the second metal layer over the gate structure and sourcedrain regions in the NFET area.
16. The method of claim 8 wherein depositing a second metal layer over the gate structure and sourcedrain regions in the NFET area comprises depositing the second metal layer over the gate structures and sourcedrain regions in the PFET area and NFET area.
17. The method of claim 8 wherein:
forming a first metal layer on the sourcedrain regions in the PFET area comprises depositing platinum on the sourcedrain regions in the PFET area; and
depositing a second metal layer over the gate structure and sourcedrain regions in the NFET area comprises depositing titanium and titanium nitride over the gate structure and sourcedrain regions in the NFET area.
18. The method of claim 8 further comprising:
depositing a metal fill material overlying the second metal layer in the PFET area and the second metal layer and second silicide contact in the NFET area; and
performing a planarization process to remove the second metal layer and the metal fill material overlying the gate structures and to define a contact structure over each sourcedrain region.
19. The method of claim 18 further comprising:
depositing a dielectric material overlying the contact structures and gate structures;
forming an electrical gate contact to a selected gate structure; and
forming an electrical sourcedrain contact to a selected contact structure.
20. An integrated circuit comprising:
a semiconductor substrate;
a PFET device overlying the semiconductor substrate and including a PFET gate structure interposed between PFET sourcedrain regions;
first contacts formed on the PFET sourcedrain regions and comprising a first metal silicide;
an NFET device overlying the semiconductor substrate and including an NFET gate structure interposed between NFET sourcedrain regions; and
second contacts formed on the NFET sourcedrain regions and comprising a second metal silicide different from the first metal silicide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
the large number of cathode lines define at least two different types of gaps x1, x2 (gap x1>gap x2) between the large number of cathode lines formed on the inner surface of the back substrate, and
distance holding members which define the distance between the back substrate and the front substrate are provided in at least some of the gaps x1.
2. A display device according, to claims 1, wherein a plurality of cathode lines are formed into each one group and the gap between the groups which are arranged close to each other is set larger than the gap between the cathode lines belonging to the same group.
3. A display device according to claims 2, wherein the cathode lines are extended in one direction in a zigzag pattern and the gap between the neighboring groups is displaced in the direction which crosses the extending direction of the cathode lines corresponding to the zigzag pattern of the cathode lines.
4. A display device according to claim 2, wherein 3N (N being a natural number) pieces of cathode lines are formed into one group.
5. A display device according to claim 2, wherein the gap between the cathode lines belonging to the same group is a gap x2 and the gap between the cathode lines belonging to the groups which are arranged close to each other is a gap x1.
6. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
a large number of plate-like control electrodes are formed such that the plate-like control electrodes are arranged close to the cathode lines, extend in another direction, are arranged in parallel in one direction, and have electron passing holes formed therein,
the large number of cathode lines define at least two different types of gaps x1, x2 (gap x1 >gap x2) between the large number of cathode lines formed on the inner surface of the back substrate, and
the plate-like control electrodes include first protrusions in at least some of the gaps x1, wherein the first protrusions approach closer to the back substrate than regions of the plate-like control electrodes where the electron passing holes are formed.
7. A display device according to claim 6, wherein the first protrusions are brought into contact with the back substrate.
8. A display device according to claim 6, wherein distance holding members which hold a distance between the back substrate and the front substrate to a given value are provided to front substrate sides of the first protrusions.
9. A display device according to claim 6, wherein the plate-like control electrodes includes second protrusions in at least some of the gaps x2, wherein the second protrusions approach closer to the back substrate than regions of the plate-like control electrodes where the electron passing holes are formed.
10. A display device according to claim 9, wherein the second protrusions have a length shorter than a length of the first protrusions as measured in an extending direction of the plate-like control electrode.
11. A display device according to claim 6, wherein a plurality of cathode lines are formed into each one group and the gap between the cathode lines belonging to the groups which are arranged close to each other is the gap x1.
12. A display device according to claim 11, wherein 3N (N being a natural number) pieces of cathode lines are formed into one group.
13. A display device according to claim 11, wherein the cathode lines are extended in one direction in a zigzag pattern and the gap between the neighboring groups is displaced in the direction which crosses the extending direction of the cathode lines corresponding to the zigzag pattern of the cathode lines.
14. A display device according to claim 6, wherein the plate-like control electrodes are metal plates.
15. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
a large number of plate-like control electrodes are formed such that the plate-like control electrodes are arranged close to the cathode lines, extend in another direction, are arranged in parallel in one direction, and have electron passing holes formed therein, and
the plate-like control electrode includes first protrusions in regions between the cathode lines, wherein the first protrusions approach closer to the back substrate than regions of the plate-like control electrodes where the electron passing holes are formed, and two or more cathode lines are arranged between at least some neighboring first protrusions.
16. A display device according to claim 15, wherein the first protrusions are brought into contact with the back substrate.
17. A display device according-to claim 15, wherein assuming the gap between the cathode lines in which the first protrusions of the plate-like control electrode are arranged as a gap x1 and the gap between the cathode lines in which the first protrusions of the plate-like control electrode are not arranged as a gap x2, a relationship the gap x1>the gap x2 is established.
18. A display device according to claim 15, wherein the plate-like control electrode includes second protrusions in at least some of regions formed between the cathode lines, wherein the second protrusions approach closer to the back substrate than regions where the electron passing holes are formed, and the second protrusions have a length shorter than a length of the first protrusion as measured in an extending direction of the plate-like control electrodes.
19. A display device according to claim 15, wherein the plate-like control electrodes are metal plates.
20. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
the gap between the cathode lines is comprised of at least two types consisting of a gap x1 and a gap x2 (the gap x1>the gap x2), and the gap between the phosphors formed on the front substrate is comprised of at least two types consisting of a gap x3 and a gap x4 (the gap x3>the gap x4) corresponding to the gaps between the cathode lines.
21. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and a large number of phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein the large number of phosphors are formed of a plurality of phosphors having different colors which are arranged in a given order, and at least one of a width of the cathode lines and a width of the phosphors is made different from each other between the phosphors having different colors in the plurality of phosphors.
22. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction and control electrodes having electron passing holes which are arranged above and in the vicinity of the cathode lines on an inner surface thereof and a front substrate having anodes and a large number of phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
the large number of phosphors are formed of phosphors in a plurality of colors which are arranged in a given order, and at least one of a width of the cathode lines, the number of electron passing holes formed in the control electrodes, a size of the electron passing holes and a width of the phosphors is made different from each other between the phosphors having different colors in the plurality of phosphors.
23. A display device in which a back substrate having a large number of cathode lines which extend in one direction and are arranged in parallel in another direction which crosses one direction formed on an inner surface thereof and a front substrate having anodes and a large number of phosphors formed on an inner surface thereof are arranged to face each other in an opposed manner with a given distance therebetween, wherein
every three cathode lines among a large number of cathode lines are formed into one group and a gap between the cathode lines in the neighboring groups is set wider than a gap between the cathode lines within the same group, and
the phosphors are arranged such that red, green and blue phosphors are formed into one group corresponding to the group of the cathode lines, wherein the green phosphor is arranged at the center of the group.