What is claimed is:
1. A semiconductor storage device comprising:
one contact which is connected to a primary bit-line;
five sub bit-lines which are connected to the primary bit-line through four bank selection transistors;
one contact which is connected to a virtual GND line; and
two sub bit-lines which are connected to the virtual GND line through two bank selection transistors,
wherein respective six sub bit-lines are arranged in parallel to signal inputted to six bank selection lines and are arranged in parallel to the primary bit lines, thus selecting memory cell transistor due to combination of level of two virtual grand lines arranged at right and left of the primary bit lines.
2. A semiconductor storage device as claimed in claim 1, wherein right and left of one sub bit-line with contact connected to the primary bit-line as center is segregated into upper part and lower part with respect to the contact connected to the primary bit-line, and right and left of one sub bit-line with contact connected to the virtual GND line as center is connected by above and below sub bit-line with respect to the contact connected to the virtual GND line.
3. A semiconductor storage device as claimed in claim 1, wherein the virtual GND line is connected to either a pre-charge circuit or GND through a row select transistor controlled by a row selection line and a virtual GND selection transistor controlled by virtual GND selection signal.
4. A semiconductor storage device as claimed in claim 2, wherein the virtual GND line is connected to either a pre-charge circuit or GND through a row select transistor controlled by a row selection line and a virtual GND selection transistor controlled by virtual GND selection signal.
5. A semiconductor storage device comprising:
one contact which is connected to a primary bit-line;
two sub bit-lines which are connected to the primary bit-line through two bank selection transistors;
one contact which is connected to a virtual GND line; and
five sub bit-lines which are connected to the virtual GND line through four bank selection transistors,
wherein respective six sub bit-lines are arranged in parallel to signal inputted to six bank selection lines and are arranged in parallel to the primary bit lines, thus selecting memory cell transistor due to combination of level of two virtual grand lines arranged at right and left of the primary bit lines.
6. A semiconductor storage device as claimed in claim 5, wherein right and left of one sub bit-line with contact connected to the primary bit-line as center is connected by above and below sub bit-line with respect to the contact connected to the primary bit-line, and right and left of one sub bit-line with contact connected to virtual GND line the as center is segregated into upper part and lower part with respect to the contact connected to the virtual GND line.
7. A semiconductor storage device as claimed in claim 5, wherein the virtual GND line is connected to either a pre-charge circuit or GND through a row select transistor controlled by a row selection line and a virtual GND selection transistor controlled by virtual GND selection signal.
8. A semiconductor storage device as claimed in claim 6, wherein the virtual GND line is connected to either a pre-charge circuit or GND through a row select transistor controlled by a row selection line and a virtual GND selection transistor controlled by virtual GND selection signal.
9. A semiconductor storage device in which there is provided one primary bit line and two virtual GND lines within one memory cell array, comprising:
a virtual GND contact for connecting electrically the memory cell array with the virtual GND line;
a bank selection transistor connected with the virtual GND contact; and
a bank row selection line for inputting signal to a gate electrode of the bank selection transistor,
wherein it causes any one of the plurality of memory cell array to be selected by controlling input of the signal.
10. A semiconductor storage device as claimed in claim 9, further comprising a bit-line contact for connecting electrically the primary bit-line with the memory cell array, wherein the one memory cell array is constituted with symmetry with respect to the center line having the bit-line contact, further, the respective two virtual GND lines have two the virtual GND contacts, furthermore, a virtual GND contact corresponding to the virtual GND contact is connected to the virtual GND contact in the memory cell array adjacent to the memory cell array.
11. A semiconductor storage device as claimed in claim 9, further comprising:
a sub bit-line which is connected with the bit line contact; and
total four bank selection transistors which are connected with both end parts of the sub bit-line in such a way that respective two transistors are connected in every both ends of the sub bit lines,
wherein respective gate electrodes of the four bank selection transistors are connected with respective separate bank row selection lines.
12. A semiconductor storage device as claimed in claim 10, further comprising:
a sub bit-line which is connected with the bit line contact; and
total four bank selection transistors which are connected with both end parts of the sub bit-line in such a way that respective two transistors are connected in every both ends of the sub bit lines,
wherein respective gate electrodes of the four bank selection transistors are connected with respective separate bank row selection lines.
13. A semiconductor storage device as claimed in claim 9, further comprising two bank selection transistors connected with the bit-line contact, wherein respective gate electrode of the two bank selection transistors are connected with respective separate bank row selection line.
14. A semiconductor storage device as claimed in claim 10, further comprising two bank selection transistors connected with the bit-line contact, wherein respective gate electrode of the two bank selection transistors are connected with respective separate bank row selection line.
15. A semiconductor storage device as claimed in claim 9, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
16. A semiconductor storage device as claimed in claim 10, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
17. A semiconductor storage device as claimed in claim 11, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
18. A semiconductor storage device as claimed in claim 12, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
19. A semiconductor storage device as claimed in claim 13, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
20. A semiconductor storage device as claimed in claim 14, further comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, an eighth, a ninth, and a tenth sub bit-lines in parallel to the primary bit lines; and
a plurality of stages of the memory cell transistor provided in between each of the first, the second, the third, the fourth, the fifth, sub bit-line and each of the sixth, the seventh, the eighth, the ninth, the tenth, sub bit-line,
wherein the first, the third, the fifth, the sixth, the eighth, and the tenth of the sub bit-lines are connected with respective separate the bank selection transistors.
21. A semiconductor storage device as claimed in claim 9, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
22. A semiconductor storage device as claimed in claim 10, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
23. A semiconductor storage device as claimed in claim 11, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
24. A semiconductor storage device as claimed in claim 12, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
25. A semiconductor storage device as claimed in claim 13, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
26. A semiconductor storage device as claimed in claim 14, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
27. A semiconductor storage device as claimed in claim 15, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
28. A semiconductor storage device as claimed in claim 16, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
29. A semiconductor storage device as claimed in claim 17, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
30. A semiconductor storage device as claimed in claim 18, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
31. A semiconductor storage device as claimed in claim 19, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
32. A semiconductor storage device as claimed in claim 20, wherein there is provided a plurality of stages of the memory cell transistor in between the first, the second, the third, the fourth, the fifth of the sub bit-lines and the sixth, the seventh, the eighth, the ninth, the tenth of sub bit-lines.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image processing device comprising:
an image correcting unit configured to correct a size of an image by inserting or deleting a predetermined number of pixels into and from the image based on size changing information of the image in which a plurality of pixel data is arranged, wherein
the image correcting unit includes:
a reading unit configured to read at least any one of attribute data corresponding to pixel of interest data in the image and the pixel data in a predetermined peripheral range including the pixel of interest;
a characteristic determining unit configured to determine a characteristic of the pixel of interest in the image from the data read by the reading unit;
a deforming process selecting unit configured to select a type of a deforming process related to determination of a position in which the predetermined number of pixels are inserted or deleted and determination of a pixel value of a pixel in a predetermined range from the inserted or deleted pixel based on a determination result of the characteristic determining unit from a plurality of types set in advance; and
a correction executing unit configured to execute the deforming process selected by the deforming process selecting unit.
2. The image processing device according to claim 1, wherein
the attribute data includes at least one of area information to classify a plurality of areas including an image area, a graph area, and a character area in the image and information related to an edge portion of a graph and a character, and
the characteristic determining unit determines a direction in which a line extends and a line width or a fine portion having a fine structure in the graph area and the character area based on continuity of the information related to the edge portion in the pixels in a predetermined adjacent range including the pixel of interest.
3. The image processing device according to claim 1, wherein
the characteristic determining unit performs area determination to classify into any one of a plurality of areas including an image area, a graph area, and a character area and determines a direction in which a line extends and a line width or a fine portion having a fine structure in the determined graph area and character area based on presence of continuity of pixel values of the pixels in a predetermined adjacent range including the pixel of interest of the image and an arranging direction and a width of the pixels having the continuity by using data of the image on which a screen process is not yet performed when the read data is the pixel data.
4. The image processing device according to claim 1, wherein
the deforming process selecting unit selects any one of:
a neighborhood pixel moving process to copy the pixel value of any one of adjacent pixels to insert or to delete the pixel data in each position on a predetermined line perpendicular to a deforming direction;
a neighborhood pixel averaging process to insert a predetermined weighted average value of pixel values of a plurality of adjacent pixels in each position on the predetermined line perpendicular to the deforming direction or to delete the pixel being a deletion target in the predetermined position and change the pixel values of a plurality of pixels adjacent to the pixel being the deletion target to predetermined weighted average values including the pixel being the deletion target;
a dispersed neighborhood pixel moving process to copy any one of the adjacent pixel values to insert or to delete the pixel data in each of positions different for each pixel column in which a plurality of pixels is arranged in the deforming direction; and
a dispersed neighborhood pixel averaging process to insert the predetermined weighted average value of the pixel values of the adjacent pixels in each of the positions different for each pixel column in which a plurality of pixels is arranged in the deforming direction to distribute an effect of the insertion to predetermined peripheral pixels of the inserted pixel or to delete the pixel data and distribute an effect of the deletion to predetermined peripheral pixels of the deleted pixel.
5. The image processing device according to claim 4, comprising:
a dispersed position table outputting unit capable of outputting a dispersed position determining table determining an insertion position or a deletion position of the pixel data in each of the pixel columns in which a plurality of pixels is arranged in the deforming direction based on a plurality of different methods when the deforming process selecting unit selects the dispersed neighborhood pixel moving process or the dispersed neighborhood pixel averaging process,
wherein, the deforming process selecting unit selects one dispersed position determining table to be output from the dispersed position table outputting unit according to the characteristic determined by the characteristic determining unit when selecting the dispersed neighborhood pixel moving process or the dispersed neighborhood pixel averaging process.
6. The image processing device according to claim 1, comprising:
an operation unit configured to receive an operation by a user, wherein
the deforming process selecting unit selects the deforming process related to a selection instruction when an input related to the selection instruction of the deforming process is performed to the operation unit.
7. The image processing device according to claim 1, wherein
the correction executing unit separately performs deforming processes in two directions orthogonal to each other in order, and
the deforming process selecting unit selects the deforming process related to deformation in one direction and selects the deforming process related to the deformation in the other direction based on a common characteristic initially determined by the characteristic determining unit.
8. The image processing device according to claim 1, comprising:
a screen process executing unit configured to perform a screen process by using a predetermined threshold matrix on data of the image, wherein
the correction executing unit includes
a correction content setting unit configured to set a process content of the deforming process based on the size changing information, the determined characteristic of each pixel, and the selected type of the deforming process, and
a correction content executing unit configured to execute the process content set by the correction content setting unit on the data of the image,
the screen process executing unit generates an inverse process matrix obtained by performing a process opposite to the deforming process of each pixel set by the correction content setting unit on each element of the threshold matrix and executes the screen process by using the inverse process matrix on the data of the image, and
the correction content executing unit performs the deforming process on the data of the image on which the screen process by the screen process executing unit is already performed.
9. The image processing device according to claim 1, comprising:
a character edge correcting unit configured to perform predetermined correction on the pixel value in the vicinity of an edge portion of a character based on information related to the edge portion of the character, wherein
the image correcting unit performs the deforming process on data of the image which is already corrected by the character edge correcting unit.
10. The image processing device according to claim 1, comprising:
a character edge correcting unit configured to perform predetermined correction on the pixel value in the vicinity of an edge portion of a character based on information related to the edge portion of the character, wherein
the image correcting unit performs the deforming process on data of the image before the correction by the character edge correcting unit is performed, and
the character edge correcting unit uses information related to deformation of the edge portion of the character by the deforming process in the correction.
11. A non-transitory recording medium storing a computer readable program for causing a computer
to serve as an image correcting unit configured to correct a size of an image by inserting or deleting a predetermined number of pixels into and from the image based on size changing information of the image in which a plurality of pixel data is arranged, wherein
the image correcting unit includes:
a reading unit configured to read at least any one of attribute data corresponding to pixel of interest data in the image and the pixel data in a predetermined peripheral range including the pixel of interest;
a characteristic determining unit configured to determine a characteristic of the pixel of interest in the image from the data read by the reading unit;
a deforming process selecting unit configured to select a type of a deforming process related to determination of a position in which the predetermined number of pixels are inserted or deleted and determination of a pixel value of a pixel in a predetermined range from the inserted or deleted pixel based on a determination result of the characteristic determining unit from a plurality of types set in advance; and
a correction executing unit configured to execute the deforming process selected by the deforming process selecting unit.
12. The non-transitory recording medium storing a computer readable program according to claim 11, wherein
the attribute data includes at least one of area information to classify a plurality of areas including an image area, a graph area, and a character area in the image and information related to an edge portion of a graph and a character, and
the characteristic determining unit determines a direction in which a line extends and a line width or a fine portion having a fine structure in the graph area and the character area based on continuity of the information related to the edge portion in the pixels in a predetermined adjacent range including the pixel of interest.
13. The non-transitory recording medium storing a computer readable program according to claim 11, wherein
the characteristic determining unit performs area determination to classify into any one of a plurality of areas including an image area, a graph area, and a character area and determines a direction in which a line extends and a line width or a fine portion having a fine structure in the determined graph area and character area based on presence of continuity of pixel values of the pixels in a predetermined adjacent range including the pixel of interest of the image and an arranging direction and a width of the pixels having the continuity by using data of the image on which a screen process is not yet performed when the read data is the pixel data.
14. The non-transitory recording medium storing a computer readable program according to claim 11, wherein
the deforming process selecting unit selects any one of:
a neighborhood pixel moving process to copy the pixel value of any one of adjacent pixels to insert or to delete the pixel data in each position on a predetermined line perpendicular to a deforming direction;
a neighborhood pixel averaging process to insert a predetermined weighted average value of pixel values of a plurality of adjacent pixels in each position on the predetermined line perpendicular to the deforming direction or to delete the pixel being a deletion target in the predetermined position and change the pixel values of a plurality of pixels adjacent to the pixel being the deletion target to predetermined weighted average values including the pixel being the deletion target;
a dispersed neighborhood pixel moving process to copy any one of the adjacent pixel values to insert or to delete the pixel data in each of positions different for each pixel column in which a plurality of pixels is arranged in the deforming direction; and
a dispersed neighborhood pixel averaging process to insert the predetermined weighted average value of the pixel values of the adjacent pixels in each of the positions different for each pixel column in which a plurality of pixels is arranged in the deforming direction to distribute an effect of the insertion to predetermined peripheral pixels of the inserted pixel or to delete the pixel data and distribute an effect of the deletion to predetermined peripheral pixels of the deleted pixel.
15. The non-transitory recording medium storing a computer readable program according to claim 14, comprising:
a dispersed position table outputting unit capable of outputting a dispersed position determining table determining an insertion position or a deletion position of the pixel data in each of the pixel columns in which a plurality of pixels is arranged in the deforming direction based on a plurality of different methods when the deforming process selecting unit selects the dispersed neighborhood pixel moving process or the dispersed neighborhood pixel averaging process, wherein
the deforming process selecting unit selects one dispersed position determining table to be output from the dispersed position table outputting unit according to the characteristic determined by the characteristic determining unit when selecting the dispersed neighborhood pixel moving process or the dispersed neighborhood pixel averaging process.
16. The non-transitory recording medium storing a computer readable program according to claim 11, wherein
the computer is capable of receiving an operation by a user through an operation unit, and
the deforming process selecting unit selects the deforming process related to a selection instruction when an input related to the selection instruction of the deforming process is performed to the operation unit.
17. The non-transitory recording medium storing a computer readable program according to claim 11, wherein
the correction executing unit separately performs deforming processes in two directions orthogonal to each other in order, and
the deforming process selecting unit selects the deforming process related to deformation in one direction and selects the deforming process related to the deformation in the other direction based on a common characteristic initially determined by the characteristic determining unit.
18. The non-transitory recording medium storing a computer readable program according to claim 11,
the program for causing the computer to further serve as a screen process executing unit configured to perform a screen process by using a predetermined threshold matrix on data of the image, wherein
the correction executing unit includes
a correction content setting unit configured to set a process content of the deforming process based on the size changing information, the determined characteristic of each pixel, and the selected type of the deforming process, and
a correction content executing unit configured to execute the process content set by the correction content setting unit on the data of the image,
the screen process executing unit generates an inverse process matrix obtained by performing a process opposite to the deforming process of each pixel set by the correction content setting unit on each element of the threshold matrix and executes the screen process by using the inverse process matrix on the data of the image, and
the correction content executing unit performs the deforming process on the data of the image on which the screen process by the screen process executing unit is already performed.
19. The non-transitory recording medium storing a computer readable program according to claim 11,
the program for causing the computer to further serve as a character edge correcting unit configured to perform predetermined correction on the pixel value in the vicinity of an edge portion of a character based on information related to the edge portion of the character, wherein
the image correcting unit performs the deforming process on data of the image which is already corrected by the character edge correcting unit.
20. The non-transitory recording medium storing a computer readable program according to claim 11,
the program for causing a computer to further serve as a character edge correcting unit configured to perform predetermined correction on the pixel value in the vicinity of an edge portion of a character based on information related to the edge portion of the character, wherein
the image correcting unit performs the deforming process on data of the image before the correction by the character edge correcting unit is performed, and
the character edge correcting unit uses information related to deformation of the edge portion of the character by the deforming process in the correction.
21. An image correcting method configured to correct a size of an image by inserting or deleting a predetermined number of pixels into and from the image based on size changing information of the image in which a plurality of pixel data is arranged comprising:
a reading step of reading at least any one of attribute data corresponding to pixel of interest data in the image and pixel data in a predetermined peripheral range including the pixel of interest;
a character determining step of determining a characteristic of the pixel of interest in the image from the data read by the step of reading;
a deforming process selecting step of selecting a type of a deforming process related to determination of a position in which the predetermined number of pixels are inserted or deleted and determination of a pixel value of a pixel in a predetermined range from the inserted or deleted pixel based on a determination result in the step of determining a characteristic from a plurality of types set in advance; and
a correction executing step of executing the deforming process selected at the deforming process selecting step.