Author: claimsbot

1. A memory element comprising:
a magnetoresistance element comprising a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer having a variable magnetization direction, a third ferromagnetic layer having a variable magnetization direction, a first non-magnetic layer located between the first ferromagnetic layer and the second ferromagnetic layer, and a second non-magnetic layer located between the second ferromagnetic layer and the third ferromagnetic layer; and
means for applying a current in a film thickness direction of the magnetoresistance element,
wherein
a magnetization direction of the second ferromagnetic layer and a magnetization direction of the third ferromagnetic layer are substantially anti-parallel with each other, and
in conducting a write operation, currents which differ in current pulse width are applied in a film thickness direction of the magnetoresistance element to cause a spin-transfer torque to act on either the second ferromagnetic layer or the third ferromagnetic layer and cause magnetization reversal therein.
2. The memory element according to claim 1, wherein the second ferromagnetic layer and the third ferromagnetic layer are in anti-parallel coupling with each other via the second non-magnetic layer.
3. The memory element according to claim 2, wherein, at the time of the write operation,
when reversing the magnetization direction of the third ferromagnetic layer with a spin-transfer torque, a current having a first pulse width is applied in a direction oriented from the third ferromagnetic layer to the first ferromagnetic layer, and
when reversing the magnetization direction of the second ferromagnetic layer with a spin-transfer torque, a current having a second pulse width is applied in the direction oriented from the third ferromagnetic layer to the first ferromagnetic layer.
4. The memory element according to claim 3, wherein,
when currents which differ in pulse width are applied in the direction oriented from the third ferromagnetic layer to the first ferromagnetic layer at the time of the write operation,
spin electrons which are substantially parallel with the magnetization direction of the first ferromagnetic layer are conducted to the second ferromagnetic layer, the second non-magnetic layer and the third ferromagnetic layer via the first ferromagnetic layer and the first non-magnetic layer.
5. The memory element according to claim 2, wherein, at the time of the write operation,
when reversing the magnetization direction of the second ferromagnetic layer with a spin-transfer torque, a current having a first pulse width is applied in a direction oriented from the first ferromagnetic layer to the third ferromagnetic layer, and
when reversing the magnetization direction of the third ferromagnetic layer with a spin-transfer torque, a current having a second pulse width is applied in the direction oriented from the first ferromagnetic layer to the third ferromagnetic layer.
6. The memory element according to claim 5, wherein
when currents which differ in pulse width are applied in the direction oriented from the first ferromagnetic layer to the third ferromagnetic layer at the time of the write operation,
conduction electrons are conducted in a direction oriented from the third ferromagnetic layer to the first ferromagnetic layer, and
spin electrons which are substantially anti-parallel with the magnetization direction of the first ferromagnetic layer are reflected at the first ferromagnetic layer and conducted to the second ferromagnetic layer, the second non-magnetic layer and the third ferromagnetic layer.
7. The memory element according to claim 2, wherein
the current having the first pulse width is based on a precession motion period of the third ferromagnetic layer, and
the current having the second pulse width is based on a precession motion period of the second ferromagnetic layer.
8. The memory element according to claim 2, wherein
the current having the first pulse width is based on an integer times a precession motion period of the third ferromagnetic layer, and
the current having the second pulse width is based on an integer times a precession motion period of the second ferromagnetic layer.
9. The memory element according to claim 2, wherein
the current having the first pulse width is based on a film thickness of the third ferromagnetic layer, and
the current having the second pulse width is based on a film thickness of the second ferromagnetic layer.
10. The memory element according to claim 3, wherein
if the magnetization direction of the first ferromagnetic layer and the magnetization direction of the second ferromagnetic layer are parallel with each other, then a spin-transfer torque acts on the third ferromagnetic layer, and
if the magnetization direction of the first ferromagnetic layer and the magnetization direction of the second ferromagnetic layer are anti-parallel with each other, then a spin-transfer torque acts on the second ferromagnetic layer and reverses the magnetization.
11. The memory element according to claim 1, wherein at the time of a read operation, a current which is smaller than a current applied at the time of the write operation is applied.
12. The memory element according to claim 2, wherein
the magnetoresistance element further comprises a third non-magnetic layer formed on a face of the first ferromagnetic layer opposite from the first non-magnetic layer, a first anti-ferromagnetic layer, and a fourth ferromagnetic layer formed between the third non-magnetic layer and the first anti-ferromagnetic layer,
a magnetization direction of the fourth ferromagnetic layer is fixed by the first anti-ferromagnetic layer, and
the first ferromagnetic layer and the fourth ferromagnetic layer are in anti-parallel coupling with each other via the third non-magnetic layer.
13. The memory element according to claim 1, wherein the first non-magnetic layer is an insulation tunnel barrier layer.
14. The memory element according to claim 1, wherein the current which differs in current pulse width at the time of the write operation is applied as a single pulse.
15. The memory element according to claim 1, wherein the current which differs in current pulse width at the time of the write operation is applied as consecutive pulses.
16. The memory element according to claim 15, wherein each of the pulse width and inter-pulse space at the time of the write operation is equal to an integer times a precession motion period of each of the second ferromagnetic layer and the third ferromagnetic layer.
17. A memory comprising:
a plurality of first wiring lines disposed substantially in parallel;
a plurality of second wiring lines disposed so as to intersect the first wiring lines and be substantially in parallel with each other;
a plurality of magnetoresistance elements disposed at intersections of the first wiring lines and the second wiring lines; and
switching elements disposed respectively between the magnetoresistance elements and the first wiring lines,
wherein
each of the magnetoresistance elements comprises a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer having a variable magnetization direction, a third ferromagnetic layer having a variable magnetization direction, a first non-magnetic layer located between the first ferromagnetic layer and the second ferromagnetic layer, and a second non-magnetic layer located between the second ferromagnetic layer and the third ferromagnetic layer, and a magnetization direction of the second ferromagnetic layer and a magnetization direction of the third ferromagnetic layer are substantially anti-parallel with each other, and
the third ferromagnetic layer is electrically connected to an associated one of the second wiring lines and the first ferromagnetic layer is electrically connected to an associated one of the first wiring lines via an associated one of the switching elements,
when conducting a write operation, currents which differ in current pulse width are applied in a film thickness direction of the magnetoresistance element to cause a spin-transfer torque to act on either the second ferromagnetic layer or the third ferromagnetic layer and cause magnetization reversal therein.
18. The memory according to claim 17, wherein the second ferromagnetic layer and the third ferromagnetic layer are in anti-parallel coupling with each other via the second non-magnetic layer.
19. The memory according to claim 17, wherein each of the switching elements is a diode.
20. A write operation method for recording information in a magnetic memory element by using a spin-transfer torque, wherein
the magnetic memory element comprises a magnetoresistance element, and means for applying a current in a film thickness direction of the magnetoresistance element,
the magnetoresistance element comprises a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer having a variable magnetization direction, a third ferromagnetic layer having a variable magnetization direction, a first non-magnetic layer located between the first ferromagnetic layer and the second ferromagnetic layer, and a second non-magnetic layer located between the second ferromagnetic layer and the third ferromagnetic layer, and a magnetization direction of the second ferromagnetic layer and a magnetization direction of the third ferromagnetic layer are substantially anti-parallel with each other, and
currents which differ in current pulse width are applied in a film thickness direction of the magnetoresistance element to cause a spin-transfer torque to act on either the second ferromagnetic layer or the third ferromagnetic layer and cause magnetization reversal therein.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A charge control circuit used in a computer, comprising:
a backup power supply;
a USB connector electronically connected to a universal serial bus (USB) device;
a charge control unit powered by the backup power supply and comprising a charge controller;
a switch unit comprising an electronic switch electronically connected to the charge controller and the backup power supply; and
a southbridge chip comprising a USB controller, the southbridge chip selectively controlling the charge controller or the USB controller to transmit enumeration signals to the USB connector to recognize and activate the USB device to be charged according to a working mode of the computer, and switching the electronic switch to connect or disconnect the power supply to the USB connector according to the working mode of the computer.
2. The charge control circuit of claim 1, wherein the southbridge chip comprises a first control pin, the switch unit further comprises a first diode, and a level shift unit electronically connected to the first control pin of the southbridge chip, an anode of the first diode is electronically connected to the output terminal of the level shift unit, and an cathode of the first diode is electronically connected to the electronic switch, the level shift unit transforms a high level voltage at a first amplitude output from the southbridge chip to a high level voltage at a second amplitude, the high level voltage at the second amplitude is output to the electronic switch via the first diode to switch off the electronic switch.
3. The charge control circuit of claim 2, where in the level shift unit comprises a first NPN type bipolar junction transistor (BJT), a second NPN type BJT, and a current limiting resistor, a base of the first NPN type BJT is electronically connected to a control pin of the southbridge chip via the current limiting resistor; an emitter of the first NPN type BJT is grounded; and a connector of the first NPN type BJT is electronically connected to the backup power supply; a base of the second NPN type BJT is electronically connected to the connector of the first NPN type BJT; an emitter of the second NPN type BJT is grounded; and a connector of the second NPN type BJT is electronically connected to the backup power supply; the anode of the first diode is electronically connected to a node between the collector of the second NPN type BJT and the backup power supply.
4. The charge control circuit of claim 2, wherein the electronic switch is a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET), the switch unit further comprises a pull-down resistor, a gate of the P-channel MOSFET is electronically connected to the cathodes of the first diode, a source of the P-channel MOSFET is electronically connected to the backup power supply, and a drain of the P-channel MOSFET is electronically connected to a power pin of the USB connector, the drain of the P-channel MOSFET is further grounded via the pull-down resistor.
5. The charge control circuit of claim 4, wherein the charge controller comprises a first input pin and two pairs of differential pins, the USB controller comprises a pair of differential pins correspondingly connected to one pair of differential pins of the charge controller, the other pair of differential pins of the charge controller are correspondingly connected to differential pins of the USB connector, the southbridge chip further comprises a first control pin electronically connected to the first input pin of the charge controller.
6. The charge control circuit of claim 5, wherein when the computer is in a normal mode, the southbridge chip outputs a high level voltage signal to the first input pin of the charge controller via the first control pin, the charge controller connects the USB controller to the USB connector, the USB controller transmits enumeration signals to the USB device via the charge controller and the USB connector; when the computer is in a sleep or standby mode, the southbridge chip outputs a low level signal to the first input pin of the charge controller via the first control pin, the charge controller generates and transmits enumeration signals to the USB device.
7. The charge control circuit of claim 6, wherein when the computer is in a sleep or standby mode, the first control pin is at high impedance.
8. The charge control circuit of claim 7, wherein the charge controller further comprises an output pin, when the first input pin observes a logic change, the output pin INT is high for a predetermined time, otherwise the output pin INT is high impedance.
9. The charge control circuit of claim 2, where the electronic switch is a PNP type BJT, the switch unit further comprises a pull-down resistor, a base of the P-channel MOSFET is electronically connected to the cathodes of the first diode, an emitter of the P-channel MOSFET is electronically connected to the backup power supply, an a collector of the P-channel MOSFET is electronically connected to a power pin of the USB connector, the drain of the P-channel MOSFET is further grounded via the pull-down resistor.
10. The charge control circuit of claim 1, wherein the charge control unit further comprises a fuse electronically connected between the electronic switch and a power pin of the USB controller.

1. A method for forming a post hole in the ground, comprising:
positioning a post hole digger over a post installation site on the ground, the post hole digger comprising a pair of shaft portions each comprising a handle slidably coupled to a base, wherein the post hole digger further comprises a pair of blades each coupled to the base of a respective one of the shaft portions;
independently sliding the handles along the bases from a raised position downwardly toward the ground into a lowered position to impact an impact plate of the post hole digger in force transmitting communication with the blades to drive the blades into the ground;
independently sliding the handles along the bases upwardly from the lowered position into the raised position; and
temporarily locking each handle in place relative to a respective base, wherein temporarily locking each handle in place relative to the respective base consists of independently rotating each handle relative to the respective base and independently lifting each handle relative to the respective base.
2. The method of claim 1, wherein:
independently sliding the handles along the bases from the raised position downwardly toward the ground into the lowered position and independently sliding the handles along the bases upwardly from the lowered position into the raised position comprises guiding respective pins of the handles along respective alignment slots formed in the bases; and
rotating the handles relative to the respective bases to temporarily lock the handles in place comprises guiding the respective pins of the handles along respective U-shaped portions of the alignment slots.
3. The method of claim 2, further comprising retracting the pins out of the alignment slots, rotating the handles relative to the bases, and extending the pins into engagement with respective apertures formed in the bases to more permanently lock the handles in place.
4. A hand tool, comprising:
a base comprising a first impact surface and a slot, the slot comprising two parallel tracks coupled together by an intermediate track extending substantially perpendicular to the two parallel tracks;
a handle slidably coupled to the base, the handle comprising a second impact surface, the handle being slidable relative to the base such that the second impact surface of the handle impacts the first impact surface of the base, wherein the handle further comprises a pin engageable with the slot of the base, the pin being movably retained by the slot as the handle slides relative to the base; and
a tool attachment coupled to the base.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An antenna structure comprising a ground plane, one and only one planar feed element, one and only one planar parasitic element (230), one and only one feed conductor (203) and one and only one short-circuit conductor, the feed conductor being coupled to the feed element (240) and the short-circuit conductor being connected to the parasitic element, which, being larger in surface area than the planar feed element, is a main radiating element, and said feed element, which is not connected to the short-circuit conductor, being electromagnetically coupled to said parasitic element.
2. A structure according to claim 1, characterized in that said feed element is arranged to resonate at substantially the same frequency as said parasitic element.
3. A structure according to claim 1, characterized in that said parasitic element (230) and said feed element (240) are separate conductive regions on a surface of a dielectric plate (208).
4. A structure according to claim 1, characterized in that said parasitic element (330) and said feed element (340) are separate self-supporting conductive bodies.
5. A structure according to claim 1, characterized in that said parasitic element viewed from said short-circuit point (S), is divided into two branches having certain resonance frequencies.
6. A radio apparatus (MS) comprising an antenna (700) having a ground plane, one and only one planar feed element, one and only one planar parasitic element, one and only one feed conductor and one and only one short-circuit conductor, the feed conductor being coupled to the feed element and the short-circuit conductor being connected to the parasitic element, which, being larger in surface area than the planar feed element, is a main radiating element, and said feed element, which is not connected to the short circuit conductor, being electromagnetically coupled to said parasitic element, which parasitic element is short-circuited at a single point to the ground plane.
7. An antenna structure comprising a ground plane, planar feed element and a planar parasitic element, characterized in that said feed element (240) is coupled to a feed conductor (203) of the antenna structure and electromagnetically coupled to said parasitic element (230) which is short-circuited at a single point (S) to the ground plane, wherein the antenna structure additionally comprises a whip element which, when pulled out, is in galvanic contact with said feed element.