Author: claimsbot

1. A chain lateral travel limiter for a bicycle having a frame and a chain drive assembly connected to the frame, the chain lateral travel limiter comprising a body including a head, the head adapted for attachment to the frame, the body including a chain return finger attached to and extending from the head, the chain return finger including an arcuate face.
2. The chain lateral travel limiter of claim 1 further comprising a neck connected at first end to the head and at a second end to the chain return finger.
3. The chain lateral travel limiter of claim 1 wherein the arcuate face further comprises a continuously curving face.
4. The chain lateral travel limiter of claim 1 wherein the chain return finger further comprises a tapered leading edge.
5. The chain lateral travel limiter of claim 1 wherein the head further comprises a mounting aperture adapted for receiving a mounting screw for attachment to the frame.
6. The chain lateral travel limiter of claim 1 wherein the head further comprises an elongated mounting aperture, the elongated mounting aperture having a primary axis lying oblique to an axis of the body, the elongated mounting aperture adapted for receiving a mounting screw for attachment to the frame.
7. The chain lateral travel limiter of claim 1 further comprising a tube clamp connected to the head, the tube clamp adapted for attachment to the frame.
8. A chain lateral travel limiter for a bicycle having a frame and a chain drive assembly connected to the frame, the chain lateral travel limiter comprising:
a body including a head, the head adapted for attachment to the frame;
a neck connected at a first end to the head;
a chain return finger the body attached to and depending from the neck, the chain return finger including an arcuate face.
9. The chain lateral travel limiter of claim 8 wherein the arcuate face further comprises a continuously curving face.
10. The chain lateral travel limiter of claim 8 wherein the chain return finger further comprises a tapered leading edge.
11. The chain lateral travel limiter of claim 8 wherein the head further comprises a mounting aperture adapted for receiving a mounting screw for attachment to the frame.
12. The chain lateral travel limiter of claim 8 wherein the head further comprises an elongated mounting aperture, the elongated mounting aperture having a primary axis lying oblique to an axis of the body, the elongated mounting aperture adapted for receiving a mounting screw for attachment to the frame.
13. The chain lateral travel limiter of claim 8 further comprising a tube clamp connected to the head, the tube clamp adapted for attachment to the frame.
14. A chain drive assembly for a bicycle for a bicycle having a frame, the chain drive assembly comprising:
a rear sprocket mounted to the frame;
at least two front chain rings mounted to the frame;
a chain mounted for rotational movement with the rear sprocket and at least one of the at least two front chain rings;
a front d\xe9railleur assembly mounted to the frame the front d\xe9railleur adapted to selectively shift the chain laterally from an outer chain ring of the at least two front chain rings to an inner chain ring of the at least two front chain rings;
a chain lateral travel limiter including a body having a head, the head adapted for attachment to the frame, the body including a chain return finger attached to and extending from the head, the chain return finger including an arcuate face, the chain lateral travel limiter positioned proximate to the inner chain ring of the at least two front chain rings, so that during a shifting event wherein the front derailleur assembly operates to shift the chain laterally from the outer of the at least two front chain rings to the inner of the at least two front chain rings, and in the event that the front derailleur shifts the chain laterally from a first plane defined by the outer chain ring to second plane defined by the inner chain ring and the chain travels laterally beyond the second plane defined by the inner chain ring, the chain is caught against the chain lateral travel limiter and guided in a manner that redirects the chain to the second plane defined by the inner chain ring to engage the inner chain ring.
15. The chain lateral travel limiter of claim 14 further comprising a neck connected at first end to the head and at a second end to the chain return finger.
16. The chain lateral travel limiter of claim 14 wherein an outer chain ring of the at least two front chain rings includes a diameter and an inner chain ring of the at least two front chain rings includes a diameter smaller than the diameter of the outer chain ring.
17. The chain lateral travel limiter of claim 14 wherein the chain return finger further comprises a tapered leading edge.
18. The chain lateral travel limiter of claim 14 wherein the head further comprises a mounting aperture adapted for receiving a mounting screw for attachment to the frame.
19. The chain lateral travel limiter of claim 14 wherein the head further comprises a elongated mounting aperture, the elongated mounting aperture having a primary axis lying oblique to an axis of the body, the elongated mounting aperture adapted for receiving a mounting screw for attachment to the frame.
20. The chain lateral travel limiter of claim 14 further comprising a tube clamp connected to the head, the tube clamp adapted for attachment to the frame.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A smart meter evaluation device that receives a signal according to a predetermined communication protocol in a wireless ad-hoc network including a plurality of smart meters that measure the amount of consumption and acquire meter value data, and evaluates a communication state of the plurality of smart meters, comprising:
a receiving unit for receiving a radio-frequency signal and converting the radio-frequency signal into a baseband signal;
a demodulating unit for converting the baseband signal into digital data and outputting the digital data as demodulated data;
a signal type specifying unit for specifying the signal type of the demodulated data on the basis of header information included in the demodulated data;
a communication information acquiring unit for acquiring communication information which is included in the demodulated data and includes at least the meter value data;
a signal waveform acquiring unit for acquiring the waveform of the baseband signal;
a display unit for displaying the signal type, the communication information, and the signal waveform;
a determining unit for detecting whether the signals from the plurality of smart meters collide with each other in one smart meter on the basis of a signal level of the baseband signal.
2. The smart meter evaluation device according to claim 1, further comprising:
a smart meter management unit for specifying the smart meter, which is a transmission source of the demodulated data; and
a signal level measuring unit for measuring the signal level of the baseband signal,
wherein the smart meter management unit specifies the smart meter, which is the transmission source of the demodulated data, on the basis of the signal level.
3. A smart meter evaluation method that receives a signal according to a predetermined communication protocol in a wireless ad-hoc network including a plurality of smart meters that measure the amount of consumption and acquire meter value data and evaluates a communication state of the plurality of smart meters, comprising:
a receiving step of receiving a radio-frequency signal and converting the radio-frequency signal into a baseband signal;
a demodulating step of converting the baseband signal into digital data and outputting the digital data as demodulated data;
a signal type specifying step of specifying the signal type of the demodulated data on the basis of header information included in the demodulated data;
a communication information acquiring step of acquiring communication information which is included in the demodulated data and includes at least the meter value data;
a signal waveform acquiring step of acquiring the waveform of the baseband signal; and
a display step of displaying the signal type, the communication information, and the signal waveform;
a signal collision detecting step of detecting whether the signals from the plurality of smart meters collide with each other in one smart meter on the basis of a signal level of the baseband signal.
4. The smart meter evaluation method according to claim 3, further comprising:
a smart meter specifying step of specifying the smart meter, which is a transmission source of the demodulated data; and
a signal level measuring step of measuring the signal level of the baseband signal,
wherein the smart meter specifying step specifies the smart meter, which is the transmission source of the demodulated data, on the basis of the signal level.

1. An integrated circuit comprising:
a single silicon die, the single silicon die comprising:
a first processing unit, the first processing unit comprising
a first microprocessor and
a memory; and

a first secure processing unit, communicatively coupled to the first processing unit, the first secure processing unit comprising:
a second microprocessor,
a first bus interface unit, the first bus interface unit being operable to restrict access to at least some components of the first secure processing unit by the first processing unit,
random-access memory,
non-volatile memory,
a power failure sensing circuit, wherein the power failure sensing circuit is operable to render the non-volatile memory within the first secure processing unit resistant to tampering when a power failure is sensed, and
a direct memory access controller.
2. The integrated circuit of claim 1, in which the first processing unit comprises a second secure processing unit, the second secure processing unit comprising a second bus interface unit, the second bus interface unit being operable to restrict access to at least some components of the second secure processing unit by the first secure processing unit.
3. The integrated circuit of claim 1, in which the at least some components of the first secure processing unit include secret information stored in the non-volatile memory of the first secure processing unit.
4. The integrated circuit of claim 3, in which the secret information comprises at least one cryptographic key.
5. The integrated circuit of claim 1, in which the at least some components of the first secure processing unit include secret information stored in the random-access memory of the first secure processing unit.
6. The integrated circuit of claim 1, in which the first processing unit is a device microcontroller.
7. The integrated circuit of claim 1, in which the first processing unit is a communications microcontroller.
8. The integrated circuit of claim 1, in which the integrated circuit comprises a network communications chip.
9. The integrated circuit of claim 1, in which the first secure processing unit is operable to execute software for controlling usage of content objects according to one or more usage rules associated with the content objects.
10. The integrated circuit of claim 9, in which the software for controlling usage of content objects is stored, at least in part, in the non-volatile memory of the first secure processing unit.
11. The integrated circuit of claim 9, in which at least some of the usage rules associated with the content objects are stored in the non-volatile memory of the first secure processing unit.
12. The integrated circuit of claim 1, in which the first secure processing unit further comprises a clock.
13. The integrated circuit of claim 12, in which the first secure processing unit further comprises a battery, the battery being operable to supply power to the clock.
14. The integrated circuit of claim 1, in which the first secure processing unit further comprises a memory management unit.
15. The integrated circuit of claim 14, in which the memory management unit is operable to prevent a less trusted task executing on the first processing unit or the first secure processing unit from modifying a more trusted task executing on the first secure processing unit.
16. The integrated circuit of claim 14, in which the memory management unit is operable to page information into and out of first secure processing unit.
17. The integrated circuit of claim 16, in which the information paged into and out of the first secure processing unit comprises virtual memory pages.
18. The integrated circuit of claim 1, in which the first secure processing unit is operable to encrypt at least some code or other information before storing it in memory external to the first secure processing unit.
19. The integrated circuit of claim 18, in which the first secure processing unit is operable to decrypt at least some code or other information loaded from memory external to the first secure processing unit.
20. The integrated circuit of claim 1, in which the first secure processing unit is operable to cryptographically seal at least some code or other information before storing it in memory external to the first secure processing unit.
21. The integrated circuit of claim 20, in which the first secure processing unit is operable to verify a cryptographic seal associated with information loaded from memory external to the first secure processing unit.
22. The integrated circuit of claim 1, in which the nonvolatile memory comprises read-only memory.
23. The integrated circuit of claim 1, in which the non-volatile memory comprises non-volatile random-access memory.
24. The integrated circuit of claim 1, in which the non-volatile memory comprises electrically erasable programmable read only memory (EEPROM).
25. The integrated circuit of claim 1, in which the non-volatile memory comprises flash memory.
26. The integrated circuit of claim 1, in which the non-volatile memory stores kernel programs used to control the first secure processing unit.
27. The integrated circuit of claim 1, in which the non-volatile memory stores one or more load modules.
28. The integrated circuit of claim 1, in which the first processing unit and the first secure processing unit are operable to run asynchronously with respect to each other.
29. An electronic appliance comprising:
a single silicon die comprising:
a first processing unit; and
a first secure processing unit, communicatively coupled to the first processing unit, the first secure processing unit comprising:
a first microprocessor;
a first bus interface unit, the first bus interface unit being operable to restrict access to at least some components of the first secure processing unit by the first processing unit;
random-access memory;
non-volatile memory;
a power failure sensing circuit, wherein the power failure sensing circuit is operable to render the non-volatile memory within the first secure processing unit resistant to tampering when a power failure is sensed; and
a direct memory access controller;
random-access memory;
a user interface; and
secondary storage, the secondary storage storing rights management software that, when executed by the first microprocessor of the integrated circuit is operable to cause the electronic appliance to control access to a piece of electronic content by enforcing control information securely associated with the piece of electronic content, the control information specifying one or more permitted uses of the piece of electronic content, wherein the rights management software is resistant to tampering by a user of the electronic appliance with enforcement of the control information.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

We claim:

1. A method of producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation, which comprises the following steps:
prefabricating a basic material wafer by producing a fixed grid of regions of a first conductivity type and regions of a second conductivity type, opposite to the first conductivity type, such that charge compensation is substantially present in a lateral direction in the basic material wafer; and
introducing a rapidly diffusing dopant into edge regions of a compensation component to be produced from the basic material wafer, so that, in the edge regions of the compensation component to be produced, a doping of the rapidly diffusing dopant predominates over a doping of the regions of the opposite conductivity type to the edge regions.
2. The method according to claim 1, which comprises selectively choosing a dopant of the first or the second conductivity type for the rapidly diffusing dopant.
3. The method according to claim 1, which comprises selecting the dopant from the group consisting of selenium and sulfur.
4. The method according to claim 1, which comprises introducing the dopant by ion implantation via a mask having openings of different widths.
5. The method according to claim 1, which comprises introducing the dopant by ion implantation via a VLD mask.
6. The method according to claim 1, wherein the following relationship holds true in the edge region defined between an edge A and a beginning C of a cell array:
3
C
A
(
x
)
x
>

1.5
q
c
where (x) is a charge density in the edge region and qc is a critical charge of the edge region.