Author: claimsbot

1. A method for journey planning, the method comprising:
receiving a journey planning request, the journey planning request comprising an origin and a destination in a transportation network;
calculating, by a processor, an optimized journey plan, wherein calculating the optimized journey plan comprises:
identifying a plurality of routes through the transportation network from the origin to the destination;
determining an uncertainty associated with each of the plurality of routes;
evaluating a robustness of each of the plurality of routes to the uncertainty associated with each of the plurality of routes; and
selecting the optimized journey plan based on the journey planning request and the robustness of each of the plurality of routes.
2. The method of claim 1, wherein the journey planning request further comprises an optimization request and wherein selecting the optimized journey plan is further based on the optimization request.
3. The method of claim 2, the optimization request comprises a worst case arrival time.
4. The method of claim 2, the optimization request comprises a most consistent arrival time.
5. The method of claim 1, wherein determining an uncertainty associated with each of the plurality of routes is based on a historical data associated with the transportation network.
6. The method of claim 1, wherein evaluating a robustness of each of the plurality of routes to the uncertainty associated with each of the plurality of routes includes determining a worst case travel time for each of the plurality of routes and an expected travel time for each of the plurality of routes.
7. The method of claim 1, wherein the transportation system is a multi-modal transportation system.
8. The method of claim 1, wherein at least one of the plurality of routes through the transportation network from the origin to the destination includes multiple contingent branches.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A fastener clip for an airbag retention system having an airbag, said fastener clip comprising:
a body having an opening extending therethrough and an exterior surface;
a rigid retaining pin inserted through the opening; and
at least one detent being formed in one of the exterior surface of the body and the rigid retaining pin, and the other of the exterior surface of the body and the rigid retaining pin having at least one flexible finger which is configured to engage the at least one detent as well as disengage from the at least one detent when the airbag is deployed.
2. A fastener clip in accordance with claim 1 wherein the at least one flexible finger is configured to engage the at least one detent when the airbag is in a standby position to limit the movement of a vehicle trim piece with respect to a vehicle chassis when the airbag is in the standby condition.
3. A fastener clip in accordance with claim 1 wherein the body comprises a substantially rectangular shape, and the at least one detent includes a pair of detents formed on opposite sides of the body.
4. A fastener clip in accordance with claim 1 wherein the body comprises a pair of flexible retention legs adapted to secure the fastener clip to a vehicle chassis.
5. A fastener clip in accordance with claim 1 wherein the at least one flexible finger is adapted to secure a trim piece to a vehicle chassis.
6. A fastener clip in accordance with claim 1, wherein the rigid retaining pin further comprises a rectangular trim stop adapted to limit the movement of the trim piece when the airbag is deployed.
7. A fastener clip in accordance with claim 1, wherein the rigid retaining pin further comprises a flexible spring adapted to limit the movement of the trim piece when the airbag is in a stowed position.
8. A fastener clip in accordance with claim 1, further comprising a concave spring adapted to limit the movement of the trim piece when the airbag is in a stowed position, the at least one flexible finger coupled to the concave spring.
9. A fastener clip in accordance with claim 1, wherein the trim piece has a rectangular opening and the rigid retaining pin further comprises a rectangular trim stop adapted to extend through the rectangular opening and retain the trim piece when the airbag is deployed.
10. A fastener clip in accordance with claim 1 wherein the rigid retaining pin further comprises a pair of catch members, the pair of catch members are deformable to enable the rigid retaining pin to be inserted through the opening in the body.
11. A fastener clip in accordance with claim 1 wherein the body further comprises a pair of stops adapted to engage a pair of catch members to limit the movement of the rigid retaining pin after the airbag has been deployed.
12. A side airbag retention system for use in conjunction with a vehicle including a vehicle chassis, an airbag coupled to the vehicle chassis, and a trim piece adapted to cover the airbag, said airbag retention system comprising:
a fastener clip comprising
a body having an opening extending therethrough;
a pair of detents formed in an exterior surface of the body; and
a rigid retaining pin inserted through the opening, the rigid retaining pin having a pair of flexible fingers configured to engage the pair of detents, the flexible fingers configured to disengage from the pair of detents when an airbag is deployed.
13. An airbag retention system in accordance with claim 12, wherein the flexible fingers are configured to engage the pair of detents when the airbag is in a standby position.
14. An airbag retention system in accordance with claim 12, wherein the body comprises a pair of flexible retention legs adapted to secure the fastener clip to the vehicle chassis.
15. An airbag retention system in accordance with claim 12, wherein the rigid retaining pin further comprises a rectangular trim stop adapted to limit the movement of the trim piece when the airbag is deployed.
16. An airbag retention system in accordance with claim 12, wherein the rigid retaining pin further comprises a flexible spring adapted to limit the movement of the trim piece when the airbag is in a stowed position.
17. An airbag retention system in accordance with claim 12, further comprising a concave spring adapted to limit the movement of the trim piece when the airbag is in a stowed position, the flexible fingers coupled to the concave spring.
18. An airbag retention system in accordance with claim 12, wherein the trim piece has a rectangular opening and the rigid retaining pin further comprises a rectangular trim stop adapted to extend through the rectangular opening and retain the trim piece when the airbag is deployed.
19. An airbag retention system in accordance with claim 12, wherein the rigid retaining pin further comprises a pair of catch members, the pair of catch members are deformable to enable the rigid retaining pin to be inserted through the opening in the body.
20. An airbag retention system in accordance with claim 12, wherein the body further comprises a pair of stops adapted to engage a pair of catch members to limit the movement of the rigid retaining pin after the airbag has been deployed.

1. Bit-detection arrangement able to convert an analog signal (AS) having an amplitude into a digital signal (DS) representing a bit sequence from which the analog signal (AS) is derived, comprising:
a quantizer (11) able to produce an output signal S1 by quantizing the amplitude of the analog signal (AS), and
a phase detector PD1 (12) able to determine a phase difference \u0394P1 between the output signal S1 and a clock signal C2, and able to generate an output signal PH2 having an amplitude, where the amplitude of PH2 indicates the phase difference \u0394P1,
an analog to digital converter ADC (13) which is able to output a processed signal (PrS) by sampling the output signal PH2 at a sample rate controlled by a clock signal C1 having a frequency which is equal to the frequency of clock signal C2 divided by a factor n,
a digital phase locked loop DPLL (2) able to lock on the processed signal (PrS) and able to output a phase signal PH1 using the clock signal C1, and
a bit decision unit (3) able to output the digital signal (DS) and a clock signal C3 using the phase signal PH1, the clock signal C1 and the output signal S1, comprising a sample and hold unit SH1 able to sample the output signal S1, using a clock signal CSH1 having a frequency equal to the frequency of clock signal C2, and to hold n samples, sampley=1 through sampley=n, of the output signal S1 for a clock period of clock signal C1, n being the division factor of clock signal C2, where n is an integer greater than one, characterized in that the bit decision unit further comprises
at least one additional sample and hold unit SH2 able to sample the output signal S1, using a clock signal CSH2 and wherein the frequency of the clock signal CSH2 is equal to the frequency of clock signal CSH1 and the phase of clock signal CSH2 is substantially different from the phase of clock signal CSH1, and
an output unit for outputting samples of either the sample and hold units SH1 or SH2, wherein the samples of the sample and hold unit SH1 are outputted when the phase signal PH1 indicates that the phase difference \u0394P1 is in a first region and the samples of the additional sample and hold unit SH2 are outputted when the phase signal PH1 indicates that the phase difference \u0394P1 is in a second region.
2. Bit-detection arrangement as claimed in claim 1, characterized in that the phase difference between clock signal CSH1 and clock signal CSH2 is approximately 180 degrees and the phase of clock signal CSH1 is approximately equal to the phase of clock signal C2 and wherein in the first region the phase difference \u0394P1 is between 0 degrees and 90 degrees and in the second region the phase difference \u0394P1 is between 90 degrees and 180 degrees.
3. Bit-detection arrangement as claimed in claim 1, characterized in that the bit decision unit further comprises sample and hold units SH3 through SHx, wherein the sample and hold units SH1 through SHx are clocked by clock signals CSH1 through Cx, wherein the frequency of the clock signals CSH2 through CSHx is equal to the frequency of clock signal CSH1 and the phases of the clock signals CSH1 through CSHx are substantially different from each other and in that the output unit is adapted to output samples of the sample and hold units SH1 through SHx, wherein the phase signal PH1 is divided into x regions, x being the number of sample and hold units, and wherein the output unit is able to output samples of the sample and hold unit which corresponds to the region in which the current value of the phase signal PH1 resides.
4. Bit-detection arrangement as claimed in claim 1, characterized in that the bit detection unit further comprises a clock signal selection unit for outputting the clock signal CSH1 and clock signal CSH2 wherein the clock signal selection unit is able to change the phases of the clock signals CSH1 and CSH2 in dependence of the current value of the phase signal PH1.
5. Bit-detection arrangement as claimed in claim 4, characterized in that the clock signal selection unit is fed with clock signals Cf1 through Cfx having a frequency equal to clock signal C2 and wherein the phases of the clock signals Cf1 through Cfx differ from each other, and wherein the clock signal selection unit passes two of the clock signals Cf1 through Cfx through as the clock signals CSH1 and CSH2 in dependence of the phase signal PH1.
6. Apparatus for reproducing information recorded on an information carrier, provided with the bit-detection arrangement as claimed in claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A nonvolatile semiconductor memory comprising:
a semiconductor substrate;
a first transistor formed on a surface of said semiconductor substrate and including a first gate insulating film and a first gate electrode; and
a second transistor formed on the surface of said semiconductor substrate and including a second gate insulating film and a second gate electrode,
wherein said first gate insulating film includes a charge storage layer and said second gate insulating film does not include a charge storage layer, and
said first and second transistors are isolated by a trench and said charge storage layer in said first transistor does not exist in an element isolation region and exists only below said first gate electrode in an element region.
2. A memory according to claim 1, wherein
said first gate insulating film comprises a 1- to 10-nm thick bottom silicon oxide film, a 0.5- to 7-nm thick silicon nitride film as said charge storage layer, and a 5- to 15-nm thick top silicon oxide film, and
the film thickness of said bottom silicon oxide film is smaller than that of said top silicon oxide film.
3. A memory according to claim 1, wherein
said first gate insulating film comprises a 1- to 10-nm thick bottom silicon oxide film, a tantalum oxide film as said charge storage layer, and a 5- to 15-nm thick top silicon oxide film, and
the film thickness of said bottom silicon oxide film is smaller than that of said top silicon oxide film.
4. A memory according to claim 1, wherein
said first gate insulating film comprises a 1- to 10-nm thick bottom silicon film, a film selected from the group consisting of a strontium titanate film and a barium strontium titanate film as said charge storage layer, and a 5- to 15-nm thick top silicon oxide film, and
the film thickness of said bottom silicon oxide film is smaller than that of said top silicon oxide film.
5. A memory according to claim 1, wherein
said nonvolatile semiconductor memory has a cell array which comprises said first transistor as a cell transistor and said second transistor as a selection transistor, and
said second gate insulating film in said second transistor has a 5- to 15-nm thick silicon oxide film.
6. A memory according to claim 1, wherein
said nonvolatile semiconductor memory comprises peripheral transistors in a peripheral region of said cell array,
said peripheral transistors include:
a first peripheral transistor formed on the surface of said semiconductor substrate and including a third gate insulting film and a third gate electrode; and
a second peripheral transistor formed on the surface of said semiconductor substrate and including a fourth gate insulating film and a fourth gate electrode, and
said third and fourth gate insulating films have different film thicknesses.
7. A method of fabricating a nonvolatile semiconductor memory having a cell array including a cell transistor and a selection transistor, comprising the steps of:
forming a first insulating film including a charge storage layer, on a surface of a semiconductor substrate, as a gate insulating film of the cell transistor;
forming a second insulating film not including a charge storage layer, on the surface of the semiconductor substrate, as a gate insulating film of the selection transistor; and
performing element isolation by forming a trench between an element region in which the cell transistor is to be formed and an element region in which the selection transistor is to be formed,
wherein the charge storage layer in the cell transistor does not exist in an element isolation region and exists only below said first gate electrode in the element region.
8. A method according to claim 7, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a 0.5- to 7-nm thick silicon nitride film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
9. A method according to claim 7, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a tantalum oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
10. A method according to claim 7, wherein the first gate insulating film comprises a 1- to 10-nm thick bottom silicon film, a film selected from the group consisting of a strontium titanate film and a barium strontium titanate oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon film.
11. A method according to claim 7, wherein the first and second gate insulating films include an HTO film as the topmost gate insulating layer.
12. A method of fabricating a nonvolatile semiconductor memory having a cell array including a cell transistor and a selection transistor, and a peripheral circuit including a peripheral transistor, comprising the steps of:
forming a first gate insulating film including a charge storage layer, on a surface of a semiconductor substrate, as a gate insulating film of the cell transistor;
forming a second gate insulating film not including a charge storage layer, on the surface of the semiconductor substrate, as a gate insulating film of the selection transistor;
forming a third gate insulating film not including a charge storage layer, on the surface of the semiconductor substrate, as a gate insulating film of the peripheral transistor; and
performing element isolation by forming trenches between an element region in which the cell transistor is to be formed, an element region in which the selection transistor is to be formed, and an element region in which the peripheral transistor is to be formed,
wherein the step of forming the second gate insulating film and the step of forming the third gate insulating film are simultaneously performed, and the charge storage layer in the cell transistor does not exist in an element isolation region and exists only below said first gate electrode in the element region.
13. A method according to claim 12, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a 0.5- to 7-nm thick silicon nitride film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
14. A method according to claim 12, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a tantalum oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
15. A method according to claim 12, wherein the first gate insulating film comprises a 1- to 10-nm thick bottom silicon oxide film, a film selected from the group consisting of a strontium titanate film and a barium strontium titanate oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
16. A method according to claim 12, wherein the first and second gate insulating films include an HTO film as the topmost gate insulating layer.
17. A method of fabricating a nonvolatile semiconductor memory having a cell array including a cell transistor and a selection transistor, and a peripheral circuit including first and second peripheral transistors, comprising the steps of:
forming a first gate insulating film including a charge storage layer, on a surface of a semiconductor substrate, as a gate insulating film of the cell transistor;
forming a second gate insulating film not including a charge storage layer, on the surface of the semiconductor substrate, as a gate insulating film of the selection transistor;
forming a third gate insulating film not including a charge storage layer, on the surface of the semiconductor substrate, as a gate insulating film of the first peripheral transistor;
forming a fourth gate insulating film not including a charge storage layer and thinner than the third gate insulating film, on the surface of the semiconductor substrate, as a gate insulating film of the second peripheral transistor; and
performing element isolation by forming trenches between an element region in which the cell transistor is to be formed, an element region in which the selection transistor is to be formed, and an element region in which the first and second peripheral transistors are to be formed,
wherein the step of forming the second gate insulating film and the step of forming the third gate insulating film are simultaneously performed, and the charge storage layer in the cell transistor does not exist in an element isolation region and exists only below said first gate electrode in the element region.
18. A method according to claim 17, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a 0.5- to 7-nm thick silicon nitride film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
19. A method according to claim 17, wherein the first gate insulating film is formed by stacking a 1- to 10-nm bottom silicon oxide film, a tantalum oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
20. A method according to claim 17, wherein the first gate insulating film comprises a 1- to 10-nm thick bottom silicon oxide film, a film selected from the group consisting of a strontium titanate oxide film and a barium strontium titanate oxide film as the charge storage layer, and a top silicon oxide film whose film thickness is 5 to 15 nm and not less than that of the bottom silicon oxide film.
21. A method according to claim 17, wherein the first and second gate insulating films include an HTO film as the topmost gate insulating layer.