Author: claimsbot

1. A switch, comprising:
(a) first and second terminals;
(b) first and second switch transistors connected in series between said first and second terminals, each of said first and second switch transistors being a field effect transistor of a first conductivity type;
(c) a first biasing resistor connected between the gate of said first switch transistor and said first terminal;
(d) a second biasing resistor connected between the gate of said second switch transistor and said second terminal; and
(e) first and second control transistors, each of said first and second control transistors being a field effect transistor of a second conductivity type opposite said first conductivity type, wherein:
(i) said first control transistor connects between said gate of said first switch transistor and a reference voltage and with the gate of said first control transistor connected to a control input; and
(ii) said second control transistor connects between said gate of said second switch transistor and said reference voltage and with the gate of said second control transistor connected to said control input;

wherein said elements are dimensioned, configured and connected so that when one of a logic high or low value is applied at said control input, said first and second control transistors will be rendered conducting to apply said reference voltage as a gate bias to said first and second switch transistors so that said first and second switch transistors will both be rendered in a conducting state to connect said first and second terminals; and when the other of said logic high or low value is applied to said control input, said first and second control transistors will be rendered non-conducting and said gate bias will be determined by voltage at said first and second terminals acting through said first and second biasing resistors to maintain one of said first and second switch transistors in an open state when voltage at said first terminal is higher or lower than voltage at said second terminal, whether or not the polarity of the voltage applied to said first or second terminal is changed.
2. The switch of claim 1, wherein said first conductivity type is p-channel and said reference voltage is ground.
3. A device, comprising:
(a) a signal input;
(b) a clamp circuit connected to said signal input; and
(c) a signal processing circuit connected to said clamp circuit;
(d) wherein said clamp circuit includes:
(i) a capacitor with a first plate connected to said signal input and a second plate connected to said signal processing circuit;
(ii) a switch connected between said second plate and a supply voltage; and
(iii) a control input for said switch;

(e) and wherein said switch includes:
(i) first and second switch transistors connected in series between said supply voltage and said second plate, each of said first and second switch transistors being a field effect transistor of a first conductivity type;
(ii) a first biasing resistor connected between the gate of said first switch transistor and said supply voltage;
(iii) a second biasing resistor connected between the gate of said second switch transistor and said second plate; and
(iv) first and second control transistors, each of said first and second control transistors being a field effect transistor of a second conductivity type opposite said first conductivity type, wherein (A) said first control transistor connects between said gate of said first switch transistor and a reference voltage and with the gate of said first control transistor connected to said control input, and (B) said second control transistor connects between said gate of said second switch transistor and said reference voltage and with the gate of said second control transistor connected to said control input;
wherein said elements are dimensioned, configured and connected so that when one of a logic high or low value is applied at said control input, said first and second control transistors will be rendered conducting to apply said reference voltage as a gate bias to said first and second switch transistors so that said first and second switch transistors will both be rendered in a conducting state to connect said first and second terminals; and when the other of said logic high or low value is applied to said control input, said first and second control transistors will be rendered non-conducting and said gate bias will be set by voltage at said first and second terminals acting through said first and second biasing resistors to maintain one of said first and second switch transistors in an open state when voltage at said first terminal is higher or lower than voltage at said second terminal, whether or not the polarity of the voltage applied to said first or second terminal is changed.
4. The device of claim 3, wherein said first conductivity type is p-channel and said reference voltage is ground.
5. A switch comprising:
a first terminal connected to a voltage source;
a second terminal at which a varying voltage is developed;
a control signal terminal for receiving a control signal;
a first PMOS transistor having a source coupled to the first terminal, a gate and a drain;
a second PMOS transistor having a source coupled to the drain of the first PMOS transistor, a drain coupled to the second terminal, and a gate;
a first resistor coupled between the source and the gate of the first PMOS transistor;
a second resistor coupled between the gate and the drain of the second PMOS transistor;
a first NMOS transistor having a gate coupled to the control signal terminal, a source connected to ground, and a drain coupled to the gate of the first PMOS transistor; and
a second NMOS transistor having a gate coupled to the control signal terminal, a source connected to ground, and a drain coupled to the gate of the second PMOS transistor;
whereby, when the control signal terminal is at logic high, the first and second NMOS transistors will be turned on to pull to ground the gate terminals of the first and second PMOS transistors, effectively turning on both PMOS transistors, connecting the first and second terminals; and, when the control signal is at logic low, the first and second NMOS transistors will be turned off so that neither of the gate terminals of the first and second PMOS transistors will be connected to ground, and voltage at the gate of the first PMOS transistor will be set by the voltage at the first terminal through the first resistor and voltage at the gate of the second PMOS transistor will be set by the voltage at the second terminal through the second resistor in such way that at least one of the first and second PMOS transistors will be left in an open state when the control signal is at a logic low, even if polarity of voltage applied to the first or second terminal is reversed.
6. A switch comprising:
a first terminal connected to a voltage source;
a second terminal at which a varying voltage is developed;
a control signal terminal for receiving a control signal;
a first NMOS transistor having a drain coupled to the first terminal, a gate and a source;
a second NMOS transistor having a drain coupled to the source of the first NMOS transistor, a source coupled to the second terminal, and a gate;
a first resistor coupled between the drain and the gate of the first NMOS transistor;
a second resistor coupled between the gate and the source of the second NMOS transistor;
a first PMOS transistor having a gate coupled to the control signal terminal, a source connected to a positive voltage source, and a drain coupled to the gate of the first NMOS transistor;
a second PMOS transistor having a gate coupled to the control signal terminal, a source connected to the positive voltage source, and a drain coupled to the gate of the second NMOS transistor;
whereby, when the control signal terminal is at logic low, the first and second PMOS transistors will be turned on to pull to a positive voltage the gate terminals of the first and second NMOS transistors, effectively turning on both NMOS transistors, connecting the first and second terminals; and, when the control signal is at logic high, the first and second PMOS transistors will be turned off so that neither of the gate terminals of the first and second NMOS transistors will be connected to the positive voltage, and voltage at the gate of the first NMOS transistor will be set by the voltage at the first terminal through the first resistor and voltage at the gate of the second NMOS transistor will be set by the voltage at the second terminal through the second resistor in such way that at least one of the first and second NMOS transistors will be left in an open state when the control signal is at a logic high, even if polarity of voltage applied to the first or second terminal is reversed.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computer implemented method, comprising:
exposing, to an application, an interface that comprises a first method;
detecting a first invocation of the first method by the application, wherein the first invocation specifies a first Smart Card-accessing device, a first type of event, and a first function;
in response to detecting the first invocation of the first method, performing steps comprising:
determining whether the first type of event is a type of event that occurs when a reset command is sent to a Smart Card-accessing device; and
if the first type of event is a type of event that occurs when a reset command is sent to a Smart Card-accessing device, then starting a first mechanism that executes the first function each time that the first Smart Card-accessing device receives a reset command;

detecting a second invocation of the first method by the application, wherein the second invocation specifies a second type of event, a second function, and the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function each time that an event of the second type of event occurs relative to the first Smart Card-accessing device, wherein the second mechanism is separate from the first mechanism.
2. The method of claim 1, further comprising:
detecting a second invocation of the first method by the application, wherein the second invocation specifies the first type of event, a second function, and a second Smart Card-accessing device that is separate from the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function each time that the second Smart Card-accessing device receives a reset command.
3. The method of claim 2, wherein the second function differs from the first function.
4. The method of claim 1, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first Smart Card-accessing device; and
in response to detecting the invocation of the second method, stopping the first mechanism.
5. The method of claim 1, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first function; and
in response to detecting the invocation of the second method, stopping the first mechanism without stopping the second mechanism.
6. A computer implemented method, comprising:
exposing, to an application, an interface that comprises a first method;
detecting a first invocation of the first method by the application, wherein the first invocation specifies a first Smart Card-accessing device, a first type of event, and a first function; and
in response to detecting the first invocation of the first method, performing steps comprising:
indicating, to the application, whether a Smart Card is currently present in the first Smart Card-accessing device; and
starting a first mechanism that executes the first function each time that an event of the first type of event occurs relative to the first Smart Card-accessing device;

detecting a second invocation of the first method by the application, wherein the second invocation specifies a second type of event, a second function, and the first Smart Card-accessing device;
in response to detecting the second invocation of the first method, performing steps comprising:
indicating, to the application, whether a Smart Card is currently present in the first Smart Card-accessing device; and

starting a second mechanism that executes the second function each time that an event of the second type of event occurs relative to the first Smart Card-accessing device, wherein the second mechanism is separate from the first mechanism.
7. The method of claim 6, further comprising:
detecting a second invocation of the first method by the application, wherein the second invocation specifies the first type of event, a second function, and a second Smart Card-accessing device that is separate from the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, performing steps comprising:
indicating, to the application, whether a Smart Card is currently present in the second Smart Card-accessing device; and
starting a first mechanism that executes the first function each time that an event of the first type of event occurs relative to the second Smart Card-accessing device.
8. The method of claim 7, wherein the second function differs from the first function.
9. The method of claim 6, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first Smart Card-accessing device; and
in response to detecting the invocation of the second method, stopping the first mechanism.
10. The method of claim 6, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first function; and
in response to detecting the invocation of the second method, stopping the first mechanism without stopping the second mechanism.
11. The method of claim 6, wherein the first type of event is a type of event that occurs when a Smart Card is inserted into a Smart Card-accessing device.
12. The method of claim 6, wherein the first type of event is a type of event that occurs when a Smart Card is removed from a Smart Card-accessing device.
13. A computer implemented method, comprising:
exposing, to an application, an interface that comprises a first method;
detecting a first invocation of the first method by the application, wherein the first invocation specifies a first Smart Card-accessing device, a first type of event, and a first function;
in response to detecting the first invocation of the first method, performing steps comprising:
determining whether the first type of event is a type of event that occurs when a command, which indicates that a Smart Card-accessing device is to be closed, is sent to a Smart Card-accessing device; and
if the first type of event is a type of event that occurs when a command, which indicates that a Smart Card-accessing device is to be closed, is sent to a Smart Card-accessing device, then starting a first mechanism that executes the first function in response to the first Smart Card-accessing device receiving a command that indicates that a Smart Card-accessing device is to be closed;

detecting a second invocation of the first method by the application, wherein the second invocation specifies a second type of event, a second function, and the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function each time that an event of the second type of event occurs relative to the first Smart Card-accessing device, wherein the second mechanism is separate from the first mechanism.
14. The method of claim 13, further comprising:
detecting a second invocation of the first method by the application, wherein the second invocation specifies the first type of event, a second function, and a second Smart Card-accessing device that is separate from the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function in response to the second Smart Card-accessing device receiving a command that indicates that a Smart Card-accessing device is to be closed.
15. The method of claim 14, wherein the second function differs from the first function.
16. The method of claim 13, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first Smart Card-accessing device; and
in response to detecting the invocation of the second method, stopping the first mechanism.
17. The method of claim 13, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first function; and
in response to detecting the invocation of the second method, stopping the first mechanism without stopping the second mechanism.
18. A computer implemented method, comprising:
exposing, to an application, an interface that comprises a first method;
detecting a first invocation of the first method by the application, wherein the first invocation specifies a first Smart Card-accessing device, a first type of event, and a first function;
in response to detecting the first invocation of the first method, performing steps comprising:
determining whether the first type of event is a type of event that occurs when loss of communication with a Smart Card-accessing device is detected; and
if the first type of event is a type of event that occurs when loss of communication with a Smart Card-accessing device is detected, then starting a first mechanism that executes the first function in response to loss of communication with the first Smart Card-accessing device being detected;

detecting a second invocation of the first method by the application, wherein the second invocation specifies a second type of event, a second function, and the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function each time that an event of the second type of event occurs relative to the first Smart Card-accessing device, wherein the second mechanism is separate from the first mechanism.
19. The method of claim 18, further comprising:
detecting a second invocation of the first method by the application, wherein the second invocation specifies the first type of event, a second function, and a second Smart Card-accessing device that is separate from the first Smart Card-accessing device; and
in response to detecting the second invocation of the first method, starting a second mechanism that executes the second function in response to loss of communication with the first Smart Card-accessing device being detected.
20. The method of claim 19, wherein the second function differs from the first function.
21. The method of claim 18, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first Smart Card-accessing device; and
in response to detecting the invocation of the second method, stopping the first mechanism.
22. The method of claim 18, wherein the interface comprises a second method, and further comprising:
detecting an invocation of the second method by the application, wherein the invocation of the second method specifies the first function; and
in response to detecting the invocation of the second method, stopping the first mechanism without stopping the second mechanism.

1. A lock cylinder comprising:
a housing defining a cylindrical cavity, and an outer pin chamber communicating with the cavity, the outer pin chamber being adapted to house an outer pin;
a plug disposed in the cavity and rotatable within the cavity between a locked position and an unlocked position, the plug having an inner pin chamber that is aligned with the outer pin chamber when the plug is in the locked position;
a key slot disposed at least partially through the plug, the key slot communicating with the inner pin chamber;
an inner pin housed in the inner pin chamber for movement along an axis, the inner pin engageable with a key inserted into the key slot, the inner pin engageable with the outer pin when the plug is in the locked position and including an outer surface having a non-axial groove, the non-axial groove having a curved surface defining a substantially semi-circular cross-section; and
an engagement member supported by the plug and having a substantially semispherical end portion extending into the non-axial groove such that the semispherical end portion is substantially engaged with the curved surface.
2. The lock cylinder of claim 1, wherein the non-axial groove is spiral-like.
3. The lock cylinder of claim 2, wherein the non-axial groove is helical.
4. The lock cylinder of claim 1, wherein the non-axial groove defines an angle of incline of about 35 degrees with respect to a vertical axis of the inner pin.
5. The lock cylinder of claim 1, wherein the housing and the plug define a shear line and the inner pin and the outer pin define a parting line, wherein the inner pin is moved to align the parting line with the shear line in response to an appropriate key inserted into the key slot, and wherein the inner pin is configured to rotate as the inner pin is moved in response to insertion of the appropriate key into the key slot.
6. The lock cylinder of claim 1, wherein the engagement member engaged with the non-axial groove is configured to inhibit movement of the inner pin in response to the inner pin being bumped by an inappropriate key in the key slot.
7. The lock cylinder of claim 1, wherein the engagement member is removably disposed within a bore of the plug, and wherein the bore is disposed substantially orthogonal to and in communication with the inner pin chamber and orthogonal to the key slot.
8. A lock cylinder comprising:
a housing defining a cylindrical cavity, and an outer pin chamber communicating with the cavity, the outer pin chamber being adapted to house an outer pin;
a plug disposed in the cavity, the plug rotatable within the cavity and including an inner pin chamber selectively aligned with the outer pin chamber;
a key slot disposed at least partially through the plug;
an inner pin disposed within the inner pin chamber, the inner pin including an outer surface having a non-axial groove, the non-axial groove having a curved surface defining a substantially semi-circular cross-section; and
an engagement member disposed within the plug and having a substantially semispherical end portion extending into the non-axial groove such that the semispherical end portion is substantially engaged with the curved surface to allow relatively slow movement of the inner pin, and to resist relatively quick movement of the inner pin.
9. The lock cylinder of claim 8, wherein the groove is spiral-like.
10. The lock cylinder of claim 9, wherein the groove is helical.
11. The lock cylinder of claim 8, wherein the non-axial groove defines an angle of incline of about 35 degrees with respect to a vertical axis of the inner pin.
12. The lock cylinder of claim 8, wherein the engagement member is configured to allow relatively slow movement of the inner pin in response to the inner pin being engaged by an appropriate key, and wherein the engagement member is configured to resist relatively quick movement of the inner pin in response to the inner pin being bumped by an inappropriate key.
13. The lock cylinder of claim 8, wherein the engagement member is removably disposed within a bore of the plug, and wherein the bore is disposed substantially orthogonal to and in communication with the inner pin chamber and orthogonal to the key slot.
14. A method of operating a lock cylinder, the method comprising:
providing a lock cylinder including a housing defining a cylindrical cavity, and an outer pin chamber communicating with the cavity, the outer pin chamber housing an outer pin;
providing a plug disposed in the cavity and being rotatable within the cavity between a locked position and an unlocked position, the plug having an inner pin chamber aligned with the outer pin chamber when the plug is in the locked position, a key slot disposed at least partially through the plug, the key slot communicating with the inner pin chamber, and an inner pin housed in the inner pin chamber, the inner pin including an outer surface having a non-axial groove with a curved surface defining a substantially semi-circular cross-section, the inner pin engageable with a key inserted into the key slot, and the inner pin engageable with the outer pin when the plug is in the locked position;
engaging the inner pin with an engagement member having a substantially semispherical end portion by extending the substantially semispherical end portion into the non-axial groove and engaging the semispherical end portion with the curved surface;
allowing relatively slow movement of the inner pin in the direction toward the outer pin; and
resisting relatively quick movement of the inner pin in the direction toward the outer pin.
15. The method of claim 14, wherein providing the inner pin with the non-axial groove includes providing the groove with an angle of incline of about 35 degrees with respect to a vertical axis of the inner pin.
16. The method of claim 14, wherein providing the inner pin with the non-axial groove includes providing a spiral-like groove.
17. The method of claim 16, wherein providing the inner pin with the non-axial groove includes providing a helical groove.
18. The method of claim 16, wherein providing the inner pin with the non-axial groove includes providing the inner pin with an outer surface portion defining the spiral-like groove, and wherein allowing relatively slow movement of the inner pin and resisting relatively quick movement of the inner pin also include engaging the engagement member with the outer surface portion.
19. The method of claim 18, wherein providing the inner pin with the non-axial groove includes providing the outer surface portion of the inner pin with a groove defining portion generally facing in the direction toward the outer pin, and wherein allowing relatively slow movement of the inner pin and resisting relatively quick movement of the inner pin also include engaging the engagement member with the groove defining portion.
20. The method of claim 14, wherein allowing relatively slow movement of the inner pin and resisting relatively quick movement of the inner pin include rotating the inner pin.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit (IC) assembly, comprising:
an IC package substrate having a top surface, a bottom surface, and a side surface, the IC package substrate having first signal contacts on the top surface or the bottom surface, and the bottom surface having second signal contacts for coupling with a socket on a circuit board, wherein a first portion of the top surface and the bottom surface are aligned with the socket along a first axis that is parallel with the side surface, and a second portion of the top surface and the bottom surface are not aligned with the socket along the first axis, and the first signal contacts are positioned on the second portion of the top surface or the bottom surface;
an intermediate member having a first end and a second end, and a second axis defined between the first and second ends, the first end having signal contacts coupled to the first signal contacts of the IC package substrate, and the second end extending beyond an edge of the IC package substrate defined by the side surface; and
a male connector, disposed at the second end of the intermediate member, having signal contacts coupled to the signal contacts of the intermediate member, and mateable with a female connector when the female connector is brought into engagement with the male connector in a direction parallel to the second axis.
2. The IC assembly of claim 1, further comprising:
the female connector, having signal contacts to couple to the signal contacts of the male connector when the female and male connectors are engaged; and
a cable having signal carriers coupled to the signal contacts of the female connector, the cable extending in a direction parallel to the second axis when the female and male connectors are engaged.
3. The IC assembly of claim 2, wherein the female connector is a low insertion force connector.
4. The IC assembly of claim 2, wherein the cable is a coaxial cable.
5. The IC assembly of claim 2, wherein the cable is a fiber optic cable.
6. The IC assembly of claim 2, wherein the cable is coupled to a switch coupled to multiple processing units.
7. The IC assembly of claim 1, wherein the intermediate member comprises a flexible flat cable.
8. The IC assembly of claim 1, wherein the intermediate member comprises a rigid circuit board.
9. The IC assembly of claim 8, wherein the male connector comprises an extension portion of the rigid circuit board, the extension portion extending away from a body of the rigid circuit board in a direction of the second axis.
10. The IC assembly of claim 1, wherein the circuit board is a motherboard.