Author: claimsbot

1. An image processing method comprising:
a) texturing at least one surface of a three-dimensional geometric shape by projecting a two-dimensional first image from a two-dimensional first image position and orientation thereof onto said at least one surface of said three-dimensional geometric shape;
b) relatively moving the three-dimensional shape with respect to the image position to which projection of the textured surface is to be made;
c) projecting the textured surface of the three-dimensional geometric shape to the two-dimensional image position to obtain a two-dimensional second image at the two-dimensional first image position and in the same orientation as said first two-dimensional image,
wherein the relative movement of the three-dimensional geometric shape to the two-dimensional first image position generates an aspect ratio change in said second image with respect to said first image; and
d) displaying said second image.
2. A method as in claim 1, wherein said first image forms part of a sequence of first images, the method further comprising:
repeating steps a), b), and c) for each first image in said sequence to obtain a corresponding sequence of second images.
3. A method as in claim 2, wherein the respective sequences of first and second images each form an animated sequence of a face speaking.
4. A method as in claim 2, and further comprising:
displaying said second sequence of second images to a user, and
reproducing recorded or synthesized sound, which may be speech, in synchrony with said display.
5. A method as in claim 4, wherein the moving step further comprises:
moving the relative position of the three-dimensional shape to the two-dimensional first image position in dependence on the energy in the reproduced sound.
6. A method as in claim 1, wherein the moving step further comprises randomly moving relative positions of the three-dimensional geometric shape to the two-dimensional first image position.
7. A method as in claim 1, wherein the moving step further comprises rotating said three-dimensional geometric shape about one or more axes thereof.
8. A method as in claim 7, wherein said rotation is no more than 10 degrees in a clockwise or counter-clockwise direction about one or more of said axes.
9. A method as in claim 1, wherein the shape is one of a group consisting of: a sphere, a cylinder, an ellipsoid, an ovoid, or a double-cylinder.
10. A method as in claim 1, wherein said first image is an image comprising a plurality of pixels located at the two-dimensional first position in a virtual space, and said three-dimensional geometric shape is a data representation of a three-dimensional virtual model of a three-dimensional geometric shape located in said virtual space, modeled by a processor.
11. A tangible storage medium containing a computer program which, when executed by a computer system, causes the computer system to perform the method of claim 1.
12. An image processing system comprising:
image receiving means for receiving a first image to be processed;
image processing means; and
image output means for outputting a second, processed image;
the image processing means comprising shape modeling means arranged to model a three-dimensional geometric shape with a projection of a two-dimensional first image from a two-dimensional first image position and orientation thereof onto said at least one surface;
b) relatively move the three-dimensional shape with respect to the image position to which projection of the textured surface is to be made, and
c) project the textured surface of the three-dimensional geometric shape to the two-dimensional image position to obtain a two-dimensional second image at the two-dimensional first image position and in the same orientation as said first two-dimensional image, wherein the relative movement of the three-dimensional geometric shape to the two-dimensional first image position generates an aspect ratio change in said second image with respect to said first image.
13. A system as in claim 12, wherein said first two-dimensional image forms part of a sequence of first images, the system being further arranged to:
receive each first image in said sequence at said image receiving means,
said image processing means being arranged to repeat steps a), b), and c) for each first image in said sequence to obtain a corresponding sequence of second images.
14. A system as in claim 13, wherein the respective sequences of first and second images each form an animated sequence of a face speaking.
15. A system as in claim 13, and further comprising:
display means for displaying said second sequence of two-dimensional second images to a user, and
sound reproduction means for reproducing recorded or synthesized sound, which may be speech, in synchrony with said display.
16. A system according to claim 15, wherein the image processing means is further arranged to move the relative position of the three-dimensional geometric shape to the two-dimensional first image position in dependence on the energy in the reproduced sound.
17. A system as in claim 12, wherein the image processing means is further arranged to move the relative position of the three-dimensional geometric shape to the two-dimensional first image position randomly.
18. A system as in claim 12, wherein the image processing means is further arranged to move the relative position of the three-dimensional geometric shape by rotating said three-dimensional geometric shape about one or more axes thereof.
19. A system according to claim 18, wherein said rotation is no more than 10 degrees in a clockwise or counter-clockwise direction about one or more of said axes.
20. A system as in claim 12, wherein the three-dimensional shape is one of a group consisting of: a sphere, a cylinder, an ellipsoid, an ovoid, or a double-cylinder.
21. A system as in claim 12, wherein said two-dimensional first image is an image comprising a plurality of pixels located at said first position in a virtual space, and said three-dimensional geometric shape is data representative of a three-dimensional virtual model of a geometric shape located in said virtual space, modeled by said shape modeling means.
22. A method as in claim 1 wherein the textured surface is a three-dimensional surface.
23. A method as in claim 1 wherein the geometric shape is kept in the same position and the image position to which the projection of the textured surface is made is moved around the shape.
24. A method as in claim 8 wherein said rotation is no more than 1 degree in a clockwise or counter-clockwise direction about said axes.
25. A system as in claim 19 wherein said rotation is no more than 1 degree in a clockwise or counter-clockwise direction about said axes.
26. A system as in claim 12 wherein the geometric shape is kept in the same position and the image position to which the projection of the textured surface is made is moved around the shape.
27. A system as in claim 12 wherein said textured surface is a three-dimensional surface.
28. Apparatus for implementing a method according to claim 1, the apparatus comprising:
a computer-readable storage medium storing a computer program, wherein in use said apparatus is arranged to enable said computer program to be executed by a computer system which causes the computer system to perform the method of claim 1.
29. An image processing method for creating an image sequence simulating a talking and moving head, said method comprising:
a) texturing a surface of a three-dimensional geometric shape by projecting a two-dimensional first image representing a human head from a first position;
b) moving the three-dimensional shape relative to the image position;
c) projecting the textured surface of the three-dimensional geometric shape to the two-dimensional image position so as to obtain a second two-dimensional image at the same first image position and in the same orientation;
d) repeating steps a\u2013c to create a sequence of images representing said talking and moving head,
wherein the relative movement of the tree-dimensional geometric shape to the two-dimensional first image position generates an aspect ratio change in said second image with respect to said first image; and
e) displaying said second image.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A capacitor comprising:
a storage electrode that includes a storage conductive pattern and a complementary member, an upper portion of the storage conductive pattern having a first surface and a second surface opposite the first surface, the complementary member formed on the first surface of the upper portion of the storage conductive pattern and structured to compensate for an etch loss of the storage conductive pattern;
a dielectric layer formed directly on the second surface of the upper portion of the storage conductive pattern such that the upper portion of the storage conductive pattern is between the dielectric layer and the complementary member; and
a plate electrode formed on the dielectric layer.
2. The capacitor of claim 1, wherein the complementary member encloses the upper portion of the storage conductive pattern.
3. The capacitor of claim 1, wherein an interior portion of the complementary member is attached to the storage conductive pattern, and a lower portion of the complementary member is supported by the storage conductive pattern.
4. The capacitor of claim 1, wherein the storage conductive pattern and the complementary member include a substantially identical material.
5. The capacitor of claim 1, wherein the storage conductive pattern and the complementary member are integrally formed.
6. The capacitor of claim 1, wherein the storage electrode has a cylindrical structure.
7. The capacitor of claim 6, wherein the cylindrical structure has a stepped cylindrical structure, where a diameter of the cylindrical structure decreases as a height of the storage electrode increases.
8. The capacitor of claim 1, wherein the storage electrode comprises an upper portion, a central portion, and a lower portion that have thicknesses that are different from one another.
9. The capacitor of claim 1, wherein the storage electrode comprises an upper portion, a central portion and a lower portion, and wherein the central and lower portions of the storage electrode have substantially identical thicknesses, and the upper portion of the storage electrode has a thickness that is greater than those of the central and lower portions.
10. The capacitor of claim 1, wherein the lower portion of the storage electrode protrudes inwardly.
11. A capacitor comprising:
a storage electrode that includes a storage conductive pattern and a structure, an upper portion of the storage conductive pattern having a first surface and a second surface opposite the first surface, the structure formed on the first surface of the upper portion and enclosing the upper portion of the storage conductive pattern;
a dielectric layer disposed directly on the second surface of the upper portion of the storage conductive pattern such that the upper portion of the conductive pattern is between the dielectric layer and the structure; and
a plate electrode disposed on the dielectric layer.
12. The capacitor of claim 11, wherein the structure and the storage conductive pattern are integrally formed.
13. The capacitor of claim 11, wherein the storage electrode has a stepped cylindrical structure where a diameter of the stepped cylindrical structure incrementally decreases as a height of the storage electrode increases.
14. The capacitor of claim 11, wherein a lower portion of the storage conductive pattern protrudes inwardly.
15. A capacitor comprising:
a storage electrode that includes a storage conductive pattern and a complementary member, wherein the storage electrode has a stepped structure and a lowermost surface of the complementary member is directly on a portion of the stepped structure;
a dielectric layer disposed on the storage electrode; and
a plate electrode disposed on the dielectric layer.
16. The capacitor of claim 15, wherein the and a complementary member encloses an upper portion of the storage conductive pattern and is integrally formed with the storage conductive pattern.
17. A semiconductor device comprising:
a semiconductor substrate that includes a first contact region and a second contact region;
a bit line that is electrically connected to the second contact region;
a storage electrode that includes a storage conductive pattern and a complementary member, an upper portion of the storage conductive pattern having a first surface and a second surface opposite the first surface, the complementary member formed on the first surface of the upper portion and enclosing the upper portion of the storage conductive pattern;
a dielectric layer disposed directly on the second surface of the upper portion of the storage conductive pattern such that the upper portion of the conductive pattern is between the dielectric layer and the structure; and
a plate electrode disposed on the dielectric layer.
18. The semiconductor device of claim 17, wherein the complementary member and the storage conductive pattern are integrally formed.
19. The semiconductor device of claim 17, wherein an interior of the complementary member is attached to the storage conductive pattern, and a lower portion of the complementary member is supported by the storage conductive pattern.
20. The semiconductor device of claim 17, wherein the storage electrode has a stepped cylindrical structure where a diameter of the stepped cylindrical structure decreases as a height of the storage electrode increases.
21. The semiconductor device of claim 17, wherein the storage electrode comprises a central portion and a lower portion having a substantially identical thickness, and an upper portion having a thickness that is greater than those of the central and lower portions of the storage electrode.
22. The semiconductor device of claim 17, wherein the storage electrode has a stepped cylindrical structure where a diameter of the stepped cylindrical structure decreases as a height of the storage electrode increases, and where a lower portion of the storage electrode protrudes inwardly.

1. A rail-to-rail (R-R) input stage circuit operating over a rail-to-rail input common mode voltage range, comprising:
a differential pair circuit, having a first input common mode voltage range, coupled to a level shifted differential pair, having a second input common mode voltage range to enable operation of the R-R input stage circuit over an input common mode voltage that extends from a negative power supply to a positive power supply; and
a first bias control circuit, coupled to the level shifted differential pair, to dynamically control the bias current of the level shifted differential pair when the input common mode voltage of the R-R input stage circuit is outside the second input common voltage range.
2. The R-R input stage circuit of claim 1, where the first bias control circuit gradually turns off the level shifted differential pair in response to the input common mode voltage of the R-R input stage circuit.
3. The R-R input stage circuit of claim 1, where the first bias control circuit further comprises a voltage sensor circuit for generating a tracking current inversely proportional to a sensed input common mode voltage of the R-R input stage, when the input common mode voltage of the R-R input stage circuit is outside the second input common voltage range.
4. The R-R input stage circuit of claim 3, further comprising a current mirror circuit having one terminal coupled to the voltage sensor circuit and a second terminal coupled to the current source of the level shifted differential pair to control the bias current of the level shifted differential pair in response to the tracking current.
5. The R-R input stage circuit of claim 3, where the voltage sensor circuit is a MOS device, and where the input common mode voltage of the R-R input stage circuit controls the gate of the MOS device.
6. The R-R input stage circuit of claim 4, where the current mirror comprises a MOS device, having its gate and drain coupled to the voltage sensor circuit and to the current source of the level shifted differential pair.
7. The R-R input stage circuit of claim 1, where the differential pair circuit comprises a pair of matched MOS transistors and a current source.
8. The R-R input stage circuit of claim 1, where the level shifted differential pair comprises a source follower and a differential pair circuit, where the differential pair circuit comprises a pair of matched MOS transistors and a current source.
9. The source follower of claim 8, comprising a pair of matched MOS transistors of type complementary to that of the MOS transistors of the differential pair circuit.
10. The R-R input stage circuit of claim 3, further comprising a second bias control circuit, coupled to the differential pair circuit, to dynamically control the bias current of the differential pair circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
11. The R-R input stage circuit of claim 10, where the second bias control circuit gradually turns off the differential pair circuit in response to the input common mode voltage of the R-R input stage circuit.
12. The R-R input stage circuit of claim 10, further comprising a first gm control circuit having a first terminal coupled to the first bias control circuit and a second terminal coupled to the current source of the differential pair circuit, where the first gm control circuit adjusts the current through the differential pair circuit to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
13. The R-R input stage circuit of claim 12, where the first gm control circuit adjusts the current through the differential pair circuit in response to the tracking current generated by the first bias control circuit.
14. The R-R input stage circuit of claim 13, further comprising a second gm control circuit having a first terminal coupled to the second bias control circuit and a second terminal coupled to the current source of the level shifted differential pair, where the second gm control circuit adjusts the current through the level-shifted differential pair to maintain substantially constant the transconductance of the R-R input stage circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
15. The R-R input stage circuit of claim 14, where the second gm control circuit adjusts the current through the level shifted differential pair in response to the tracking current generated by the second bias control circuit.
16. A rail-to-rail (R-R) input stage circuit operating over a rail-to-rail input common mode voltage range, comprising:
a differential pair circuit, having a first input common mode voltage range, coupled to a level shifted differential pair, having a second input common mode voltage range to enable operation of the R-R input stage circuit over an input common mode voltage that extends from negative power supply to positive power supply; and
first means, coupled to the level shifted differential pair, for dynamically controlling the bias current of the level shifted differential pair when the input common mode voltage of the R-R input stage circuit is outside of the second input common mode voltage range.
17. The R-R input stage circuit of claim 16, where the first means gradually turns off the level shifted differential pair in response to the input common mode voltage of the R-R input stage circuit.
18. The R-R input stage circuit of claim 16, where the first means includes means for sensing the input common mode voltage of the R-R input stage circuit.
19. The R-R input stage circuit of claim 18, where the means for sensing also generate a tracking current inversely proportional to the sensed input common mode voltage, when the input common mode voltage of the R-R input stage circuit is outside the second input common mode voltage range.
20. The R-R input stage circuit of claim 19, where the first means further comprises means for mirroring the tracking current to the current source of the level shifted differential pair to control the bias current of the level shifted differential pair.
21. The R-R input stage circuit of claim 19, further comprising second means coupled to the differential pair circuit, to dynamically control the bias current of the differential pair circuit when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
22. The R-R input stage circuit of claim 21, where the second means gradually turns off the differential pair circuit in response to the input common mode voltage of the R-R input stage circuit.
23. The R-R input stage circuit of claim 22, where the second means includes means for sensing the input common mode voltage of the R-R input stage circuit.
24. The R-R input stage circuit of claim 23, where the means for sensing also generate a tracking current inversely proportional to the sensed input common mode voltage, when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
25. The R-R input stage circuit of claim 19, further comprising first gm control means having a first terminal coupled to the first means and a second terminal coupled to the differential pair circuit, where the first gm control means adjusts the current through the differential pair circuit in response to the tracking current generated by the first means, to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the first input common mode voltage range.
26. The R-R input stage circuit of claim 25, further comprising second gm control means having a first terminal coupled to the second means and a second terminal coupled to the level shifted differential pair, where the second gm control means adjust the current through the level shifted differential pair in response to the tracking current generated by the second means, to maintain the transconductance of the R-R input stage circuit substantially constant when the input common mode voltage of the R-R input stage circuit is outside the second input common mode voltage range.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-11. (canceled)
12. A kit for performing a blood sedimentation rate analysis, comprising:
a) a substantially optically clear glass tube having an overall length of about 100 to about 300 mm and a wall thickness of about 0.5 to about 1.5 mm, and having a plastic containment barrier with a thickness of less than about 1 mm and a closed end, and containing an additive including a surfactant that is free of clouding under the conditions to which it will be exposed prior to and during sedimentation rate testing and at least one additional additive selected from the group consisting of an anti-microbial, and anti-coagulant, a preservative, or any combination thereof; and
b) at least two components for performing a blood sedimentation rate analysis selected from an alcohol swab, gauze, a tube holder, a tube rack for performing a blood sedimentation rate analysis, a tourniquet, a glove, another cell collection tube, needle, lancet, adhesive strip, syringe, test strip, glass or plastic strip containing reagents for cell analysis, packaging to store the desired components, packaging to transport the blood sample stored in the tube after collection, a timer, a worksheet, or any combination thereof.
13. The kit of claim 12, wherein the surfactant is present in sufficient amount that it is capable of providing reproducible sedimentation rate tests in a consistent and reproducible manner that approximates that of a fresh blood sample after a delay of more than about 6 hours.
14. The kit of claim 13, wherein the surfactant is a nonionic surfactant of the form CxEy, where x is the number of carbons in the alkyl chain (C) and y is the number of ethylene oxide units in the polyoxyethylene chain (E).
15. The kit of claim 14, wherein x is from about 6 to about 18 and y is from about 4 to about 40.
16. A blood collection tube for sedimentation rate analysis, comprising:
an evacuated and sealed elongated glass tube with an open first end for receiving a venipuncture blood sample of at least 1 ml, formed with a closed end opposite the first end;
a plastic containment barrier that is substantially transparent and substantially encapsulates the elongated glass tube so that following a fracture of the tube, blood is contained within the tube;
and a surfactant, based upon polyoxyethylene alcohols, polyoxyethylene alkylphenols, or a combination thereof, being present in sufficient amount that it is capable of providing reproducible sedimentation rate tests in a consistent and reproducible manner that approximates that of a fresh blood sample after a delay of more than about 6 hours, and that is free of clouding under the conditions to which it will be exposed Prior to and during sedimentation rate testing.
17. The blood collection tube of claim 16, wherein the surfactant is a nonionic surfactant of the form CxEy, where x is the number of carbons in the alkyl chain (C) and y is the number of ethylene oxide units in the polyoxyethylene chain (E).
18. The blood collection tube of claim 17, wherein x is from about 6 to about 18 and y is from about 4 to about 40.
19. The blood collection tube of claim 18, wherein the surfactant is present in a concentration of about 0.1 gl to about 5 gl, the surfactant is selected to have an average monomer molecular weight in the range of about 500 to about 2000, and the surfactant will have an aggregation number that ranges from about 20 to about 120; and further comprising at least one additional additive selected from the group consisting of an anti-microbial, and anti-coagulant, a preservative, or any combination thereof.
20. The blood collection tube of claim 19, wherein the surfactant is present such that a sedimentation rate test approximating that of fresh blood is obtained after a period of at least 4 days between the time of the blood draw and sedimentation rate testing.
21. A method for performing an erythrocyte sedimentation rate analysis, comprising:
drawing a venipuncture blood sample into an evacuated and sealed elongated glass tube with an open first end and a closed end opposite the first end, the elongated glass tube including a containment barrier that is substantially transparent and substantially encapsulates the elongated glass tube so that following a fracture of the tube, the blood sample is contained within the tube;
contacting the blood sample with a surfactant in the glass tube, the surfactant being free of clouding under the conditions to which it will be exposed prior to and during sedimentation rate testing; and
performing the erythrocyte sedimentation rate analysis while the blood sample is contained within the tube.
22. The method of claim 21, wherein the surfactant is a nonionic surfactant of the form CxEy, where x is the number of carbons in the alkyl chain (C) and y is the number of ethylene oxide units in the polyoxyethylene chain (E).
23. The method of claim 22, wherein x is from about 6 to about 18 and y is from about 4 to about 40.
24. The method of claim 23, wherein the surfactant is present in a concentration of about 0.1 gl to about 5 gl, the surfactant is selected to have an average monomer molecular weight in the range of about 500 to about 2000, and the surfactant will have an aggregation number that ranges from about 20 to about 120;
25. The method of claim 21, wherein the surfactant is selected from polyoxyethylene (20) sorbitan monolaurate, polyoxyethylene (23) lauryl ether, polyoxyethylene (9) mono(octylphenyl)ether, polyoxyethylene octylphenyl ether, or any combination thereof.
26. The method of claim 21, wherein the surfactant is selected from organosilicone surfactants, alcohols, esters of fatty acids, mercaptans, and alkylamines; nonionic surfactants containing an amide group; polyol ester surfactants or any combination thereof
27. The method of claim 22, further comprising contacting the blood sample in the tube with at least one additional additive selected from the group consisting of an anti-microbial, and anti-coagulant, a preservative, or any combination thereof.