1. A method of making a semiconductor device, comprising:
forming a dielectric layer over dummy gate electrodes overlying a semiconductor substrate having an N-channel region and a P-channel region;
exposing an upper surface of said dummy gate electrodes;
removing said dummy gate electrodes thereby forming trenches;
forming a gate dielectric layer, a barrier conductive layer and a silicon layer in said trenches, wherein a thickness of said barrier conductive layer in trenches overlying said N-channel region is different from a thickness of said barrier conductive layer in trenches overlying said P-channel region;
depositing a first metal on said silicon layer, said first metal being capable of undergoing a substitution reaction with silicon; and
annealing said first metal so as to effect a substitution of said first metal for said silicon layer and removing a silicon-containing layer that is formed overlying said first metal by said substitution, said substitution of said first metal for said silicon layer forming a metal substituted layer.
2. The method according to claim 1, further comprising forming a layer of a second metal on said first metal deposited by said depositing step, prior to performing said annealing step, said second metal being capable of forming a silicide.
3. The method according to claim 2, wherein said second metal is titanium.
4. The method according to claim 1, wherein said dummy gate electrodes are positioned between respective pairs of sidewalls, and wherein said trenches are formed between respective pairs of said sidewalls.
5. The method according to claim 4, further comprising etching said silicon layer such that an upper surface of said silicon layer is recessed from upper surfaces of said sidewalls, prior to depositing said metal on said silicon layer.
6. The method according to claim 4, wherein said sidewalls are spaced from one another by a length of 20 nm or less.
7. The method according to claim 6, wherein said sidewalls are spaced from one another by the length of 10-20 nm.
8. The method according to claim 6, wherein said trenches have a depth of 60 nm or less.
9. The method according to claim 8, wherein said trenches have trenches have the depth of 40-60 nm.
10. The method according to claim 1, said barrier conductive layer is a nitrogen-containing film.
11. The method according to claim 1, wherein said annealing is conducted at a temperature of 400\xb0 C. to 500\xb0 C.
12. The method according to claim 1, wherein said first metal has a silicon content of 0.1 to 10 atomic % following said annealing.
13. The method according to claim 1, wherein said first metal is at least one of Al, Cu, Ag, Pt and W.
14. The method of claim 1, wherein said semiconductor device, after said annealing step, comprises:
said semiconductor substrate, said N-channel transistor and said P-channel transistor formed on said semiconductor substrate, with each of said N-channel transistor and said P-channel transistor having the gate dielectric film overlying said substrate, and with said gate electrode overlying said gate dielectric film, said gate electrode comprising said metal substituted layer,
said barrier conductive layer is located between said gate dielectric film and said metal substituted layer, and
said barrier conductive layer of said N-channel transistor has a different thickness than said barrier conductive layer of said N-channel transistor.
15. The method of claim 14, wherein said metal substituted layer has a silicon content from 0.1 to 10 atomic % following said annealing.
16. The method of claim 15, wherein said metal substituted layer comprises at least one metal selected from the group consisting of Al, Cu, Ag, Pt and W.
17. The method of claim 14, wherein each of said N-channel transistor and said P-channel transistor has a gate length of 20 nm or less.
18. The method of claim 17, wherein each of said N-channel transistor and said P-channel transistor has the gate length of 10-20 nm.
19. The method of claim 17, wherein each of said N-channel transistor and said P-channel transistor has a gate height of 60 nm or less.
20. The method of claim 19, wherein each of said N-channel transistor and said P-channel transistor has the gate height of 40-60 nm.
21. The method of claim 20, wherein said protective dielectric layer provides stress for a channel region of said transistor.
22. The method of claim 14, wherein said dielectric layer comprises silicon nitride.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising a first layer bearing first metallization patterned for defining a first inductive coil, a second layer bearing second metallization patterned for defining a second inductive coil that overlies the first inductive coil and that is magnetically coupled to the first inductive coil through a third layer interposed between the first layer and the second layer, said third layer bearing third metallization for defining an electric shield, the third metallization being patterned into a plurality of structures having shapes intended to minimize eddy currents and being connected to further metallization that carries a ground potential.
2. An integrated circuit as in claim 1, where said third layer further bears other metallization for coupling together at least two components of said integrated circuit.
3. An integrated circuit as in claim 1, where said electric shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of a frequency of an electrical signal that is applied to said first inductive coil.
4. An integrated circuit as in claim 1, where said electric shield is patterned to form a plurality of ribbon structures, each ribbon being spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and said second metallization.
5. An integrated circuit as in claim 1, where said electric shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of a frequency of an electrical signal that is applied to said first inductive coil and each ribbon being spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and said second metallization.
6. An integrated circuit as in claim 1, where said electric shield is patterned to form a plurality of groups of ribbon structures, within each group the ribbon structures being electrically connected together at one point, and each group being electrically connected together at one point for being connected to the further metallization that carries the ground potential.
7. An integrated circuit as in claim 6, where each group of ribbon structures is electrically connected together at a point located at about a center of the patterning of the first and second metallizations.
8. An integrated circuit as in claim 1, further comprising a fourth layer interposed between the first layer and the second layer, said fourth layer bearing fourth metallization for defining a second electric shield, the fourth metallization also being patterned into a plurality of structures having shapes intended to minimize eddy currents and being connected to still further metallization that carries a ground potential.
9. An integrated circuit as in claim 8, where the further metallization that carries the ground potential carries a ground potential associated with said first inductive coil, and where the still further metallization that carries the ground potential carries a ground potential associated with said second inductive coil.
10. An integrated circuit as in claim 1, where the third metal is a non-ferrous metal.
11. A radio frequency integrated circuit (RFIC) comprising a first layer bearing first metallization patterned for defining a primary coil of at least one transformer, a second layer bearing second metallization patterned for defining a secondary coil of the at least one transformer, one of the primary or the secondary coil overlying the other one of the secondary or primary coil and being magnetically coupled thereto through a third layer interposed between the first layer and the second layer, said third layer bearing third metallization for defining an electrostatic shield for the at least one transformer, the third metallization being patterned into a plurality of structures having shapes intended to minimize eddy currents and being connected to further metallization that carries a ground potential, where said third layer further bears other metallization for coupling together at least two components of said RFIC.
12. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of the RF frequency of an electrical signal that is applied to said primary coil.
13. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of a skin depth in the third metallization of an RF frequency of an electrical signal that is applied to said primary coil.
14. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon being spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and said second metallization.
15. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of the RF frequency of an electrical signal that is applied to said primary coil and each ribbon being spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and said second metallization.
16. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of a skin depth in the third metallization of an RF frequency of an electrical signal that is applied to said primary coil and each ribbon being spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and said second metallization.
17. An RFIC as in claim 11, where said electrostatic shield is patterned to form a plurality of groups of ribbon structures, within each group the ribbon structures being electrically connected together at one point, and each group being electrically connected together at one point for being connected to the further metallization that carries the ground potential.
18. An RFIC as in claim 17, where each group of ribbon structures is electrically connected together at a point located at about a center of the patterning of the first and second metallizations.
19. An RFIC as in claim 11, further comprising a fourth layer interposed between the first layer and the second layer, said fourth layer bearing fourth metallization for defining a second electrostatic shield, the fourth metallization also being patterned into a plurality of structures having shapes intended to minimize eddy currents and being connected to still further metallization that carries a ground potential.
20. An RFIC as in claim 19, where the further metallization that carries the ground potential carries a ground potential associated with said primary coil, and where the still further metallization that carries the ground potential carries a ground potential associated with said secondary coil.
21. An RFIC as in claim 11, where the third metal is a non-ferrous metal.
22. An RFIC as in claim 11, where the RFIC is constructed using a CMOS process.
23. A method to construct a planar transformer in an integrated circuit, comprising:
fabricating a first layer bearing first metallization patterned for defining a first inductive coil;
fabricating a second layer over the first layer, the second layer bearing second metallization for defining an electric shield, the second metallization being patterned into a plurality of structures having shapes intended to minimize eddy currents, where fabricating the second layer comprises fabricating an electrical connection for coupling the electric shield to a ground potential; and
fabricating a third layer over the second layer, the third layer bearing third metallization patterned for defining a second inductive coil that overlies the first inductive coil and that is magnetically coupled to the first inductive coil through the electric shield.
24. A method as in claim 23, where fabricating the second layer further comprises providing additional metallization associated with other circuitry.
25. A method as in claim 23, where fabricating the second layer comprises fabricating a fourth layer over the second layer, and where fabricating the third layer fabricates the third layer over the fourth layer, the fourth layer bearing fourth metallization for defining a second electric shield, the fourth metallization also being patterned into a plurality of structures having shapes intended to minimize eddy current, where fabricating the fourth layer comprises fabricating a second electrical connection for coupling the second electric shield to ground potential.
26. A method as in claim 25, where the electrical connection couples the electric shield to a ground potential associated with one of the first inductive coil or the second inductive coil, and where the second electrical connection couples the second electric shield to a ground potential associated with the other one of the first inductive coil or the second inductive coil.
27. A method as in claim 23 where the fabricating steps are carried out in accordance with a CMOS process, and where the integrated circuit contains radio frequency (RF) circuitry.
28. A method as in claim 27, where the electrostatic shield is patterned to form a plurality of ribbon structures, each ribbon having a width that is a function of a skin depth in the second metallization of a radio frequency of an electrical signal that is applied to said primary coil.
29. A method as in claim 28, where each ribbon is spaced apart from an adjacent ribbon by a distance that is a function of a distance between said first metallization and third second metallization.
30. A method as in claim 23, where the second metal is a non-ferrous metal.
31. A radio frequency integrated circuit (RFIC) comprising a first layer bearing first electrically conductive material patterned for defining a primary coil of at least one transformer, a second layer bearing second electrically conductive material patterned for defining a secondary coil of the at least one transformer, one of the primary or the secondary coil overlying the other one of the secondary or primary coil and being magnetically coupled thereto through a third layer interposed between the first layer and the second layer, said third layer bearing third electrically conductive material for defining at least one electric shield for the at least one transformer, the third electrically conductive material being patterned into a plurality of structures having shapes intended to minimize eddy currents and being connected to further electrically conductive material that carries a ground potential.
32. An RFIC as in claim 31, where at least some of said electrically conductive material is comprised of metal.
33. An RFIC as in claim 31, where at least some of said electrically conductive material is comprised of a non-metal.
34. An RFIC as in claim 31, where said transformer is a balanced transformer, and where said at least one electric shield functions to improve the symmetry of the balanced transformer.
35. An RFIC as in claim 31, where said RFIC comprises a plurality of transformers, and where said third layer bears the third electrically conductive material for defining, for each of said plurality of transformers, at least one electric shield.
36. An RFIC as in claim 35, where said third layer further bears other electrically conductive material for coupling together at least two components of said RFIC.