Author: claimsbot

1. A process comprising:
polymerizing
(a) propylene,
(b) at least one C4-C8 \u03b1-olefin, and
(c) optionally ethylene, wherein the polymerizing step is carried out in the gas-phase,
wherein the process is carried out in a reactor having two interconnected polymerization zones, a riser and a downcomer,
wherein polymer particles flow through the riser under fast fluidization conditions, leave said riser and enter the downcomer,
wherein the polymer particles in the downcomer flow downward in a densified form, leave said downcomer and are reintroduced into said riser, thus establishing a circulation of polymer between the riser and the downcomer,
wherein a gas mixture present in the riser is prevented from entering the downcomer by introducing a liquid barrier into an upper part of said downcomer, thereby creating a recycle gas mixture that flows upward to a separation zone wherein the liquid barrier comprises at least one C4-C8 \u03b1-olefin in a total amount of from 0.1% to 35% by mol, and has a composition different from the gas mixture present in the riser,
wherein the recycle gas is separated into:
(i) a first stream of recycled gas, wherein the first stream of recycled gas is fed into a bottom part of the downcomer,
(ii) a second stream of recycled gas, wherein the second stream of recycled gas is fed into a bottom part of the riser; and
(iii) a third stream of recycled gas, wherein the third stream of recycled gas is fed into at least one distillation column before being recycled into the downcomer.
2. The process according to claim 1, wherein the partial evaporation of said liquid barrier generates in the upper part of the downcomer a flow of gas moving counter-currently to the flow of descendent polymer.
3. The process according to claim 1, wherein the C4-C8 \u03b1-olefin is 1-hexene and its amount ranges from 0.1% to 10% by mol.
4. The process according to claim 3, wherein the liquid barrier further comprises:
from 70 to 90% by mol of propylene;
from 5 to 15% by mol of propane; and
from 0 to 5% by mol of ethylene.
5. The process according to claim 4, wherein the obtained polyolefin contains from 0.2 to 8.0% by weight of recurring units derived from 1-hexene.
6. The process according to claim 1, wherein the C4-C8 \u03b1-olefin is 1-butene and its amount ranges from 2% to 30% by mol.
7. The process according to claim 6, wherein the liquid barrier further comprises:
from 50 to 90% by mol of propylene;
from 5 to 15% by mol of propane; and
from 0 to 5% by mol of ethylene.
8. The process according to claim 7, wherein the obtained polyolefin contains from 1 to 25% by weight of recurring units derived from 1-butene.
9. The process according to claim 1, wherein the liquid barrier derives from condensation andor distillation of a part of the gaseous stream continuously recycled to said reactor having two interconnected polymerization zones.
10. The process according to claim 9, wherein the composition of the liquid barrier is adjusted by feeding liquid make-up monomers and propane before introducing said liquid barrier into the upper part of the downcomer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode formed in a portion over a lower electrode and the lower electrode;
an antioxidant film which is formed covering an upper surface of the lower electrode, and a side surface of the TMR film at least, about the memory cell; and
an oxide film formed over the antioxidant film.
2. A semiconductor device according to claim 1, wherein
the antioxidant film covers a side surface of the lower electrode further.
3. A semiconductor device according to claim 1, wherein
the antioxidant film includes a plurality of antioxidant films.
4. A semiconductor device according to claim 1, further comprising:
a read wire which separates a predetermined distance from the TMR film in plan view and is formed under the lower electrode; and
a metal plug which is formed over the read wire and electrically connects the read wire and the lower electrode.
5. A semiconductor device according to claim 1, wherein
the upper electrode includes a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
6. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode which were formed in a portion over a lower electrode and the lower electrode;
a read wire which separates a predetermined distance from the TMR film in plan view and is formed under the lower electrode; and
a metal plug which is formed over the read wire and electrically connects the read wire and the lower electrode.
7. A semiconductor device according to claim 6, wherein
the upper electrode includes a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
8. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode which were formed in a portion over a lower electrode and the lower electrode;
wherein the upper electrode is a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
9. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a laminated structure of a TMR film layer and an upper electrode layer which were formed over a lower electrode layer and the lower electrode layer over a semiconductor substrate;
(b) patterning the upper electrode layer and the TMR film layer;
(c) forming a first antioxidant film covering the lower electrode layer, the upper electrode, and the TMR film;
(d) patterning the first antioxidant film and the lower electrode layer after the first antioxidant film has covered the upper electrode and the TMR film; and
(e) forming an oxide film in a whole surface.
10. A method of manufacturing a semiconductor device, further comprising a step of:
(f) performing after the step (d) and before the step (e), and forming a second antioxidant film covering the first antioxidant film and the lower electrode;
wherein the step (e) includes a step which forms an oxide film all over the second antioxidant film being included.
11. A method of manufacturing a semiconductor device according to claim 9, wherein
the step (a) comprises the steps of:
(a-1) forming a read wire over the semiconductor substrate;
(a-2) forming an interlayer insulation film over the read wire;
(a-3) forming a via hole, penetrating the interlayer insulation film over the read wire;
(a-4) forming a metal plug embedding the via hole; and
(a-5) forming the laminated structure over the interlayer insulation film including the via hole;

wherein
the lower electrode in the laminated structure is electrically connected with the read wire via the metal plug; and
at the step (b), the TMR film after patterning is formed separating a predetermined distance from the read wire in plan view.
12. A method of manufacturing a semiconductor device according to claim 9, wherein
the upper electrode includes an electrode which was formed using the same material as the lower electrode and whose thickness is 30-100 nm; and
the step (b) comprises the steps of:
(b-1) patterning the upper electrode layer; and
(b-2) patterning the TMR film layer using the upper electrode as a hard mask layer.
13. A method of manufacturing a semiconductor device according to claim 9, wherein
the antioxidant film includes a silicon nitride film formed below or equal to 300\xb0 C.
14. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a read wire over a semiconductor substrate;
(b) forming an interlayer insulation film over the read wire;
(c) forming a via hole, penetrating the interlayer insulation film over the read wire;
(d) forming a metal plug, embedding the via hole; and
(e) forming a laminated structure of a lower electrode, a TMR film, and an upper electrode over the interlayer insulation film comprising the via hole;
wherein
the lower electrode is electrically connected with the read wire via the metal plug, and further comprising a step of:
(f) patterning the upper electrode layer and the TMR film layer;
wherein
the TMR film after patterning is formed, separating a predetermined distance in plan view from the read wire.
15. A method of manufacturing a semiconductor device according to claim 14, wherein
the upper electrode includes an electrode whose thickness is 30-100 nm formed using the same material as the lower electrode; and
the step (f) comprises the steps of:
(f-1) patterning the upper electrode layer; and
(f-2) patterning the TMR film layer using the upper electrode as a hard mask layer.
16. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a laminated structure of a lower electrode layer, a TMR film layer, and an upper electrode layer over a semiconductor substrate;
(b) patterning the upper electrode layer; and
(c) patterning the TMR film layer using the upper electrode as a hard mask layer.
17. A semiconductor device, comprising:
a first interlayer insulation film formed above a semiconductor substrate;
a lower layer wiring which penetrates the first interlayer insulation film and is formed selectively; and
a second interlayer insulation film formed over the first interlayer insulation film including the lower layer wiring;
wherein the second interlayer insulation film has a via hole where at least a part of the lower layer wiring constitutes a bottom; and further comprising a lower electrode formed at a bottom and a side surface of the via hole, and over the second interlayer insulation film; wherein the lower electrode is electrically connected with the lower layer wiring via the via hole; and further comprising a TMR element which is formed selectively over a portion over the lower electrode, and includes a laminated structure of a TMR film and an upper electrode; and an insulating film formed over the lower electrode comprising an inside of the via hole; wherein both the insulating film and the lower electrode have a side surface over the second interlayer insulation film in a uniform direction; and a side surface of the lower electrode corresponds in an uniform direction to a side surface of the insulating film, or a side surface of the lower electrode is depressed from the insulating film.
18. A semiconductor device according to claim 17, wherein
the insulating film includes a low-temperature insulation film formed at a low temperature less than or equal to 300\xb0 C.
19. A semiconductor device according to claim 17, wherein
the insulating film is formed over a whole surface over the lower electrode over the second interlayer insulation film.
20. A semiconductor device according to claim 17, wherein
a side surface of the lower electrode is formed to correspond to a side surface of the insulating film in the uniform direction.
21. A semiconductor device according to claim 17, wherein
the semiconductor device has a first and a second TMR formation areas; and the TMR element, the lower electrode, and the insulating film are formed in each of the first and the second TMR formation areas; and further comprising a third interlayer insulation film formed over a whole surface over the second interlayer insulation film comprising the first and the second TMR formation areas; wherein insulated separation of a lower electrode of the first and the second TMR formation area is mutually done with the third interlayer insulation film directly formed over the second interlayer insulation film; and as for the second and third interlayer insulation film, in an interface and its neighboring region, chemical species are formed with the same material at least.
22. A semiconductor device according to claim 21, wherein
the second and third interlayer insulation film is formed by the manufacturing process of the same contents.
23. A semiconductor device according to claim 22, wherein
the second and third interlayer insulation film is formed in an interface and its neighborhood by a low-temperature insulation film formed at a low temperature less than 300\xb0 C. at least.
24. A semiconductor device according to claim 17, wherein
the semiconductor device has a first and a second TMR formation areas;
the TMR element includes a first and a second TMR elements formed in the first and second TMR formation area;
the insulating film includes a first and a second insulation films formed in the first and second TMR formation area, and the first and second insulation film has a side surface which separates a first gap and faces mutually;
the lower electrode includes a first and a second lower electrodes formed in the first and the second TMR formation areas, and the first and second lower electrode has a side surface which separates a second gap and faces mutually; and
the first insulation film and the first lower electrode make a direction which goes to the second TMR formation area from the first TMR formation area the uniform direction, and the second insulation film and the second lower electrode make a direction which goes to the first TMR formation area from the second TMR formation area the uniform direction; and further comprising a third interlayer insulation film formed over a whole surface over the second interlayer insulation film comprising the first and second TMR formation area; wherein by being formed between the first and second lower electrodes, the third interlayer insulation film does insulated separation of the first and second lower electrode; and
a side surface of the first and second lower electrode is formed to be depressed to a side surface of the first and second insulation film in the uniform direction; and further comprising an end portion oxidization region which adjoins a side surface of the first and the second lower electrode, and is formed in the first and second insulating film lower part.
25. A semiconductor device according to claim 24, wherein
the first and second lower electrode includes a metallic material with which it is a high melting point, and an oxide has insulation.
26. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a first interlayer insulation film above a semiconductor substrate;
(b) forming a lower layer wiring selectively, penetrating the first interlayer insulation film;
(c) forming a second interlayer insulation film over the first interlayer insulation film including the lower layer wiring; and
(d) forming a via hole, penetrating the second interlayer insulation film over the lower layer wiring;
wherein a bottom of the via hole becomes at least a part of the lower layer wiring; and further comprising the steps of:
(e) forming a lower electrode over a bottom and a side surface of the via hole, and the first interlayer insulation film;
wherein the lower electrode is electrically connected with the lower layer wiring via the via hole; and further comprising the steps of;
(f) forming selectively a TMR element used as a laminated structure of a TMR film and an upper electrode over the lower electrode over the second interlayer insulation film;
(g) forming an insulating film over the lower electrode comprising the via hole;
(h) forming a resist patterned over the insulating film;
(i) etching the lower electrode and the insulating film by using the resist as a mask, and patterns the lower electrode and the insulating film; and
(j) removing the resist.
27. A method of manufacturing a semiconductor device according to claim 26, wherein
the insulating film includes a low-temperature insulation film; and
the step (g) includes a step which forms the insulating film at a low temperature less than or equal to 300\xb0 C.
28. A method of manufacturing a semiconductor device according to claim 26, wherein
the step (j) includes at least one processing of ashing treatment and a wet cleaning treatment.
29. A method of manufacturing a semiconductor device according to claim 26, wherein
the semiconductor device has the first and second TMR formation area;
the TMR element includes a first and second TMR element formed in the first and second TMR formation area;
the insulating film includes a first and second insulation film formed in the first and second TMR formation area, and the first and second insulation film has a side surface which separates a prescribed interval and faces mutually after the step (i) execution;
the lower electrode includes a first and second lower electrode formed in the first and second TMR formation area, and the first and second lower electrode has a side surface which separates the prescribed interval and faces mutually after the step (i) execution; and
the step (j) includes ashing treatment, and by oxidizing in part from a side surface of the first and second lower electrode by the ashing treatment, a first and second end portion oxidization region is formed.
30. A method of manufacturing a semiconductor device according to claim 26, wherein
the semiconductor device includes an element formation region in which the TMR element is formed, and a peripheral region in which the TMR element is not formed;
the second interlayer insulation film includes a first partial interlayer insulation film, and a second partial interlayer insulation film formed over the first partial interlayer insulation film; and
the insulating film is formed with material with comparable thickness and the same chemical species as the second partial interlayer insulation film; and further comprising the steps of:
(k) forming a third interlayer insulation film all over performing after the step (j) and including the element formation region and the peripheral region;
(l) forming a partial via hole for periphery which penetrates the third interlayer insulation film and the second partial interlayer insulation film in the peripheral region at the same time of forming a partial via hole for TMR which penetrates the third interlayer insulation film in the element formation region; and
(m) forming a via hole for periphery which makes the first partial interlayer insulation film penetrate from the partial via hole for periphery in the peripheral region while making the insulating film penetrate furthermore from the partial via hole for TMR and forming the via hole for TMR in the element formation region; wherein
the third interlayer insulation film is formed with a material with which the insulating film, and the second partial interlayer insulation film differ from chemical species, and are formed with the same material as the second partial interlayer insulation film in chemical species.

1. An image processing device for performing a process using a first image or a front image obtained based on an image for an object photographed with a first camera and a second image based on an image photographed with a second camera arranged so at to photograph the object from a direction different from the direction photographed with the first camera; the image processing device comprising:
a setting means for a user to perform a setting on a specified region using a setting image or the front image obtained based on the image for a setting object photographed with the first camera;
a position specifying means for defining a specified region based on the setting with respect to the first image or the front image obtained based on the image for an object to be measured photographed with the first camera and specifying a position on the object within the specified region; and
a three dimensional measurement means for specifying a position on the second image corresponding to the position specified on the first image and calculating a three dimensional coordinate using the specified position on the first image and the position on the second image.
2. The image processing device according to claim 1, further comprising a conversion means for performing a conversion calculation of converting a slant image photographed with the first camera arranged so as to photograph the object from a slanted direction to the front image; wherein
the setting image is obtained by converting the image for a setting image photographed with the first camera in a slanted direction with the conversion means; and
the first image is obtained by converting the image for the object to be measured photographed with the first camera in the slanted direction with the conversion means.
3. The image processing device according to claim 2, wherein the scale information for associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured, a value of scale reference height or a front height consistent with the scale information, and a value of the allowable range of the front height defined so as to include the scale reference height are available; and the image processing device further comprises:
a two dimensional image processing means for performing two dimensional image process on the first image using the scale information; and
a determining means for determining whether or not the front height indicated by the three dimensional coordinate calculated by the three dimensional means is within the allowable range.
4. The image processing device according to claim 2, further comprising:
a scale information calculating means for calculating scale information associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured using the front height indicated by the three dimensional coordinate calculated by the three dimensional measurement means; and
a two dimensional image processing means for performing the two dimensional image process on the first image using the scale information.
5. The image processing device according to claim 2, wherein scale information for associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured, and a value of scale reference height or a front height consistent with the scale information are available; and the image processing device further comprises:
an adjustment means for coherently changing the scale reference height and the scale information based on the operation of the user.
6. The image processing device according to claim 5, further including an image editing means for editing the display image with a scale figure indicating the actual dimension in a plane at a scale reference height with respect to the first image.
7. An image processing device for performing a process using a first image or a front image obtained based on an image for an object photographed with a first camera in a slanted direction and a second image based on an image photographed with a second camera arranged so as to photograph the object from a direction different from the direction photographed with the second camera; the image processing device comprising:
a conversion means for performing a conversion calculation for converting a slant image photographed with the first camera arranged to photograph the object from a slanted direction to the front image;
a setting means for the user to perform a setting on a position to be measured using a setting image obtained by converting the image obtained for a setting image photographed with the first camera;
a position specifying means for specifying a position on the object based on the setting in the first image obtained by converting the image obtained for object to be measured photographed the with the camera with the conversion means; and
a three dimensional measurement means for specifying a position in the second image corresponding to the position specified on the first image and calculating a three dimensional coordinate using the specified position on the first image and the position on the second image.
8. The image processing device according to claim 7, wherein the scale information for associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured, a value of scale reference height or a front height consistent with the scale information, and a value of the allowable range of the front height defined so as to include the scale reference height are available; and the image processing device further comprises:
a two dimensional image processing means for performing two dimensional image process on the first image using the scale information; and
a determining means for determining whether or not the front height indicated by the three dimensional coordinate calculated by the three dimensional means is within the allowable range.
9. The image processing device according to claim 7, further comprising:
a scale information calculating means for calculating the scale information associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured using the front height indicated by the three dimensional coordinate calculated by the three dimensional measurement means; and
a two dimensional image processing means for performing the two dimensional image process on the first image using the scale information.
10. The image processing device according to claim 7, wherein the scale information for associating the dimension in the front image converted by the conversion means and the actual dimension of the location to be measured, and the value of scale reference height or a front height consistent with the scale information are available; and the image processing device further comprises:
an adjustment means for coherently changing the scale reference height and the scale information based on the operation of the user.
11. The image processing device according to claim 10, further including an image editing means for editing the display image with a scale figure indicating the actual dimension in a plane at a scale reference height with respect to the first image.
12. An image processing method for performing a process using a first image of a front image obtained based on an image for an object photographed with a first camera and a second image based on an image photographed with a second camera arranged so at to photograph the object from a direction different from the direction photographed with the first camera; the image processing method comprising:
setting step of displaying a setting image of a front image obtained based on the image for a setting object photographed with the first camera, and having a user perform a setting for a specified region using the setting image;
position specifying step of defining a specified region based on the setting with respect to the first image of the front image obtained based on the image for an object to be measured photographed with the first camera and specifying a position on the object within the specified region; and
three dimensional measurement step of specifying a position on the second image corresponding to the position specified on the first image and calculating a three dimensional coordinate using the specified position on the first image and the position on the second image.
13. An image processing method for performing a process using a first image or a front image obtained based on an image for an object photographed with a first camera arranged so as to photograph the object in a slanted direction and a second image based on an image photographed with a second camera arranged so at to photograph the object from a direction different from the direction photographed with the first camera; the image processing method comprising:
setting step of converting the image for a setting image photographed with the first camera to a setting image through a conversion calculation of converting a slant image photographed with the first camera to the front image, and having a user perform a setting on a position to be measured using the setting image;
position specifying step of converting the image for the object to be measured photographed with the first camera to a first image through the conversion calculation and specifying the position on the object based on the setting on the first image; and
three dimensional measurement step of specifying a position on the second image corresponding to the position specified on the first image and calculating a three dimensional coordinate using the specified position on the first image and the position on the second image.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory device comprising:
a memory array;
a test circuit suitable for detecting a first repair address corresponding to a defective cell in the memory array, in a test mode;
an external input circuit suitable for receiving a second repair address from an exterior, in response to an address input command, in an external input mode; and
a nonvolatile memory circuit including a first region and a second region, and suitable for programming the first repair address in the first region in response to a first program command in the test mode, and programming the second repair address in the second region in response to a second program command in the external input mode, wherein the first repair address is programmed in the second region in response to the second program command while the address input command is deactivated in the external input mode.
2. The memory device according to claim 1, wherein the test circuit writes the same data in two or more memory cells in the memory array, and detects a defective cell of the two or more memory cells by determining whether data read from the two or more memory cells is the same.
3. The memory device according to claim 1, wherein the external input mode is a post package repair (PPR) mode, and the address input command is an active command.
4. The memory device according to claim wherein the external input circuit comprises:
a latch suitable for temporarily storing the second repair address in response to the active command in the external input mode; and
a control unit suitable for generating the second program command in response to an activation of a write command and a logic level of an entirety or a part of data inputted from the exterior, in the external input mode.
5. The memory device according to claim 4, wherein the control unit determines whether to activate the second program command, by checking if a first value of data is inputted to a 0th data pad a predetermined time after the write command is activated in the external input mode.
6. The memory device according to claim further comprising:
a selection unit suitable for transmitting the first repair address to the nonvolatile memory circuit in the test mode, and transmitting the first repair address to the nonvolatile memory circuit before the address input command is activated and the second repair address to the nonvolatile memory circuit after the address input command activated, in the external input mode.
7. An operation method of a memory device, comprising:
detecting a first defective cell through a test operation, and programming a first repair address corresponding to the first defective cell in a first region of a nonvolatile memory in response to a first program command, in a test mode;
receiving a second repair address in response to an address input command, and programming the second repair address in a second region of the nonvolatile memory in response to a second program command, in an external input mode; and
detecting a second defective cell through the test operation in the test mode, and programming a third repair address corresponding to the second defective cell in the second region of the nonvolatile memory in response to the second program command in the external input mode.
8. The operation method according to claim 7, wherein the detecting of the first defective cell and the programming of the first repair address comprises:
entering the test mode;
detecting the first defective cell through the test operation;
temporarily storing the first repair address corresponding to the first defective cell; and
programming the first repair address in the first region of the nonvolatile memory in response to the first program command.
9. The operation method according to claim 8, wherein the receiving of the second repair address and the programming of the second repair address comprises:
entering the external input mode;
temporarily storing the second repair address which is inputted together with the address input command; and
programming the second repair address in the second region of the nonvolatile memory in response to the second program command.
10. The operation method according to claim 8, wherein the detecting of the second defective cell and the programming of the third repair address comprises:
entering the test mode;
detecting the second defective cell through the test operation;
temporarily storing the third repair address corresponding to the second defective cell;
exiting the test mode, and entering the external input mode; and
programming the third repair address in the second region of the nonvolatile memory in response to the second program command.
11. The operation method according to claim 10, wherein the external input mode is a post package repair (PPR) mode.
12. The operation method according to claim 11, wherein the programming of the third repair address in the second region of the nonvolatile memory in response to the second program command comprises:
checking application of a write command;
generating the second program command by checking a logic level of an entirety or a part of data inputted from an exterior a predetermined time after the application of the write command; and
programming the third repair address in the second region in response to the second program command generated in the generating.