Author: claimsbot

1. A printing apparatus, comprising:
a reading unit adapted to read a document image;
an extraction unit adapted to extract application data from the document image read by said reading unit;
a first determination unit adapted to determine whether a license to direct-print the application data extracted by said extraction unit is permitted;
a second determination unit adapted to determine, if it is determined by said first determination unit that a license to direct-print the application data extracted by said extraction unit is not permitted, whether a temporary licensing key is recorded in the document image read by said reading unit; and
a processing unit is adapted to,
a) if it is determined by said first determination unit that a license to direct-print the application data extracted by said extraction unit is permitted, analyze the application data extracted by said extraction unit and generate bitmap data,
b) if it is determined by said second determination unit that the temporary licensing key is recorded in the document image read by said reading unit, temporarily permit a license to direct-print, analyze the application data extracted by said extraction unit, generate bitmap data, print the bitmap data and return the temporarily permitted license to direct-print to original state.
2. The apparatus according to claim 1, wherein the processing unit,
if it is determined by the first determination unit that a license to direct-print the application data extracted by said extraction unit is permitted, analyzes the application data extracted by said extraction unit, generates bitmap data, and counts up a charging counter;
if it is determined by the second determination unit that the temporary licensing key is recorded in the document image read by said reading unit, temporally permits a license to direct-print, analyzes the application data extracted by said extraction unit, generates bitmap data, prints the bitmap data, counts up a licensing charging counter, and returns the temporarily permitted license to direct-print to original state; and
if it is determined by the second determination unit that the temporary licensing key is not recorded in the document image read by said reading unit, displays an error notification window.
3. A control method for printing apparatus, comprising,
a reading step of reading a document image;
an extraction step of extracting application data from the document image read in said reading step;
a first determination step of determining whether a license to direct-print the application data extracted in said extraction step is permitted;
a second determination step of determining, if it is determined in said first determination step that a license to direct-print the application data extracted in said extraction step is not permitted, whether a temporary licensing key is recorded in the document image read in said reading step; and
a processing step of,
a) if it is determined in said first determination step that a license to direct-print the application data extracted in said extraction step is permitted, analyzing the application data extracted in said extraction step and generating bitmap data,
b) if it is determined in said second determination step that the temporary licensing key is recorded in the document image read in said reading step, temporarily permitting a license to direct-print, analyzing the application data extracted in said extraction step, generating bitmap data, print the bitmap data and returning the temporarily permitted license to direct-print to original state.
4. The method according to claim 3, wherein the processing step,
if it is determined in the first determination step that a license to direct-print the application data in said extraction step is permitted, analyzes the application data extracted in said extraction step, generates bitmap data, counts up a charging counter;
if it is determined in the second determination step that the temporary licensing key is recorded in the document image read in said reading step, temporally permits a license to direct-print, analyzes the application data extracted in said extraction step, generates bitmap data, prints the bitmap, counts up a licensing charging counter, and returns the temporarily permitted license to direct-print to original state; and
if it is determined in the second determination step that the temporary licensing key is not recorded in the document image read in said reading step, displays an error notification window.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that outputs a selected one of a reset pulse and a set pulse in response to a logic level of data and the data;
a current control circuit that receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and
a current drive circuit that outputs writing current to the phase-change memory array in response to the control signal during the enable duration of the reset pulse or of the set pulse.
2. The writing driver circuit of claim 1, wherein at least one of the first level and the second level of the control signal increases or decreases in response to a change of the bias voltage.
3. The writing driver circuit of claim 1, wherein the enable duration of the reset pulse is shorter than the enable duration of the set pulse.
4. The writing driver circuit of claim 1, wherein a level of the writing current when the reset pulse is selected in the pulse selection circuit is higher than a level of the writing current when the set pulse is selected in the pulse selection circuit.
5. The writing driver circuit of claim 1, wherein the pulse selection circuit includes:
a first transmitter, which passes the reset pulse in response to the first logic level of the data;
a second transmitter, which passes the set pulse in response to the second logic level of the data;
a buffer that buffers the data and outputs the buffered data to the current control circuit; and
a first inverter that inverts an output of the first transmitter or the second transmitter and applies the inverted output to the current drive circuit.
6. The writing driver circuit of claim 5, wherein the first transmitter and the second transmitter include transmission gates which are turned on or off in response to the data and the inverted data, and wherein when either of the first transmitter and the second transmitter is turned on, the other transmitter is turned off.
7. The writing driver circuit of claim 6, wherein the buffer includes:
a second inverter which inverts the data to generate the inverted data; and
a third inverter which inverts the inverted data and outputs the data to the current control circuit.
8. The writing driver circuit of claim 1, wherein the current control circuit includes:
a first level controller which is turned on in response to the bias voltage and controls the level of the control signal to be generated at the first level during an enable duration of the set pulse;
a second level controller, which controls the level of the control signal to be generated at the second level in during an enable duration of the reset pulse;
a first control transistor which activates the current control circuit in response to the reset pulse or the set pulse; and
a second control transistor which turns deactivates the current control circuit and outputs the control signal at a third level during the disable duration of the reset pulse or the set pulse.
9. The writing driver circuit of claim 8, wherein the first level controller includes a first level transistor and a second level transistor which are connected in series between a drain of a first transistor and the drain of the first control transistor, the bias voltage being applied to gates of the first level transistor and the second level transistor, and the second level controller includes a third level transistor and a fourth level transistor which are connected in series between the drain of the first transistor and the drain of the first control transistor, the data being applied to gates of the third level transistor and the fourth level transistor.
10. The writing driver circuit of claim 9, wherein the first control transistor has a drain commonly connected to sources of the second and fourth level transistors, a source connected to a second voltage, and a gate to which the reset pulse or the set pulse is applied, and the second control transistor has a source connected to a first voltage, a drain connected to the drain of the first transistor, and a gate to which the reset pulse or the set pulse is applied.
11. The writing driver circuit of claim 9, wherein the current drive circuit includes:
a pull up transistor having a source connected to the first voltage, a drain connected to the first node, and a gate to which the control signal is applied; and
a pull down transistor having a drain connected to the first node, a source connected to the second voltage, and a gate to which an inverted reset pulse or an inverted set pulse is applied.
12. The writing driver circuit of claim 11, wherein the second level of the control signal is a voltage level which turns on the pull up transistor more than the first level of the control signal, and the third level of the control signal is a voltage level which turns off the pull up transistor.
13. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that outputs a selected one of a reset pulse and a set pulse in response to a logic level of data;
a current control circuit that receives a bias voltage, the data and the selected one of a reset pulse and a set pulse, and outputs a control signal at a second level when the data is at a first level during an enable duration of the reset pulse , and outputs a control signal at a first level when the data is at a second level during an enable duration of the set pulse, and outputs a control signal at a third level during a disable duration of the reset pulse or the set pulse; and
a current drive circuit that outputs writing current at a first level or a second level to the phase-change memory array during an enable duration of the reset pulse or the set pulse respectively.
14. The writing driver circuit of claim 12, wherein the level of the at least one of the first level and the second level of the control signal increases or decreases in response to a change of the bias voltage.
15. The writing driver circuit of claim 12, wherein the first level of the writing current is higher than the second level of the writing current.
16. The writing driver circuit of claim 12, wherein the pulse selection circuit includes:
a first transmitter which passes the reset pulse in response to a logic level of the data;
a second transmitter which passes the set pulse in response to a logic level of the data.
17. The writing driver circuit of claim 16, wherein the first transmitter and the second transmitter include transmission gates which are turned on or off in response to the data, and wherein when either of the first transmitter and the second transmitter is turned on, the other transmitter is turned off.
18. The writing driver circuit of claim 13, wherein the current drive circuit includes:
a second level controller which outputs the writing current at a first level through a first node in response to the control signal during the enable duration of the reset pulse when the inverted data is at a second level;
a pull up transistor which outputs the writing current at a second level through the first node in response to the control signal during the enable duration of the set pulse when the inverted data is at a first level; and
a pull down transistor which discharges the first node during the disable duration of the reset pulse or the set pulse irrespective of a logic level of the data.
19. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that receives a reset pulse and a set pulse and outputs a selected one of the reset pulse and the set pulse in response to the logic level of data;
a current drive circuit that outputs writing current at a first level or a second level to the phase-change memory array during an enable duration of the reset pulse or the set pulse respectively.
20. The writing driver circuit of claim 19, wherein the current drive circuit includes a first pull-up transistor and a second pull-up transistor connected in parallel between a first voltage and a first node; and wherein
the current drive circuit outputs writing current at the first level when the first pull-up transistor is activated during an enable duration of the reset pulse; and wherein
the current drive circuit outputs writing current at the second level when the first pull-up transistor and the second pull-up transistor are activated during an enable duration of the set pulse.

1. A microprocessor, comprising:
a plurality of reservation stations for storing a basic block of instructions to be executed by at least one execution unit included therein; and
means for providing any of said instructions in said basic blocks to any of said at least one execution units.
2. A microprocessor according to claim 1, further comprising a scheduler, included in each of said plurality of reservation stations, for outputting said instructions in a corresponding one of said basic blocks to one of said at least one execution units when any dependencies affecting said instructions are resolved.
3. A microprocessor according to claim 2 wherein said scheduler comprises means for determining when said dependencies are resolved for those of said instructions in said basic block.
4. A microprocessor according to claim 3 wherein each said scheduler comprises an arbiter for obtaining access to any one of said execution units, when said dependencies are resolved, in accordance with the type of said instruction.
5. A microprocessor according to claim 4 further comprising an instruction cache for storing said instructions prior to their input to said reservation stations.
6. A microprocessor according to claim 5 further comprising a second scheduler, associated with said instruction cache for determining when said dependencies are resolved for those of said instructions in said instruction cache, and for providing said instructions having resolved dependencies to one of said plurality of execution units without storing said instruction in one of said plurality or reservation stations.
7. A microprocessor according to claim 6 wherein at least one of said instructions from a first basic block is provided to a first one of said plurality of execution units concurrently with the provision of at least one other of said instructions from a second basic block to a second one of said plurality of execution units.
8. A microprocessor according to claim 7 wherein said dependencies include at least one of control dependencies, data dependencies and resource dependencies.
9. A method of executing instructions on a microprocessor included in a data processing system, comprising the steps of:
generating basic blocks of said instructions;
storing said basic blocks of said instructions in one of a plurality of reservation stations;
scheduling said instructions for execution on said microprocessor in accordance with a resolution of dependencies affecting said instructions; and
transferring any of said instructions in any of said plurality of basic blocks to any one of at least one execution units included in said microprocessor when said dependencies are resolved.
10. A method according to claim 9 wherein said step of scheduling comprises the step of determining when said dependencies are resolved for those of said instructions in said basic block.
11. A method according to claim 10 wherein said step of scheduling further comprises the step of arbitrating for access to any one of said execution units when said dependencies are resolved in accordance with the type of said instruction.
12. A method according to claim 11 further comprising the step of determining, by a second scheduler associated with said instruction cache, when said dependencies are resolved for those of said instructions in said instruction cache, and for providing said instructions having resolved dependencies to one of said plurality of execution units without storing said instruction in one of said plurality or reservation stations.
13. A method according to claim 12 wherein at least one of said instructions from a first basic block is provided to a first one of said plurality of execution units concurrently with the provision of at least one other of said instructions from a second basic block to a second one of said plurality of execution units.
14. A method according to claim 13 wherein said dependencies include at least one of control dependencies, data dependencies and resource dependencies.
15. A data processing system comprising:
a main memory for storing microprocessor instructions to be executed on a microprocessor in said data processing system;
cache memory for storing said microprocessor instructions in said microprocessor;
a branch prediction circuit for predicting an outcome of any branch instructions in said microprocessor instructions, and for generating basic blocks of microprocessor instructions in accordance with said branch instructions;
a plurality of reservation stations for storing said basic blocks of microprocessor instructions prior to being executed;
a first bus for providing said basic blocks of microprocessor instructions to one of said plurality of reservation stations;
a scheduler for scheduling an output of each of said microprocessor instructions from one of said plurality of reservation stations based on resolution of any dependencies affecting said microprocessor instructions; and
a second bus for providing said microprocessor instructions from any of said plurality of reservation stations to any of at least one execution unit included in said microprocessor.
16. A data processing system according to claim 15 wherein one said scheduler is provided in each of said reservation stations and comprises means for determining when said dependencies are resolved for those of said instructions in said basic block.
17. A data processing system according to claim 16 wherein each said scheduler comprises an arbiter for obtaining access to any one of said execution units when said dependencies are resolved in accordance with the type of said instruction.
18. A data processing system according to claim 17 further comprising a second scheduler, associated with said instruction cache for determining when said dependencies are resolved for those of said instructions in said instruction cache, and for providing said instructions having resolved dependencies to one of said plurality of execution units without storing said instruction in one of said plurality or reservation stations.
19. A data processing system according to claim 19 wherein at least one of said instructions from a first basic block is provided to a first one of said plurality of execution units concurrently with the provision of at least one other of said instructions from a second basic block to a second one of said plurality of execution units.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A memory system that receives an external supply voltage from a host, said memory system comprising:
a plurality of memory blocks, each of said memory blocks including at least a plurality of data storage elements; and
a memory controller operatively coupled to said memory blocks and operatively coupled to receive the external supply voltage when said memory system is operatively connected to the host, said memory controller including at least a voltage generation circuit operable to produce at least a first and second supply voltages for use by each of said memory blocks.
2. A memory system as recited in claim 1, wherein said memory system further comprises:
a power bus coupled to each of said memory blocks, said power bus supplying at least the first and supply voltages between said memory blocks.
3. A memory system as recited in claim 1, wherein said memory blocks do not include voltage generation circuitry to internally generate any supply voltages.
4. A memory system as recited in claim 1, wherein said data storage elements provide non-volatile data storage.
5. A memory system as recited in claim 4, wherein said data storage elements provide semiconductor-based data storage.
6. A memory system as recited in claim 5, wherein said data storage elements are EEPROM or FLASH.
7. A memory system as recited in claim 4, wherein each of said data storage elements comprise at least one floating-gate storage device.
8. A memory system as recited in claim 1, wherein said memory system is a memory card.
9. A memory system as recited in claim 1, wherein said memory system is provided within a single package.
10. A memory system as recited in claim 9, wherein the single package is a memory card.
11. A memory system as recited in claim 1, wherein said memory system is a removable data storage product.
12. A memory system as recited in claim 1, wherein the host is a computing device.
13. A memory system as recited in claim 1, wherein said memory system removably couples to the host.
14. A memory system as recited in claim 1, wherein said power bus supplies at least the first supply voltage to each of said memory blocks.
15. A memory system as recited in claim 1, wherein said voltage generation circuit produces the first supply voltage and a second supply voltage, and
wherein said power bus supplies the first supply voltage and the second supply voltage between said memory blocks.
16. A memory system as recited in claim 1, wherein the voltage generation circuit is a voltage regulator.
17. A memory system that receives an external supply voltage from a host, said memory system comprising:
a plurality of memory blocks, each of said memory blocks including at least a plurality of data storage elements, at least one of said memory blocks further including at least a first voltage generation circuit operable to produce at least one memory-generated supply voltage;
a memory controller operatively coupled to said memory blocks and operatively coupled to receive the external supply voltage when said memory system is operatively connected to the host, said memory controller including at least a second voltage generation circuit operable to produce at least one controller-generated supply voltage; and
a power bus coupled to each of said memory blocks, said power bus supplying the at least one memory-generated supply voltage between said memory blocks.
18. A memory system as recited in claim 17, wherein said power bus further supplies the at least one controller-generated supply voltage between said memory blocks.
19. A memory system as recited in claim 17, wherein said memory system further comprises:
an InputOutput (IO) bus operatively coupling between said memory controller and each of said memory blocks.
20. A memory system as recited in claim 17, wherein, when said memory system is operatively connected to the host, the external supply voltage is supplied to the at least one of said memory blocks that includes at least said first voltage generation circuit.
21. A memory system as recited in claim 20, wherein said first voltage generation circuit receives the external supply voltage when said memory system is operatively connected to the host, and the external supply voltage is used by said first voltage generation circuit to generate the at least one memory-generated supply voltage.
22. A memory system as recited in claim 17, wherein said memory system further comprises a link that couples said memory controller to the at least one of said memory blocks, the link carrying the at least one controller-generated supply voltage from said memory controller to the at least one of said memory blocks.
23. A memory system as recited in claim 17, wherein said first voltage generation circuit is a voltage regulation circuit, and wherein said second voltage generation circuit is a charge pump and regulation circuit.
24. A memory system as recited in claim 17, wherein said memory blocks other than the at least one of said memory blocks do not include voltage generation circuitry to internally generate any supply voltages.
25. A memory system as recited in claim 17, wherein said data storage elements provide non-volatile data storage.
26. A memory system as recited in claim 17, wherein said memory system is a memory card.
27. A memory system as recited in claim 26, wherein said memory system is provided within a single package.
28. A memory system as recited in claim 17, wherein said memory system is a removable data storage product.
29. A memory system as recited in claim 17, wherein the host is a computing device, and wherein said memory system removably couples to the host.
30. A memory system as recited in claim 17,
wherein said voltage generation circuit produces a plurality of memory-generated supply voltages, one of the memory-generated supply voltages being the at least one memory-generated supply voltage, and
wherein said power bus supplies the plurality of memory-generated supply voltages between said memory blocks.
31. A memory system as recited in claim 17, wherein at least another of said memory blocks further includes at least a voltage generation circuit operable to produce the at least one memory-generated supply voltage.
32. A memory system that receives an external supply voltage from a host, said memory system comprising:
a plurality of memory blocks, each of said memory blocks including at least a plurality of data storage elements, at least one of said memory blocks further including at least a first voltage generation circuit operable to produce at least one memory-generated supply voltage;
a memory controller operatively coupled to access said memory blocks; and
a power bus coupled to each of said memory blocks, said power bus supplying the at least one memory-generated supply voltage between said memory blocks.
33. A memory system as recited in claim 32, wherein, when said memory system is operatively connected to the host, the external supply voltage is supplied to the at least one of said memory blocks that includes at least said first voltage generation circuit.
34. A memory system as recited in claim 33, wherein said memory system further comprises:
an InputOutput (IO) bus operatively coupling between said memory controller and each of said memory blocks.
35. A memory system as recited in claim 32, wherein at least another of said memory blocks further includes at least a voltage generation circuit operable to produce the at least one memory-generated supply voltage.
36. A memory system as recited in claim 32, wherein said memory system is a memory card.
37. A memory system as recited in claim 32,
wherein said voltage generation circuit produces a plurality of memory-generated supply voltages, one of the memory-generated supply voltages being the at least one memory-generated supply voltage, and
wherein said power bus supplies the plurality of memory-generated supply voltages between said memory blocks.
38. A memory system as recited in claim 37, wherein at least one of the plurality of memory-generated supply voltages is supplied to said memory controller.
39. A memory system as recited in claim 38, wherein said memory controller does not include any voltage generation circuitry for producing any supply voltages for use by any of said memory blocks.
40. A memory system as recited in claim 32,
wherein said memory system further comprises:
a voltage regulator separate from said memory controller and said memory blocks, said voltage regulator producing a regulator-generated supply voltage that is supplied to said power bus, and
wherein the regulator-generated supply voltage is supplied between said memory blocks via said power bus.
41. A data storage device that removably couples to a host unit, said data storage device comprising:
a memory controller;
a plurality of memory blocks operatively connected to said memory controller, each of said memory blocks including at least data storage elements; and
a power bus operatively supplying different level supply voltages between each of said memory blocks, the different level supply voltages being centrally generated by said memory controller or one of said memory blocks.
42. An electronic system, comprising:
a data acquisition device; and
a data storage device removably coupled to said data acquisition unit, said data storage device storing data acquired by said data acquisition device, and said data storage device including at least
a memory controller;
a plurality of memory blocks operatively connected to said memory controller, each of said memory blocks including at least data storage elements; and
a power bus operatively supplying different level supply voltages between each of said memory blocks, the different level supply voltages being centrally generated by one or both of said memory controller and one of said memory blocks.
43. An electronic system as recited in claim 42, wherein said data acquisition device is one of a camera, a network card or appliance, a hand-held or notebook computer, a set-top box, a hand-held or other small audio playerrecorder, and a medical monitor.