Author: claimsbot

1. A turbine system comprising:
a turbine casing;
a shroud block coupled to the turbine casing;
a fluid passage in the shroud block; and
a pin configured to interface with the fluid passage, the pin comprising:
a hollow shaft;
a rod inserted into the hollow shaft; and
a controlling feature disposed on the rod, wherein the controlling feature is configured to open and close the fluid passage when the rod is rotated about an axis of the rod and the hollow shaft.
2. The turbine system of claim 1, wherein the fluid passage is in fluid communication with a damping mechanism of the shroud block.
3. The turbine system of claim 2, wherein the damping mechanism comprises a spring.
4. The turbine system of claim 1, wherein the fluid passage is in fluid communication with a heat-resistant lining of the shroud block.
5. The turbine system of claim 1, wherein the fluid passage is configured to transfer cooling fluid to the shroud block.
6. The turbine system of claim 5, comprising an opening in the shroud block in fluid communication with the fluid passage, wherein the opening is configured to transfer cooling fluid when the valve is open.
7. The turbine system of claim 1, wherein the pin extends through both the shroud block and the turbine casing.
8. The turbine system of claim 1, wherein the controlling feature comprises a butterfly valve.
9. The turbine system of claim 1, wherein the controlling feature comprises a ball valve, or a piston valve.
10. A turbine system, comprising:
a stator component comprising a cooling fluid passage; and
an anti-rotation pin inserted mounted in a receptacle in the stator component, wherein the anti-rotation pin comprises:
a hollow shaft;
a rod inserted into the hollow shaft, wherein a distal end of the rod extends beyond the hollow shaft into the cooling fluid passage; and
a valve disposed on the distal end of the rod, wherein the valve is configured to open and close when the rod is rotated about an axis of the rod and the hollow shaft.
11. The turbine system of claim 10, wherein the stator component comprises a turbine shroud.
12. The turbine system of claim 10, wherein the stator component comprises a spring.
13. The turbine system of claim 10, wherein the pin supports the stator component in a circumferential direction.
14. An anti-rotation pin for a turbine system, comprising:
a hollow shaft;
a rod inserted into the hollow shaft; and
a valve disposed on a portion of the rod extending past the hollow shaft along an axis of the rod and the hollow shaft, wherein the valve is configured to be opened and closed when the rod is moved relative to the hollow shaft.
15. The anti-rotation pin of claim 14, wherein the valve is configured to be opened and closed when the rod is rotated about the axis of the rod and the hollow shaft.
16. The anti-rotation pin of claim 14, wherein the valve is configured to be opened and closed when the rod is moved in a direction along the axis of the rod and the hollow shaft.
17. The anti-rotation pin of claim 14, comprising a key configured to block rotation of the rod about the axis of the rod and the hollow shaft.
18. The anti-rotation pin of claim 17, wherein the key extends through a first passage in a first proximal end of the hollow shaft and a second passage in a second proximal end of the rod.
19. The anti-rotation pin of claim 14, wherein the key comprises a wire.
20. The anti-rotation pin of claim 14, comprising a removable seal between the hollow shaft and the rod.
21. The anti-rotation pin of claim 14, comprising interlocking surfaces between the hollow shaft and the rod.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor storage device comprising:
a plurality of bit lines;
a plurality of word lines;
at least one source line;
magnetic tunnel junction elements and transistors, each magnetic tunnel junction element and each transistor being serially connected between the respective bit lines and the source line;
a sense amplifier configured to detect data stored in the magnetic tunnel junction elements;
a multiplexer between the plural bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier; and
a plurality of write amplifiers corresponding to a plurality of memory cell blocks each including a plurality of memory cells each including one of the magnetic tunnel junction elements and one of the transistors, and connected to the bit lines or connected to the bit lines via the multiplexer, wherein
at data writing, the write amplifiers hold the write voltage after the sense amplifier applies a write voltage to the bit lines.
2. The device of claim 1, wherein in a data write operation, the sense amplifier performs a first writing step to write data to the write amplifiers, and the write amplifiers perform a second writing step to write the data to the memory cells in the memory cell block corresponding to the write amplifiers.
3. The device of claim 2, wherein in the second writing step, driving of the word lines is performed after end of a data write period and during a precharge period of the sense amplifier.
4. The device of claim 1 wherein
the multiplexer successively selects the bit lines and successively transmits write data from the sense amplifier to the bit lines at a time of data writing,
the write amplifiers respectively correspond to the bit lines, the write amplifiers are respectively connected between the bit lines and the source line, and the write amplifiers hold the write data transmitted to the bit lines at the time of data writing, and
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
5. The device of claim 2 wherein
the multiplexer successively selects the bit lines and successively transmits write data from the sense amplifier to the bit lines at a time of data writing,
the write amplifiers respectively correspond to the bit lines, the write amplifiers are respectively connected between the bit lines and the source line, and the write amplifiers hold the write data transmitted to the bit lines at the time of data writing, and
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
6. The device of claim 3 wherein
the multiplexer successively selects the bit lines and successively transmits write data from the sense amplifier to the bit lines at a time of data writing,
the write amplifiers respectively correspond to the bit lines, the write amplifiers are respectively connected between the bit lines and the source line, and the write amplifiers hold the write data transmitted to the bit lines at the time of data writing, and
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
7. The device of claim 1, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the pairs of the bit lines and hold write data transmitted to any one of bit lines of the corresponding bit line pair at a time of data writing,
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
8. The device of claim 2, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the pairs of the bit lines and hold write data transmitted to any one of bit lines of the corresponding bit line pair at a time of data writing,
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
9. The device of claim 3, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the pairs of the bit lines and hold write data transmitted to any one of bit lines of the corresponding bit line pair at a time of data writing,
by driving one of the word lines after writing to the write amplifiers ends, the write amplifiers write the write data to the memory cell connected to the driven word line.
10. The device of claim 7, wherein the write amplifiers are connected between the pair of the bit lines.
11. The device of claim 1, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the bit lines and hold write data transmitted to corresponding one of the bit lines at a time of data writing, and
by driving one of the word lines after writing of the write amplifiers ends, the write amplifiers write the write data to the memory cells connected to the driven word line.
12. The device of claim 2, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the bit lines and hold write data transmitted to corresponding one of the bit lines at a time of data writing, and
by driving one of the word lines after writing of the write amplifiers ends, the write amplifiers write the write data to the memory cells connected to the driven word line.
13. The device of claim 3, wherein
each pair of adjacent bit lines shares a source line,
the device further comprises short-circuit switches each connected between the bit line and the corresponding source line,
the write amplifiers respectively correspond to the bit lines and hold write data transmitted to corresponding one of the bit lines at a time of data writing, and
by driving one of the word lines after writing of the write amplifiers ends, the write amplifiers write the write data to the memory cells connected to the driven word line.
14. The device of claim 11, wherein the write amplifiers are connected between the bit lines and the multiplexer.
15. The device of claim 11, wherein in a data read operation, the write amplifiers disconnect the corresponding bit lines and a voltage supply regardless of voltage levels of the bit lines.
16. The device of claim 11, wherein in a data read operation, the write amplifiers connect the corresponding bit lines to a voltage supply to fix voltages of the bit lines when the bit lines are not selected, and disconnect the corresponding bit lines from the voltage supply when the bit lines are selected.
17. The device of claim 1, wherein
the write amplifiers are provided between the multiplexer and the sense amplifier, and
at data writing, after the sense amplifier applies a write voltage to the bit lines, the write amplifiers write data to the memory cells via bit lines selected by the multiplexer.
18. The device of claim 17, wherein the write amplifiers correspond to a plurality of the bit lines.
19. The device of claim 1, wherein the number of the write amplifiers is larger than the number of the sense amplifiers.

1. A toilet paper roll holder capacity extender comprising:
a telescopic roll spindle having a roller axis and opposite ends; and
a pair of thin, plastic extender links of oblong, smoothly rounded shape, each such link being permanently, non-rotatably attached to a respective end of said spindle and extending at right angles thereto, each link having an outwardly-extending cylindrical pin thereon non-coaxial with the spindle roller axis.
2. An extender as defined in claim 1 wherein one of side links is hinged.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for facilitating authentication of an entity engaging in an interaction with a financial institution, the authentication based on a record of interactions initiated by the entity, the method comprising:
receiving interaction requests over a network at a central authentication and interaction tracking system, the central authentication and interaction tracking system including at least one computer memory and at least one computer processor, the interaction requests originating from multiple entities and including a plurality of authentication factors;
executing instructions stored in the computer memory using the computer processor to perform steps including:
building, from each interaction request, an entity print record for each of the multiple entities, wherein each entity print record includes the authentication factors from each initiated interaction request, the authentication factors including a location of the interaction request, a device identifier, and personal identifiers;
deriving, from the entity print record, an entity print and storing the entity print in at least one computer memory;
building, from each interaction request, an interaction signature for each interaction and classifying each interaction signature as a valid interaction signature or a fraudulent interaction signature;
comparing the received authentication factors for a requested interaction with the entity print and comparing the interaction signature for a received interaction request with the classified interaction signatures, wherein the comparisons yield a level of risk for each transaction; and
making an authentication determination based on a level of risk resulting from the comparisons.
2. The method of claim 1, wherein deriving an entity print comprises deriving a level of confidence that the entity is authentic and a determining an entity risk level for the entity.
3. The method of claim 1, wherein the entity print for each entity is stored as a measure of proximity to multiple existing entity prints.
4. The method of claim 1, wherein the device identifier includes an IP address.
5. The method of claim 1, wherein the personal identifier includes at least one of an RSID and a biometric indicator.
6. The method of claim of claim 1, further comprising comparing each interaction request to existing fraudulent interaction signatures to determine if the transaction request represents a fraudulent interaction.
7. The method of claim 1, further comprising building the entity print record and modifying the entity print upon receiving each transaction request from the entity.
8. A central authentication and interaction tracking system for facilitating authentication of an entity engaging in an interaction with a financial institution, the authentication based on a record of interactions initiated by the entity, the system comprising:
an application interface receiving interaction requests over a network, the interaction requests originating from multiple entities and including a plurality of authentication factors, the central authentication and interaction tracking system including;
at least one computer memory storing information from the interaction requests and instructions for processing the information; and
at least one computer processor accessing the computer memory and executing the instructions stored in the computer memory using the computer processor to perform steps including:
building, from each interaction request, an entity print record for each of the multiple entities, wherein each entity print record includes the authentication factors from each initiated interaction request, the authentication factors including a location of the interaction request, a device identifier, and personal identifiers;
deriving, from the entity print record, an entity print and storing the entity print in at least one computer memory;
building, from each interaction request, an interaction signature for each interaction and classifying each interaction signature as a valid interaction signature or a fraudulent interaction signature;
comparing the received authentication factors for a requested interaction with the entity print and comparing the interaction signature for a received interaction request with the classified interaction signatures, wherein the comparisons yield a level of risk for each transaction; and
making an authentication determination based on a level of risk resulting from the comparisons.
9. The system of claim 8, wherein deriving an entity print comprises deriving a level of confidence that the entity is authentic and determining an entity risk level for the entity.
10. The system of claim 8, wherein the entity print for each entity is stored as a measure of proximity to multiple existing entity prints.
11. The system of claim 8, wherein the device identifier includes an IP address.
12. The system of claim 8, wherein the personal identifier includes at least one of an RSID and a biometric indicator.
13. The system of claim 8, further comprising comparing each interaction request to existing fraudulent interaction signatures to determine if the transaction request represents a fraudulent interaction.
14. The system of claim 8, further comprising building the entity print record and modifying the entity print upon receiving each transaction request from the entity.
15. The system of claim 8, further comprising comparing, using triangulation, the received authentication factors with both the entity print and a unique standardized reference entity print.