Author: claimsbot

1. A transistor comprising:
a semiconductor die;
a plurality of transistor segments organized into a plurality of sections, the sections being arranged substantially across the semiconductor die, each section being substantially square, each transistor segment having a racetrack shape with a length and a width, each transistor segment including:
a pillar that includes an extended drain region that extends in a vertical direction through the semiconductor die;
first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;
first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

wherein a first section comprises transistor segments arranged in a side-by-side relationship with the length oriented in a first lateral direction, and a second section comprises transistor segments arranged in the side-by-side relationship with the length oriented in a second lateral direction substantially orthogonal to the first direction, the first section being disposed adjacent the second section.
2. The transistor of claim 1 wherein the pillar further comprises a source region disposed near a top surface of the semiconductor die, and a body region that vertically separates the source region from the extended drain region.
3. The transistor of claim 1 further comprising a gate disposed within the first and second dielectric regions adjacent the body region, the gate being insulated from the body region and the first and second field plates.
4. The transistor of claim 1 wherein the length is at least 20 times greater than the width.
5. The transistor of claim 1 wherein a fourth section comprises transistor segments arranged in the side-by-side relationship with the length oriented in the first lateral direction, and a third section comprises transistor segments arranged in the side-by-side relationship with the length oriented in the second lateral direction, the first section being disposed adjacent the second section in the second lateral direction and adjacent the third section in the first lateral direction, the fourth section being disposed adjacent the second section in the first lateral direction and adjacent the third section in the second lateral direction.
6. The transistor of claim 1 wherein a ratio of the length to the width of the transistor segments in the first and second sections is in a range of about 30 to 80.
7. The transistor of claim 1 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.
8. A transistor comprising:
a semiconductor die;
a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the length being at least 20 times greater than the width, each transistor segment including:
a pillar of a semiconductor material, the pillar including an extended drain region that extends in a vertical direction through the die;
first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;
first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

the sections being arranged in rows and columns substantially across the semiconductor die, adjacent sections in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.
9. The transistor of claim 8 wherein the pillar further comprises a source region disposed near a top surface of the semiconductor die, and a body region that vertically separates the source region from the extended drain region.
10. The transistor of claim 9 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.
11. The transistor of claim 8 wherein the pillar extends in the first and second lateral directions to form a racetrack-shaped ring or oval.
12. The transistor of claim 8 wherein a ratio of the length to the width of the transistor segments in the first and second sections is in a range of about 30 to 80.
13. The transistor of claim 8 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.
14. A semiconductor wafer comprising:
a substrate;
a plurality of die arranged on the substrate in rows and columns, each die including a transistor having a plurality of transistor segments, each transistor segment having a length that extends substantially across the die and a width, the transistor segments of each die being arranged in a side-by-side relationship along the width substantially across the die, each transistor segment including:
a pillar of a semiconductor material, the pillar including a source region disposed near a top surface of the die, and an extended drain region that extends in a vertical direction through the substrate, the pillar extending in the first and second lateral directions to form a racetrack-shaped ring or oval;
first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;
first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

adjacent die in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent die extends in a first direction and the length of the transistor segments in a second one of the adjacent die extends in a second direction, the first direction being substantially orthogonal to the second direction.
15. The semiconductor wafer of claim 14 wherein each transistor segment further comprises a body region that vertically separates the source and extended drain regions.
16. The semiconductor wafer of claim 15 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.
17. The semiconductor wafer of claim 15 wherein a ratio of the length to the width of the transistor segments is in a range of about 50 to 150.
18. The semiconductor wafer of claim 15 wherein each of the plurality of die are substantially square.
19. The semiconductor wafer of claim 15 wherein each of the plurality of die are substantially identical.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A height adjustment device comprising:
a first chassis having an adjustment hole,
an adjustment screw that stands when threadedly engaged with the adjustment hole in the first chassis,
a second chassis locked by the adjustment screw so as to have a preset separation distance from the first chassis, and
biasing means for biasing the first chassis and the second chassis in the direction of attaining separation therebetween, wherein
the adjustment screw has a tip portion for forming a female thread in the adjustment hole when rotated and inserted into the adjustment hole, a threaded portion having a male thread threadedly engaged with the female thread formed by the tip portion, and a head portion for locking the second chassis against the direction of biasing by the biasing means, in a nearly linear state, and
the distance between the end of the head portion of the adjustment screw on the male thread side and the end of the tip portion on the male thread side is made larger than the sum of the length of the inside diameter portion of the adjustment hole in which the female thread is formed, the maximum value of the distance between the first chassis and the second chassis and the thickness of the second chassis.
2. The height adjustment device in accordance with claim 1, wherein the adjustment hole in the first chassis has a small diameter portion in which the female thread is formed and a large diameter portion having a diameter larger than the outside diameter of the tip portion of the adjustment screw, and the adjustment screw is inserted from the side of the small diameter portion to the side of the large diameter portion.
3. The height adjustment device in accordance with claim 1, wherein the threaded portion of the adjustment screw has the same pitch as that of the tip portion and is provided with thread ridges, the diameter of which is smaller than that of the tip portion.

1. A semiconductor memory device comprising:
a memory cell array composed by arranging memory cells containing data storage capacitors in a matrix;
a filter circuit that removes noise contained in an address signal provided from the outside;
a first signal transition detection circuit system that generates a first pulse signal for controlling refresh operation by detecting a change in an address signal prior to passing through the filter circuit;
a second signal transition detection circuit system that generates a second pulse signal for controlling readwrite operation by detecting a change in an address signal after passing through the filter circuit; and
a control system that sequentially performs the refresh operation and the readwrite operation within the same cycle by using the first and second pulse signals as triggers.
2. The semiconductor memory device according to claim 1, wherein the second signal transition detection circuit system controls the first signal transition detection circuit system in an inactive state by detecting a change in an address signal that has passed through the filter circuit.
3. The semiconductor memory device according to claim 1, wherein the control system controls the refresh operation based on the first pulse signal, and controls the readwrite operation based on the second pulse signal.
4. The semiconductor memory device according to claim 1, further comprising a row decoder circuit for selecting a row of the memory cell array,
wherein the control system is composed to include an address multiplexer that selects either a readwrite address signal generated from an address signal that has passed through the filter circuit or a refresh address signal generated in advance within the device based on the first and second pulse signals, and supplies a selected address signal to the row decoder circuit.
5. The semiconductor memory device according to claim 1, wherein the filter circuit is composed to include a delay circuit having a delay amount corresponding to the pulse width of presumed noise targeted for removal.
6. The semiconductor memory device according to claim 1, wherein the filter circuit is composed of a flip-flop that directly inputs the address signal from the outside.
7. The semiconductor memory device according to claim 1, wherein the filter circuit has characteristics that remove noise that causes an address signal provided from the outside to change to the H level in the case the address signal is at the L level.
8. The semiconductor memory device according to claim 1, wherein the second signal transition detection circuit system prohibits readwrite operation by the control system by detecting a change in an address signal that has passed through the filter circuit.
9. A control method of a semiconductor memory device comprising the steps of:
generating a first pulse signal for controlling refresh operation of a memory cell array composed by arranging memory cells containing data storage capacitors in a matrix by detecting a change in an address signal provided from outside the semiconductor memory device;
removing noise contained in the address signal provided from the outside;
generating a second pulse signal for controlling readwrite operation of the memory cell array by detecting a change in the address signal from which noise has been removed; and
sequentially performing the refresh operation and the readwrite operation within the same cycle by using the first and second pulse signals as triggers.
10. The control method of a semiconductor memory device according to claim 9, wherein the generation of the fist pulse signal is prohibited over a prescribed time period by detecting a change in the address signal from which noise has been removed.
11. The control method of a semiconductor memory device according to claim 9, wherein either a readwrite address signal generated from the address signal from which noise has been removed or a refresh address signal generated in advance within the semiconductor memory device is selected based on the first and second pulse signals, and a decoding operation is performed to select a row of the memory cell array.
12. The control method of a semiconductor memory device according to claim 9, wherein an operation is performed for removing noise contained in the address signal provided from the outside over period of time corresponding to the pulse width of presumed noise targeted for removal.
13. The control method of a semiconductor memory device according to claim 9, wherein noise is removed from an address signal input directly from outside the semiconductor memory device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A seat for use in a vehicle, the seat comprising:
a seat base having a cushion and a seat back pivotably coupled to the seat base by a recliner mechanism, such that the seat back can be pivoted in a forward and rearward direction relative to the seat base;
a track assembly coupled to the vehicle and the seat that moves the seat in the forward and rearward directions relative to the vehicle,
a first electromechanical push button actuator located on the seat, the first actuator operable to actuate the seat such that the seat is moved from a use position to an easy entry position in which the seat back is tipped in a forward direction and the seat is slid forward on the track assembly;
a second actuator operable to actuate the seat such that the seat is moved from a use position to a fold flat position in which the seat back is folded forward and rests flat on a top surface of the cushion;
an energy storage device for storing energy generated from movement of the seat and selectively releasing stored energy to assist in repositioning the seat when at least one of the first and second actuators is actuated;
a force transmitting device having one end connected to the first actuator and a second end connected to the recliner mechanism, such that energizing the first actuator actuates the force transmitting device to release the recliner mechanism and move the seat from the use position to the easy entry position; and
an energy storage bypass mechanism that prevents release of stored energy from the energy storage device when the seat is occupied and enables release of stored energy from the energy storage device when the seat is not occupied.
2. The seat of claim 1, further comprising an emergency release handle that is operatively connected to the recliner mechanism, and disengages the recliner mechanism when pulled thereby enabling the seat to be adjusted.
3. The seat of claim 1, wherein the first actuator is activated remotely outside the vehicle using a key fob.
4. The seat of claim 1, wherein the energy storage bypass mechanism further comprises:
a housing;
a pivot member disposed within the housing and coupled to the energy storage device and having a central aperture, wherein the pivot member is pivotably coupled to the housing and the seat, and the energy storage device biases the pivot member in a predetermined direction;
a slide block member slidably disposed within the housing and having a first end and a second end, the first end having a surface for engagement with the pivot member;
a pinion member disposed within the housing and having a first end and a second end, the first end having a biasing member for coupling to the slide block member,
an interlock member disposed within the housing and having a first end and a second end, wherein the first end includes a surface for engagement with the pinion member and the second end includes a surface having a biasing member that biases the pinion member away from the slide block member such that the interlock member is in engagement with the slide block member when the seat is occupied, thereby enabling the energy stored in the energy storage device to be released upon actuation of at least one of the first actuator and the second actuator and the interlock member is disengaged from pinion member and the pinion member is disengaged from the slide block member when the seat is occupied, thereby preventing the slide block member from being disengaged from the pivot member and thereby preventing the energy stored in the energy storage device from being released upon actuation of at least one of the first actuator and the second actuator.
5. The seat of claim 1, further comprising:
a seat occupation detection system for regulating engagement and disengagement of the energy storage bypass mechanism.
6. The seat of claim 1, wherein the force transmitting device is a push-pull cable.
7. The seat of claim 1, further comprising a seat occupant detection system that detects the presence of an occupant in the seat and regulates engagement and disengagement of an energy storage bypass mechanism depending on whether the seat is occupied or unoccupied.
8. The seat of claim 7, wherein the seat occupant detection system includes a cable placed across a portion of the seat and is operatively engaged to the energy storage bypass mechanism, such that the weight of an occupant causes the cable to be pulled to deactivate the energy storage bypass mechanism and prevent disengagement of the recliner mechanism.
9. The seat of claim 8, wherein the cable is placed across a suspension surface of the seat base.
10. The seat of claim 1, wherein the first actuator is a linear motor, a rotary motor, or a solenoid.