1. A method for characterizing movement of an object having at least one feature, the method comprising:
identifying data indicative of a plurality of pixels defining an apparent shape, apparent size and apparent position of the at least one feature from data indicative of a pixilated image of the object;
classifying the at least one feature into one of a plurality of predetermined feature classes based on the apparent shape of the at least one feature;
estimating an actual size of the at least one feature based on the classification; and
determining a speed of the object based on the estimated actual size of the at least one feature, the apparent size of the at least one feature, a frame to frame change in the apparent size and the apparent position of the at least one feature, and a time between two frames.
2. The method of claim 1 wherein the data indicative of the plurality of pixels further defines an apparent position of the at least one feature and wherein the determined speed of the object is further based on a change in the apparent position of the at least one feature.
3. The method of claim 1 wherein the determined speed of the object is further based on a change in the apparent shape of the at least one feature.
4. The method of claim 1 further comprising displaying a representation of the determined speed with a pixilated image of the object.
5. The method of claim 1 further comprising determining whether the object is moving.
6. The method of claim 1 wherein determining a speed of the object includes determining whether the object is rotating.
7. The method of claim 1 wherein the at least one feature comprises an outline of the object.
8. The method of claim 1 wherein the at least one feature comprises an outline of a portion of the object.
9. The method of claim 1 wherein classifying the at least one feature into one of a plurality of predetermined feature classes based on the apparent shape of the at least one feature includes comparing the apparent shape of the at least one feature with a plurality of shapes corresponding to the predetermined feature classes.
10. The method of claim 1 wherein the plurality of predetermined feature classes comprises a plurality of predetermined geometric shapes.
11. A non-transitory computer-readable storage medium having information stored thereon for directing a computer to perform the method of claim 1.
12. A system for characterizing movement of an object having at least one feature, the system comprising:
a computing machine configured to
receive input indicative of a pixilated image of the object,
identify data indicative of a plurality of pixels defining an apparent shape, apparent size and apparent position of the at least one feature from the input indicative of the pixilated image of the object,
classify the at least one feature into one of a plurality of predetermined feature classes based on the apparent shape of the at least one feature,
estimate an actual size of the at least one feature based on the classification,
determine a speed of the object based on the estimated actual size of the at least one feature, the apparent size of the at least one feature, a frame to frame change in the apparent size and the apparent position of the at least one feature, and a time between two frames, and
provide output indicative of the determined speed.
13. The system of claim 12 wherein the data indicative of the plurality of pixels further defines an apparent position of the at least one feature and wherein the determined speed of the object is further based on a change in the apparent position of the at least one feature.
14. The system of claim 12 wherein the determined speed of the object is further based on a change in the apparent shape of the at least one feature.
15. The system of claim 12 wherein the computing machine is further configured to display a representation of the determined speed with a pixilated image of the object.
16. The system of claim 12 wherein the computing machine is further configured to determine whether the object is moving.
17. The system of claim 12 wherein determining a speed of the object includes determining whether the object is rotating.
18. The system of claim 12 wherein the at least one feature comprises an outline of the object.
19. The system of claim 12 wherein the at least one feature comprises an outline of a portion of the object.
20. The system of claim 12 wherein classifying the at least one feature into one of a plurality of predetermined feature classes based on the apparent shape of the at least one feature includes comparing the apparent shape of the at least one feature with a plurality of shapes corresponding to the predetermined feature classes.
21. The system of claim 12 wherein the plurality of predetermined feature classes comprises a plurality of predetermined geometric shapes.
22. A system for analyzing movement of an object having at least one feature, the system comprising:
a processing unit configured to
receive a plurality of pixilated images of the object,
extract an outline of the at least one feature from each of the plurality of pixilated images of the object,
determine an apparent position of the at least one feature within each of the plurality of pixilated images of the object,
determine an apparent size of the at least one feature for each of the plurality of pixilated images of the object,
estimate an actual size of the at least one feature based on at least one of the outlines, and
determine a speed of the object based on the estimated actual size of the at least one feature, frame to frame changes in the apparent size of the at least one feature, at least one of (i) the outlines of the at least one feature or (ii) frame to frame changes in the apparent position of the at least one feature, and a time between two frames.
23. A system for analyzing movement of an object, the system comprising:
a processing unit configured to
receive image input indicative of a plurality of frames of pixilated images of the object and size input indicative of an estimated size of the object;
determine a speed of the object based on the size input, frame to frame changes in an apparent size and position of the image, and a time between two frames; and
provide output indicative of the determined speed of the object.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit (IC) having components for providing a first programmable output, the IC comprising:
an accumulator circuit that receives a programmable input N and generates an overflow indication and a remainder R left in the accumulator circuit when an overflow indication is made, wherein the accumulator circuit is coupled to receive a first clock signal having a first frequency;
means for computing a quotient (RN) as the remainder R divided by the programmable input N; and
means for providing an output signal driven by a second clock signal, wherein the output signal is determined from the overflow indication of the accumulator circuit as adjusted by an amount determined using the quotient RN and, wherein a second frequency of the second clock signal is greater than the first frequency to enable desired delay increments, the means for providing an output signal generates a stream of \u201c0s\u201d and \u201c1s\u201d defining the output signal, wherein the means for providing an output signal adds or subtracts \u201c0s\u201d or \u201c1s\u201d to the stream of \u201c0s\u201d and \u201c1s\u201d to adjust a frequency of the output signal;
wherein the means for providing an output signal comprises a repetitive structure having incremental delay elements;
wherein delay provided by the incremental delay elements of the repetitive structure is calibrated under current temperature and supply voltage conditions during operation of the IC; and
wherein a measurement of the number of incremental delay elements equal to one accumulator clock period can be performed under the current temperature and supply voltage conditions.
2. The IC of claim 1 wherein the means for computing the quotient RN comprises a multiplier.
3. The IC of claim 2 wherein an inverse of the programmable input N (1N) is pre-computed and then multiplied by the remainder R in the multiplier.
4. The IC of claim 1 wherein the means for computing the quotient RN comprises a divider.
5. The IC of claim 1, wherein the means for providing an output signal further comprises:
a means for delaying an output edge caused by the overflow indication.
6. The IC of claim 1, wherein the means for providing an output operates at a higher frequency than the accumulator circuit.
7. The IC of claim 1, wherein the means for providing an output signal further provides a serial to parallel conversion to generate a parallel output signal.
8. The IC of claim 1, wherein the means for providing an output comprises a multi-gigabit transceiver.
9. The IC of claim 1, wherein a calibration of the incremental delay elements of the repetitive structure is periodically performed.
10. The IC of claim 1 wherein the accumulator circuit further comprises:
a register; and
an adder having a first input for receiving the programmable input N and a second input for receiving an output feedback from the register, wherein the register provides a first output indicating the remainder R and a second output indicating the when the overflow occurs.
11. An integrated circuit (IC) having components for providing a programmable frequency output, the IC comprising:
an accumulator comprising an adder and a register, wherein the adder comprises a first input for receiving a programmable input N and a second input for receiving an output from the register, and wherein the register indicates an overflow and provides a remainder R occurring at overflow of the register, wherein the register is clocked using a first clock signal having a first frequency;
a multiplier connected with the accumulator to receive the remainder R at overflow, the multiplier for computing a quotient (RN) as the remainder R divided by the programmable input N; and
conversion logic receiving the multiplier quotient RN and a second clock signal having a second frequency which is a higher frequency than the first frequency, wherein the conversion logic provides a jitter-reduced output as adjusted dependent upon the quotient RN, the conversion logic generating a stream of \u201c0s\u201d and \u201c1s\u201d defining the jitter-reduced output, wherein the conversion logic adds or subtracts \u201c0s\u201d or \u201c1s\u201d to the stream of \u201c0s\u201d and \u201c1s\u201d to adjust a frequency of the jitter-reduced output;
wherein the conversion logic comprises a repetitive structure having incremental delay elements;
wherein delay provided by the incremental delay elements of the repetitive structure are calibrated under current temperature and supply voltage conditions during operation of the IC; and
wherein a measurement of the number of incremental delay elements equal to one accumulator clock period can be performed under the current temperature and voltage conditions.
12. The IC as in claim 11 wherein when the remainder R equals zero, the jitter-reduced output will not be affected by the conversion logic output.
13. The IC as in claim 11 wherein the quotient RN ranges from 0 to 1.
14. The IC of claim 11 wherein when the quotient RN is not equal to 0, the conversion logic delays an output edge of the first frequency output.
15. A method of providing a programmable frequency source in a device having programmable resources, comprising:
selecting a first programmable frequency for a first programmable frequency source by setting an input N of an accumulator implemented using the programmable resources of the device and selecting a first frequency of a first clock signal;
determining, by the programmable resources of the device, a remainder R from the accumulator at an overflow of the accumulator;
computing a quotient (RN) as the remainder R divided by the accumulator input N;
driving conversion logic with a second clock signal having a second frequency, wherein the conversion logic comprises a repetitive structure having incremental delay elements;
compensating for a timing error in a frequency of the output signal indicated by overflow of the accumulator using the quotient RN;
generating a stream of \u201c0s\u201d and \u201c1s\u201d defining the output signal at an output of the conversion logic; and
adding or subtracting \u201c0s\u201d or \u201c1s\u201d to the stream of \u201c0s\u201d and \u201c1s\u201d to adjust the frequency of the output signal,
wherein delay provided by the incremental delay elements of the repetitive structure are calibrated under current temperature and supply voltage conditions during operation of the IC; and
wherein a measurement of the number of incremental delay elements equal to one accumulator clock period can be performed under the current temperature and voltage conditions.
16. The method as in claim 15 wherein the step of computing a quotient (RN) comprises multiplying R by an inverse of the accumulator input N(1N).
17. The method as in claim 16 further comprising the step of pre-computing an inverse of the accumulator input N(1N).
18. The method as in claim 15 wherein the computing step comprises dividing the remainder R by the accumulator input N.