Author: claimsbot

1. A keyboard with improving EMC, comprising from top to bottom direction:
a return line layer with a plurality of touch pads;
an insulation layer;
a scan line layer with a plurality of touch pads on a front face thereof;
at least one ground pad on a read face of the scan line layer and opposite to one of the touch pads of the scan line layer; and
A return line layer of U-shape formed on the front face of the scan line layer and connected with one of the touch pads of the scan line layer;
wherein the ground pad forms a capacitor with corresponding touch pad of the scan line layer and the return line layer forms an inductor providing a filter circuit with the capacitor.
2. The keyboard with improving EMC as in claim 1, wherein the diameters of the touch pad and the ground pad are preferably between 3 mm and 4 mm.
3. The keyboard with improving EMC as in claim 1, wherein the return line layer is of reverse U shape.
4. The keyboard with improving EMC as in claim 3, wherein the interval between the reversed U-shaped inductors is preferably about 0.3 mm.
5. The keyboard with improving EMC as in claim 1, wherein the elongate-shaped trace is formed at an input end of the scan line layer.
6. A method for improving EMC (Electromagnetic Compatibility) of a keyboard soft board, which comprises the steps of
providing a return line layer with a plurality of first pads on a front face thereof;
providing a scan line layer with a plurality of second pads on a front face thereof;
providing an insulation layer between the return line layer and the scan line layer;
providing at least one ground pad on a rear face of the scan line layer and opposite to one of the second pads of the scan line layer; and
providing an return line layer formed on the front face of the scan line layer and connected with one of the second pads of the scan line layer;
wherein the ground pads forms a capacitor with each corresponding pad of the scan line layer and the return line layer forms an inductor providing a filter circuit with the capacitor and wherein each of the capacitors is preferably installed between the input terminal of the scan line and the first touch pad.
7. The method of claim 6, wherein the diameters of the touch pad and the ground pad are between 3 mm and 4 mm.
8. The method of claim 6, wherein the shape of the return line layer is a reversed U shape.
9. The method of claim 8, wherein the interval between the reversed U-shaped inductors is about 0.3 mm.
10. A method for improving the EMC of a keyboard soft board, which comprises the steps of arbitrarily selecting more than one scan lines from a plurality of scan lines of the keyboard soft board and designing a low-pass filter for each of them;
the steps of designing the low-pass filter comprising
providing a return line layer with a plurality of first pads on a front face thereof;
providing a scan line layer with a plurality of second pads on a front face thereof;
providing an insulation layer between the return line layer and the scan line layer;
providing at least one ground pad on a rear face of the scan line layer and opposite to one of the second pads of the scan line layer; and
providing an return line layer formed on the front face of the scan line layer and connected with one of the second pads of the scan line layer;
wherein the ground pad forms a capacitor with corresponding pad of the scan line layer and the return line layer forms an inductor providing a filter circuit with the capacitor.
11. The method of claim 10, wherein the diameters of the touch pad and the ground pad are between 3 mm and 4 mm.
12. The method of claim 10, wherein each of the capacitors is preferably installed between the input terminal of the scan line and the first touch pad.
13. The method of claim 10, wherein the shape of the trace is a reversed U shape.
14. The method of claim 13, wherein the interval between the reversed U-shaped inductors is about 0.3 mm.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A motor braking circuit, comprising a braking power switching device coupled across windings of a motor that is repeatedly cycled open and closed by a sequence of pulses generated by the motor braking circuit to intermittently short the windings to brake the motor, the motor braking circuit adjustable to vary at least one of a duty cycle and frequency of the sequence of pulses, the braking power switching device having a small amount of resistance to reduce peak current flow when the windings are shorted through the braking power switching device.
2. The motor braking circuit of claim 1 wherein the braking power switching device is a FET.
3. The motor braking circuit of claim 2 wherein the FET is a MOSFET.
4. The motor braking circuit of claim 2 and further including a controller coupled to the FET that upon power to the motor being disconnected generates the sequence of pulses to switch the FET on and off.
5. The motor braking circuit of claim 4 wherein the controller includes a timer for generating the sequence of pulses.
6. The motor braking circuit of claim 5 wherein the controller includes an adjustment circuit coupled to the timer for adjusting the at least one of the duty cycle and the frequency of the sequence of pulses output by the timer.
7. The motor braking circuit of claim 6 wherein the sequence of pulses comprises a pulse width modulated signal.
8. The motor braking circuit of claim 5 and further including a storage capacitor that is charged when power is connected to the motor and that provides power to the motor braking circuit when power to the motor is disconnected.
9. The motor braking circuit of claim 2 wherein an internal diode of the FET is used in lieu of a separate diode across the windings of the motor.
10. The motor braking circuit of claim 1 and further including a controller for repeatedly cycling the braking power switching device open and closed when a switch that activates the motor when closed is opened.
11. The motor braking circuit of claim 10 and further including a storage capacitor that is charged when power is connected to the motor and that provides power to the motor braking circuit when power to the motor is disconnected.
12. The motor braking circuit of claim 10 wherein the switch provides a signal to the controller based on how far the switch is depressed, the controller controlling the speed of the motor in response to the signal provided by the switch.
13. The motor braking circuit of claim 1 wherein the motor is a DC motor.
14. The motor braking circuit of claim 13 wherein the DC motor is a permanent magnet DC motor.
15. The motor braking circuit of claim 1 wherein the motor is a mains powered motor.
16. A motor braking circuit, comprising:
a FET coupled across windings of a motor, wherein the FET includes an internal diode coupled across the windings of the motor that acts as a free wheeling diode and is used in lieu of a separate free wheeling diode;
a controller coupled to the FET that, upon the motor being switched off, generates a sequence of pulses that switch the FET on and off to brake the motor, the controller adjustable to vary at least one of a duty cycle and a frequency of the sequence of pulses; and
a storage capacitor that is charged when power to the motor is switched on and that provides power for the motor braking circuit when power to the motor is switched off.
17. The motor braking circuit of claim 16 wherein the controller outputs a free running pulsating signal to the braking power switching device.
18. The motor braking circuit of claim 17 wherein the free running pulsating signal is a pulse width modulated signal.
19. The control circuit of claim 17 wherein the free running pulsating signal is a square wave.
20. The motor braking circuit of claim 16 wherein the controller outputs a pulse width modulated signal to generate the sequence of pulses and varies at least one of the duty cycle and frequency of the pulse width modulated signal to control braking of the motor.
21. A control circuit for a motor, comprising a switch for activating the motor when the switch is on, a controller, a FET coupled across windings of the motor and coupled to the controller, the FET having an internal diode coupled across the windings of the motor, the internal diode of the FET acting as a freewheeling diode and used in lieu of a separate diode, the controller cycling the FET on and off to brake the motor when the switch is switched off.
22. The control circuit of claim 21 wherein the motor is a DC motor and the switch connects the motor to a source of DC power to activate the motor when the switch is on and disconnects the motor from the source of DC power to deactivate it when the switch is off, and further including a storage capacitor that is charged when the switch is on and provides power for the controller and the FET when the switch is off.
23. The control circuit of claim 21 wherein the FET is a MOSFET.
24. The control circuit of claim 21 wherein the motor is a mains powered motor.
25. The control circuit of claim 21 wherein the motor is a DC motor coupled to a battery, the motor remaining connected to the battery when the switch is off deactivating the motor so that power generated during braking the motor recharges the battery at least in part.
26. The control circuit of claim 21 wherein the switch is a trigger switch housed in a module that also houses the FET.
27. The control circuit of claim 21 wherein the controller controls braking of the motor by varying at least one of a duty cycle and frequency of a pulse width modulated signal that the controller outputs to the FET.
28. The control circuit of claim 27 wherein the controller senses at least one of motor speed and back emf of the motor and controls braking of the motor based on the at least one of motor speed and back emf of the motor.
29. The control circuit of claim 21 wherein the controller outputs a free running pulsating signal to the FET.
30. The control circuit of claim 29 wherein the free running pulsating signal is a pulse width modulated signal.
31. The control circuit of claim 29 wherein the free running pulsating signal is a square wave signal.
32. The control circuit of claim 21 wherein the switch is a trigger switch that provides a signal to the controller based on how far the switch is depressed, the controller controlling the speed of the motor in response to the signal provided by the trigger switch.
33. The control circuit of claim 32 wherein the trigger switch includes a potentiometer that provides the signal to the controller based on how far the switch is depressed.
34. A power tool, comprising:
a housing surrounding a motor;
a switch for activating the motor when the switch is on;
a controller; and
a braking switching device coupled across windings of the motor and coupled to the controller, the controller cycling the braking switching device open and closed with a sequence of pulses to intermittently short the windings to brake the motor when the switch is switched off, the controller adjustable to vary at least one of a duty cycle and a frequency of the sequence of pulses, the braking switching device having a small amount of resistance to reduce peak current flow when the windings are shorted through the braking switching device.
35. The power tool of claim 34, wherein the braking switching device includes a semiconductor switch.
36. The power tool of claim 35 wherein the semiconductor switch includes a FET having an internal diode coupled across the windings of the motor, the internal diode of the FET acting as a free wheeling diode and used in lieu of a separate free wheeling diode.
37. The power tool of claim 35 wherein the switch is a trigger switch housed in a module, the braking switching device also housed in the module.
38. The power tool of claim 37 wherein the switch is a trigger switch having a potentiometer that provides a signal to the controller based on how far the switch is depressed, the controller controlling the speed of the motor in response to the signal provided by the potentiometer.
39. The power tool of claim 37 wherein the motor is a DC motor and the switch connects the motor to a source of DC power to activate the motor when the switch is on and disconnects the motor from the source of DC power to deactivate it when the switch is off.
40. The power tool of claim 37 wherein the motor is a mains powered motor.
41. The power tool of claim 35 and further including a battery and a storage capacitor, the motor comprising a DC motor that is coupled to the battery when the switch is on and decoupled from the battery when the switch is off, the storage capacitor being charged by the battery when the switch is on and providing power to the controller and semiconductor switch when the switch is off.
42. A method of braking a motor, comprising cycling a braking switching device coupled across windings of the motor open and closed to intermittently short the windings to brake the motor by pulsing the braking switching device with a pulsating signal and adjusting at least one of a duty cycle and frequency of the pulsating signal, the braking switching device having a small amount of resistance to reduce peak current flow when the windings are shorted through the braking switching device.
43. The method of claim 42, wherein cycling the braking switching device open and closed includes switching a semiconductor switch coupled across the windings of the motor on and off.
44. The method of claim 43, wherein pulsing the semiconductor switch includes pulsing it with a pulse width modulated signal and varying at least one of a duty cycle and frequency of the pulse width modulated signal to vary at least one of a braking speed and braking current.
45. In a cordless power tool having a permanent magnet DC motor, a switch that activates the motor when switched on and deactivates the motor when switched off, a method of braking the motor, comprising switching a semiconductor switch coupled across the windings of the motor on and off to intermittently short the windings to brake the motor by pulsing the semiconductor switch with a pulsating signal and adjusting at least one of a duty cycle and frequency of the pulsating signal, the semiconductor switch having a small amount of resistance to reduce peak current flow when the windings are shorted through the semiconductor switch.
46. The method of claim 45 and further including charging a storage capacitor when the switch is on and providing power to the semiconductor switch from the storage capacitor when the switch is switched off.
47. The method of claim 46 wherein the semiconductor switch is a MOSFET having an internal diode coupled across the windings of the motor, the method further including using the internal diode of the MOSFET as a free wheeling diode in lieu of a separate free wheeling diode.
48. In a power tool having a mains powered motor, a switch that activates the motor when switched on and deactivates the motor when switched off, a method of braking the motor, comprising switching a semiconductor switch coupled across the windings of the motor on and off to intermittently short the windings to brake the motor by pulsing the semiconductor switch with a pulsating signal and adjusting at least one of a duty cycle and frequency of the pulsating signal, the semiconductor switch having a small amount of resistance to reduce peak current flow when the windings are shorted through the semiconductor switch.
49. The method of claim 48 and further including charging a storage capacitor when the switch is on and providing power to the semiconductor switch from the storage capacitor when the switch is switched off.
50. The method of claim 49 wherein the semiconductor switch is a MOSFET having an internal diode coupled across the windings of the motor, the method further including using the internal diode of the MOSFET as a free wheeling diode in lieu of a separate free wheeling diode.
51. A power tool, comprising:
a housing surrounding a motor;
a switch for activating the motor when the switch is on;
a controller; and
a FET coupled across windings of the motor and coupled to the controller, the controller cycling the FET open and closed to brake the motor when the switch is switched off, the FET having an internal diode coupled across the windings of the motor, the internal diode of the FET acting as a freewheeling diode and used in lieu of a separate freewheeling diode.
52. A power tool, comprising:
a housing surrounding a motor;
a switch for activating the motor when the switch is on;
a controller; and
a FET coupled across windings of the motor and coupled to the controller, the controller cycling the FET open and closed to intermittently short the windings to brake the motor when the switch is switched off, the FET having an internal diode coupled across the windings of the motor, the internal diode of the FET acting as a freewheeling diode and used in lieu of a separate freewheeling diode, the FET having a small amount of resistance to reduce peak current flow when the windings are shorted through the FET.
53. The power tool of claim 52 wherein the switch is a trigger switch housed in a module that also houses the controller and FET.

1. Apparatus comprising an endovascular stent-graft system, which comprises:
a fenestrated stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, and which comprises a fenestrated support structure and a fenestrated covering element, which is securely attached to and covers at least a portion of the fenestrated support structure, wherein the fenestrated support structure and the fenestrated covering element are shaped so as to together define first and second lateral apertures in the central portion, which apertures face in generally radially opposing directions, when the fenestrated stent-graft is in a radially-expanded state thereof; and
a crossing stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, and which comprises a crossing support structure and one or more crossing covering elements, which are securely attached to and at least partially cover the first and the second end portions, such that the central portion is at least partially uncovered when the crossing stent-graft is in a radially-expanded state thereof,
wherein the fenestrated and the crossing stent-grafts are sized and shaped such that, when the crossing stent-graft is disposed through the first and the second apertures such that the central portion of the crossing stent-graft is within the central portion of the fenestrated stent-graft, the first and the second end portions of the crossing stent-graft (a) pass through the first and the second apertures, respectively, and (b) when the fenestrated and the crossing stent-grafts are in their radially-expanded states, form blood-impervious seals with the first and the second apertures, respectively, such that interior spaces defined by all of the following are in fluid communication with one another: the first and the second end portions and the central portion of the fenestrated stent-graft, and the first and the second end portions and the central portion of the crossing stent-graft.
2. The apparatus according to claim 1, wherein the central portion of crossing stent-graft is generally sized to fit a perimeter of each of the apertures, when the stent-grafts are unconstrained in their radially-expanded states.
3. The apparatus according to claim 1, wherein the one or more crossing covering elements include first and second covering elements, which are securely attached to and at least partially cover the first and the second end portions of the crossing stent-graft, respectively.
4. The apparatus according to claim 3, wherein, when the crossing stent-graft is unconstrained in its radially-expanded state:
one end of the first covering element defines a generally elliptical circumferential junction between the first end portion and the central portion of the crossing stent-graft,
one end of the second covering element defines a generally elliptical circumferential junction between the second end portion and the central portion of the crossing stent-graft, and
the central portion of the crossing stent-graft is entirely uncovered.
5-6. (canceled)
7. The apparatus according to claim 1, wherein the central portion of the fenestrated stent-graft is generally fusiform, when the fenestrated stent-graft is unconstrained in its radially-expanded state.
8. The apparatus according to claim 1, wherein the fenestrated stent-graft is generally fusiform, when the fenestrated stent-graft is unconstrained in its radially-expanded state.
9-13. (canceled)
14. The apparatus according to claim 1, wherein the first and the second end portions of the crossing stent-graft have respective medial ends, at which the first and the second end portions are joined to the central portion of the crossing stent-graft, respectively, and wherein at least one of the first and the second end portions of the crossing stent-graft is outwardly flared toward the central portion of the crossing stent-graft, when the crossing stent-graft is in its radially-expanded state.
15. The apparatus according to claim 1, wherein the first and the second end portions of the fenestrated stent-graft have respective ends that coincide with respective ends of the fenestrated stent-graft, and wherein a ratio of (a) a greatest perimeter of the central portion of the fenestrated stent-graft to (b) a perimeter of each of the ends of the first and the second end portions of the fenestrated stent-graft is between 4 and 15, when the fenestrated stent-graft is unconstrained in its radially-expanded state.
16-17. (canceled)
18. The apparatus according to claim 1, wherein the fenestrated covering element does not extend to at least one end of the fenestrated stent-graft, such that the fenestrated support structure is not covered near the end.
19. The apparatus according to claim 1, wherein the one or more crossing covering elements do not extend to at least one end of the crossing stent-graft, such that the crossing support structure is not covered near the end.
20. The apparatus according to claim 1, wherein an average perimeter of the central portion of the crossing stent-graft (a) is less than an average perimeter of the first end portion of the crossing stent-graft and (b) is less than an average perimeter of the second end portion of the crossing stent-graft, when the crossing stent-graft is unconstrained in its radially-expanded state.
21-26. (canceled)
27. The apparatus according to claim 1, wherein the crossing stent-graft, when in its radially-expanded state, has an hour-glass shape, and the central portion of the crossing stent-graft is shaped so as to define a stricture in the hour-glass shape.
28. The apparatus according to claim 1, wherein the crossing stent-graft is configured to be implanted in a main blood vessel having an aneurysm, and the first and the second end portions of the fenestrated stent-graft are configured to be implanted at least partially in respective branching blood vessels of the main blood vessel, such that the central portion of the fenestrated stent-graft is positioned in the main blood vessel.
29. The apparatus according to claim 1, wherein the fenestrated stent-graft is configured to be implanted in a main blood vessel having an aneurysm, and the first and the second end portions of the crossing stent-graft are configured to be implanted at least partially in respective branching blood vessels of the main blood vessel, such that the central portion of the crossing stent-graft is positioned in the main blood vessel.
30. (canceled)
31. A method for treating a patient, the method comprising:
providing (a) a fenestrated stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, which central portion is shaped so as to define first and second lateral apertures that face in generally radially opposing directions, when the fenestrated stent-graft is in a radially-expanded state thereof, and (b) a crossing stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, and which comprises a crossing support structure and one or more crossing covering elements, which are securely attached to and at least partially cover the first and the second end portions, such that the central portion is at least partially uncovered when the crossing stent-graft is in a radially-expanded state thereof;
deploying the fenestrated stent-graft such that the first and the second end portions thereof are at least partially positioned in respective first and second branching blood vessels of a main blood vessel of the patient, the central portion of the fenestrated stent-graft is positioned in the main blood vessel, and the fenestrated stent-graft is in its radially-expanded state;
thereafter, introducing the crossing stent-graft into the main blood vessel, and passing the crossing stent-graft, while in a radially-compressed state thereof, through the second and the first apertures, such that the central portion of the crossing stent-graft is within the central portion of the fenestrated stent-graft, and the first and the second end portions of the crossing stent-graft pass through the first and the second apertures, respectively; and
transitioning the crossing stent-graft to its radially-expanded state, such that the first and the second end portions of the crossing stent-graft form blood-impervious seals with the first and the second apertures, respectively, such that interior spaces defined by all of the following are in fluid communication with one another: the first and the second end portions and the central portion of the fenestrated stent-graft, and the first and the second end portions and the central portion of the crossing stent-graft.
32. The method according to claim 31, wherein deploying the fenestrated stent-graft comprises laparoscopically introducing the fenestrated stent-graft into the first branching blood vessel, and advancing the fenestrated stent-graft across the main blood vessel to the second branching blood vessel.
33. The method according to claim 31, wherein introducing the crossing stent-graft comprises endovascularly introducing the crossing stent-graft into the main blood vessel.
34. (canceled)
35. The method according to claim 31, wherein providing the fenestrated stent-graft comprises providing the fenestrated stent-graft in which the central portion thereof is generally fusiform, when the fenestrated stent-graft is unconstrained in its radially-expanded state.
36. The method according to claim 31, wherein providing the fenestrated stent-graft comprises providing the fenestrated stent-graft which is generally fusiform, when the fenestrated stent-graft is unconstrained in its radially-expanded state.
37. A method for treating a patient, the method comprising:
providing (a) a fenestrated stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, which central portion is shaped so as to define first and second lateral apertures that face in generally radially opposing directions, when the fenestrated stent-graft is in a radially-expanded state thereof, and (b) a crossing stent-graft, which includes first and second end portions and a central portion disposed longitudinally therebetween, and which comprises a crossing support structure and one or more crossing covering elements, which are securely attached to and at least partially cover the first and the second end portions, such that the central portion is at least partially uncovered when the crossing stent-graft is in a radially-expanded state thereof;
deploying the fenestrated stent-graft in a main blood vessel of the patient such that the first and the second apertures generally face first and second branching blood vessels of the main blood vessel, and the fenestrated stent-graft is in its radially-expanded state;
thereafter, introducing the crossing stent-graft into the first branching blood vessel, and passing the crossing stent-graft, while in a radially-compressed state thereof, through the first and the second apertures, and into the second branching blood vessel, such that the central portion of the crossing stent-graft is within the central portion of the fenestrated stent-graft, and the first and the second end portions of the crossing stent-graft pass through the first and the second apertures, respectively; and
transitioning the crossing stent-graft to its radially-expanded state, such that the first and the second end portions of the crossing stent-graft form blood-impervious seals with the first and the second apertures, respectively, such that interior spaces defined by all of the following are in fluid communication with one another: the first and the second end portions and the central portion of the fenestrated stent-graft, and the first and the second end portions and the central portion of the crossing stent-graft.
38. The method according to claim 37, wherein deploying the fenestrated stent-graft comprises endovascularly introducing the crossing stent-graft into the main blood vessel.
39. The method according to claim 37, wherein introducing the crossing stent-graft comprises laparoscopically introducing the crossing stent-graft into the first branching blood vessel, and advancing the crossing stent-graft across the main blood vessel to the second branching blood vessel.
40-44. (canceled)
45. The method according to claim 31, wherein providing the crossing stent-graft comprises providing the crossing stent-graft in which the central portion thereof is generally sized to fit a perimeter of each of the apertures, when the stent-grafts are unconstrained in their radially-expanded states.
46-49. (canceled)
50. The method according to claim 37, wherein providing the crossing stent-graft comprises providing the crossing stent-graft in which the central portion thereof is generally sized to fit a perimeter of each of the apertures, when the stent-grafts are unconstrained in their radially-expanded states.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode;
forming a gate insulating layer over the gate electrode;
forming an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;
forming a source electrode and a drain electrode over the oxide semiconductor layer;
forming a first insulating layer over the source electrode and the drain electrode under a condition with a first gas flow rate, a first pressure, a first RF power, and first substrate temperature, the first insulating layer being in contact with part of the oxide semiconductor layer;
introducing oxygen into the first insulating layer by a plasma treatment under oxygen atmosphere; and
forming a second insulating layer over the first insulating layer under a condition with a second gas flow rate, a second pressure, a second RF power, and second substrate temperature,
wherein a thickness of the first insulating layer is more than 10 nm and less than 100 nm,
wherein the second insulating layer is thicker than the first insulating layer,
wherein the first gas flow rate is smaller than the second gas flow rate,
wherein the first pressure is smaller than the second pressure,
wherein the first RF power is smaller than the second RF power, and
wherein the first substrate temperature is higher than the second substrate temperature.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of removing impurities of the part of the oxide semiconductor layer after forming the source electrode and the drain electrode.
3. The method for manufacturing a semiconductor device according to claim 1,
further comprising the step of forming a third insulating layer over the second insulating layer by forming a metal layer over the second insulating layer and performing an oxygen doping treatment thereon.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the third insulating layer comprises aluminum oxide.
5. The method for manufacturing a semiconductor device according to claim 3, wherein the third insulating layer has a resistivity less than or equal to 1\xd71019 \u03a9\xb7m.
6. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode;
forming a gate insulating layer over the gate electrode;
forming an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;
forming a source electrode and a drain electrode over the oxide semiconductor layer;
forming a first insulating layer over the source electrode and the drain electrode, the first insulating layer being in contact with part of the oxide semiconductor layer;
introducing oxygen into the first insulating layer by a plasma treatment under oxygen atmosphere; and
forming a second insulating layer over the first insulating layer,
wherein a thickness of the first insulating layer is more than 10 nm and less than 100 nm,
wherein a thickness of the second insulating layer is more than 3 nm and less than 10 nm, and
wherein the second insulating layer is a metal oxide layer formed by forming a metal layer over the first insulating layer and performing an oxygen doping treatment thereon.
7. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of removing impurities of the part of the oxide semiconductor layer after forming the source electrode and the drain electrode.
8. The method for manufacturing a semiconductor device according to claim 6, wherein the second insulating layer comprises aluminum oxide.
9. The method for manufacturing a semiconductor device according to claim 6, wherein the second insulating layer has a resistivity less than or equal to 1\xd71019 \u03a9\xb7m.
10. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a planarization insulating layer over the second insulating layer.
11. The method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a conductive layer over the planarization insulating layer.
12. The method for manufacturing a semiconductor device according to claim 11, wherein the conductive layer is electrically connected to a photodiode.
13. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of forming a planarization insulating layer over the second insulating layer.
14. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of forming a conductive layer over the planarization insulating layer.
15. The method for manufacturing a semiconductor device according to claim 14, wherein the conductive layer is electrically connected to a photodiode.
16. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of performing heat treatment to the oxide semiconductor layer before forming the source electrode and the drain electrode.
17. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of performing heat treatment to the oxide semiconductor layer before forming the source electrode and the drain electrode.
18. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode;
forming a gate insulating layer over the gate electrode;
forming an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate electrode;
forming a source electrode and a drain electrode over the oxide semiconductor layer;
performing dinitrogen monoxide plasma treatment to the oxide semiconductor layer after forming the source electrode and the drain electrode;
forming a first insulating layer over the source electrode and the drain electrode under a condition with a first gas flow rate, a first RF power, and first substrate temperature, the first insulating layer being in contact with part of the oxide semiconductor layer; and
forming a second insulating layer over the first insulating layer under a condition with a second gas flow rate, a second RF power, and second substrate temperature,
wherein a thickness of the first insulating layer is more than 10 nm and less than 100 nm,
wherein the second insulating layer is thicker than the first insulating layer,
wherein the first gas flow rate is smaller than the second gas flow rate,
wherein the first RF power is smaller than the second RF power, and
wherein the first substrate temperature is higher than the second substrate temperature.
19. The method for manufacturing a semiconductor device according to claim 18,
further comprising the step of forming a third insulating layer over the second insulating layer by forming a metal layer over the second insulating layer and performing an oxygen doping treatment thereon.
20. The method for manufacturing a semiconductor device according to claim 19, wherein the third insulating layer comprises aluminum oxide.
21. The method for manufacturing a semiconductor device according to claim 19, wherein the third insulating layer has a resistivity less than or equal to 1\xd71019 \u03a9\u2022m.
22. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a planarization insulating layer over the second insulating layer.
23. The method for manufacturing a semiconductor device according to claim 22, further comprising the step of forming a conductive layer over the planarization insulating layer.
24. The method for manufacturing a semiconductor device according to claim 23, wherein the conductive layer is electrically connected to a photodiode.
25. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of performing heat treatment to the oxide semiconductor layer before forming the source electrode and the drain electrode.