Author: claimsbot

1. For use with a circuit tester having control signals used to exercise a target circuit in a test mode, the target circuit having logic circuitry that processes data in response to an operational clock signal having at least one clock cycle, a method for delay-fault testing comprising: providing a test-clock signal having at least four clock-state transitions that occur within said at least one clock cycle; concurrently using both the circuit tester to exercise the target circuit using the operational clock signal and the test-clock signal to exercise the logic circuitry and therein cause the logic circuitry to generate an output signal; and receiving and processing the output signal at the circuit tester and, therefrom, detecting a delay fault in the target circuit.
2. The method of claim 1, wherein providing a test-clock signal includes generating a rapid clock signal having said at least four clock-state transitions and wherein using the test-clock signal to exercise the logic circuitry includes selectively applying the rapid clock signal for at least four clock-state transitions.
3. The method of claim 1, further comprising: providing an interface circuit that responds to the test-clock signal and the operational clock signal to control signals by selectively passing the test-clock signal to exercise the logic circuitry.
4. The method of claim 3, wherein providing an interface circuit further comprises providing an interface circuit that has a delay mode and a capture mode and that passes the operational clock signal to the target circuit during the delay mode and passes the test-clock signal to exercise the logic circuitry during the capture mode, wherein exercising the logic circuitry and therein causing the logic circuitry to generate an output signal includes causing the logic circuitry to generate an output signal during the capture mode.
5. The method of claim 3, wherein selectively passing the test-clock signal includes selectively passing the test-clock signal during a capture mode by delaying the passing of the test-clock signal for at least one cycle of the test-clock signal after the start of the capture mode and by disabling the passing of the test-clock signal at least one cycle of the test-clock signal before the end of the capture mode.
6. The method of claim 1, wherein detecting a delay fault includes detecting a resistive circuit.
7. The method of claim 6, wherein detecting a resistive circuit includes detecting a circuit that responds slower than other circuits in the target circuit due to higher resistance in the resistive circuit.
8. The method of claim 1, wherein providing a test-clock signal includes generating the test-clock signal using circuitry in the target circuit.
9. The method of claim 1, wherein providing a test-clock signal includes using a computer programmed for selecting a frequency of the test-clock signal and selecting the frequency with the programmed computer for exercising the logic circuitry at the selected frequency.
10. The method of claim 1, prior to providing the test-clock signal, further comprising locking the phase of the receiving and processing of the output signal so that a change in phase of the output signal is detectable as a delay in the output signal from the logic circuitry.
11. For use with a circuit tester having control signals used to exercise a target circuit in a test mode, the target circuit having logic circuitry that processes data in response to an operational clock signal having at least one clock cycle, a system for delay-fault testing comprising: means for providing a test-clock signal having at least four clock-state transitions that occur within said at least one clock cycle; means for concurrently using both the circuit tester to exercise the target circuit using the operational clock signal and the test-clock signal to exercise the logic circuitry and therein cause the logic circuitry to generate an output signal; and means for receiving and processing the output signal at the circuit tester and, therefrom, detecting a delay fault in the target circuit.
12. For use with a circuit tester having control signals used to exercise a target circuit in a test mode, the target circuit having logic circuitry that processes data in response to an operational clock signal having at least one clock cycle, a system for delay-fault testing comprising: a test-clock signal generator having at least four clock-state transitions that occur within said at least one clock cycle; an interface circuit adapted to concurrently use both the circuit tester to exercise the target circuit using the operational clock signal and the test-clock signal to exercise the logic circuitry and therein cause the logic circuitry to generate an output signal; and a detection arrangement adapted to receive and process the output signal at the circuit tester and, therefrom, detect a delay fault in the target circuit.
13. The system of claim 12, wherein the test-clock signal generator is located in the target circuit and is coupled to the logic circuitry for providing the test-clock signal thereto.
14. The system of claim 12, wherein the test-clock signal generator is programmable for generating a test-clock signal having a selectable frequency.
15. The system of claim 12, further comprising the circuit tester, wherein the circuit tester is adapted to provide a scan enable signal during a capture mode, the interface circuit being further adapted to respond to the scan enable signal by entering exercising the logic circuitry is during the capture mode.
16. The system of claim 15, wherein the circuit tester is further adapted to provide a delay fault enable signal, wherein the interface circuit is adapted to respond to the delay fault enable signal and the scan enable signal by delaying the application of the test-clock signal for exercising the logic circuitry for at least one clock-state transition of the test-clock signal after the scan enable signal has been enabled and to disable the application of the test-clock signal for exercising the logic circuitry at least one clock-state transition of the test-clock signal before the scan enable signal has been disabled.
17. The system of claim 15, wherein the circuit tester is adapted to provide the control signals to the logic circuitry using the test-clock signal.
18. The system of claim 12, wherein the test-clock signal generator includes a latching circuit configured and arranged for locking the phase of the output signal to a reference for detecting a delay as a change in the phase of the output signal.
19. The system of claim 18, wherein the latching circuit is adapted to lock the phase of the output signal after a test vector has been initiated to the target circuit and prior to the interface circuit concurrently using both the circuit tester to exercise the target circuit using the operational clock signal and the test-clock signal to exercise the logic circuitry and therein cause the logic circuitry to generate an output signal.
20. For use with a delay-fault circuit tester adapted to provide test signals to a target circuit using an operational clock having at least one clock cycle, a circuit chip comprising: a target circuit including logic circuitry susceptible to timing-related failures at high operational clock speeds and being operational in a test mode in response to test signals from the circuit tester; a test-clock signal generator circuit programmed to selectively provide a high-speed test-clock clock signal having at least four clock-state transitions that occur within said at least one clock cycle of the operational clock; and a clock interface circuit adapted to selectively separately apply one of the operational clock signal and the test-clock signal to the target circuit to exercise the target circuit, the test-clock signal being selectively applied during a capture mode to cause the target circuit to generate an output signal that is detectable by the circuit tester for detecting a delay in the output signal that is a function of a timing-related failure in the target circuit that occurs in response to the target circuit being exercised by the high-speed test-clock signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus comprising:
an interlock assembly, the interlock assembly comprising:
a slide element which slideably couples to an air-moving assembly, the air-moving assembly being removable from a chassis within which the air-moving assembly resides when in an operating state, the slide element residing in a first position when the air-moving assembly is in the operating state, and being slidable to a second position when the air-moving assembly is in a quiesced state, wherein the slide element facilitates preventing removal of the air-moving assembly from the chassis in the first position, and allows removal of the air-moving assembly from the chassis in the second position; and
at least one interlock element associated with the slide element and preventing sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
2. The apparatus of claim 1, wherein the at least one interlock element physically contacts a feature associated with the air-moving assembly to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
3. The apparatus of claim 1, wherein the at least one interlock element engages a plugged cable of the air-moving assembly to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
4. The apparatus of claim 3, wherein the at least one interlock element comprises an interlock arm which extends from the side element and engages the plugged cable to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
5. The apparatus of claim 4, wherein transitioning the slide element from the first position to the second position requires unplugging of the plugged cable, to transition the air-moving assembly from the operating state to a non-operating state, and to disengage the interlock arm from contact with the power cable.
6. The apparatus of claim 1, wherein the interlock assembly further comprises at least one louver disposed at one of an air inlet or an air outlet of the air-moving assembly, the at least one louver pivoting between an operational orientation and a quiesced orientation, dependent on presence or absence, respectively, of airflow through the air-moving assembly, and wherein the at least one interlock element contacts a louver of the at least one louver to prevent sliding of the slide element from the first position to the second position when the at least one louver is in the operational orientation.
7. The apparatus of claim 6, wherein the at least one interlock element extends from the slide element and engages at least one side edge of the louver when the at least one louver is in operational orientation, thereby preventing sliding of the slide element from the first position to the second position.
8. The apparatus of claim 7, wherein the at least one interlock element comprises an interlock arm extending from the slide element.
9. The apparatus of claim 6, wherein the interlock assembly further comprises multiple interlock elements, the at least one interlock element being at least one interlock element of the multiple interlock elements, and wherein the multiple interlock elements further comprise at least one other interlock element which engages a plugged cable of the air-moving assembly to farther prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
10. The apparatus of claim 1, wherein the slide element blocks, at least in part, access in the first position to at least one fastener securing the air-moving assembly within the chassis.
11. The apparatus of claim 1, wherein the air-moving assembly comprises a centrifugal fan, and the interlock assembly is coupled to the air-moving assembly an air outlet thereof.
12. An apparatus comprising:
an air-moving assembly residing within a chassis when in an operating state, the air-moving assembly being removable from the chassis; and
an interlock assembly, the interlock assembly comprising:
a slide element slideably coupled to the air-moving assembly, the slide element residing in a first position when the air-moving assembly in the operating state, and being slidable to a second position when the air-moving assembly is in a quiesced state, wherein the slide element facilitates preventing removal of the air-moving assembly from the chassis in the first position, and allows removal of the air-moving assembly from the chassis in the second position; and
an interlock element associated with the slide element and preventing sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
13. The apparatus of claim 12, wherein the at least one interlock element physically contacts a feature associated with the air-moving assembly to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
14. The apparatus of claim 12, wherein the at least one interlock element engages a plugged cable of the air-moving assembly to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
15. The apparatus of claim 14, wherein the at least one interlock element comprises an interlock arm which extends from the slide element and engages the plugged cable to prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
16. The apparatus of claim 12, wherein the interlock assembly further comprises at least one louver disposed at one of an air inlet or an air outlet of the air-moving assembly, the at least one louver pivoting between an operational orientation and a quiesced orientation, dependent on presence or absence, respectively, of airflow through the air-moving assembly, and wherein the at least one interlock element contacts a louver of the at least one louver to prevent sliding of the slide element from the first position to the second position when the at least one louver is in the operational orientation.
17. The apparatus of claim 16, wherein the at least one interlock element extends from the slide element and engages at least one side edge of the louver when the at least one louver is in operational orientation, thereby preventing sliding of the slide element from the first position to the second position.
18. The apparatus of claim 16, wherein the interlock assembly further comprises multiple interlock elements, the at least one interlock element being at least one interlock element of the multiple interlock elements, and wherein the multiple interlock elements further comprise at least one other interlock element which engages a plugged cable of the air-moving assembly to further prevent sliding of the slide element from the first position to the second position when the air-moving assembly is in the operating state.
19. The apparatus of claim 12, wherein the slide element blocks, at least in part, access in the first position to at least one fastener securing the air-moving assembly within the chassis.
20. (canceled)

1. A radiating source for transmitting and receiving at different frequencies, intended to be installed on board a satellite to define a radiation pattern in a terrestrial zone, said source being intended to be disposed in or near the focal plane of a reflector associated with other sources corresponding to other terrestrial zones, the source including a plurality of radiating apertures, each of which has an efficiency at least equal to 70%, and feed means for feeding each radiating aperture, the radiating apertures and their feed means being such that the energy radiated by all of the radiating apertures is practically limited to the corresponding reflector, at least for transmission.
2. A source according to claim 1, wherein the radiating apertures are fed differently for transmission and for reception.
3. A source according to claim 1, wherein the feed means for each radiating aperture are such that the radiation pattern is substantially the same for transmission and for reception.
4. A source according to claim 1, including a central radiating aperture and peripheral radiating apertures.
5. A source according to claim 4, wherein the peripheral radiating apertures are regularly distributed around the axis of the central radiating aperture.
6. A source according to claim 4, wherein the feed to the central radiating aperture is such that said radiating aperture produces the most radiation.
7. A source according to claim 6, wherein the feed means for the peripheral radiating apertures are such that the radiation produced by each of said peripheral radiating apertures is of practically the same intensity and less than the intensity of the radiation produced by the central radiating aperture.
8. A source according to claim 1, wherein the radiation to be transmitted by the source has linear polarization in a particular direction and the feed means are such that each radiating aperture transmits radiation polarized in said particular direction, which is oriented relative to the set of radiating apertures in such a manner as to maximize the uniformity of the radiation in three dimensions.
9. A source according to claim 8, wherein the polarization direction is chosen so that a straight line segment in that direction passing through the center of the exit plane of the source passes through a minimum number of radiating apertures.
10. A source according to claim 1, wherein the radiating apertures and the feed means are such that the intensity of the transmitted radiation at the periphery of the reflector is approximately 9 dB below the intensity of the transmitted radiation in the central part of the associated reflector.
11. A source according to claim 1, wherein the Ka band is used for transmission and for reception.
12. A source according to claim 11, wherein the transmit frequency is of the order of 20 GHz and the receive frequency is of the order of 30 GHz.
13. A source according to claim 1, wherein the distance between the axes of two adjoining radiating apertures is of the same order as the wavelength of the transmit radiation.
14. A telecommunications system in which calls are relayed by antennas on board a satellite, in particular a geosynchronous satellite, including an antenna with radiating sources each of which is a radiating source according to claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of fabricating a microelectromechanical systems (MEMS) device, comprising:
forming an electrode layer over a substrate;
depositing a sacrificial layer over the electrode layer;
forming a plurality of support structures, said support structures extending through the sacrificial layer, wherein at least some of said plurality of support structures comprise edge support structures;
depositing a mechanical layer over the plurality of support structures;
patterning the mechanical layer to form strips, wherein said strips are separated by gaps, and wherein said gaps are located over a central portion of each of said edge support structures; and
after forming the plurality of support structures, etching a portion of each of said edge support structures underlying the gaps, thereby forming isolated edge support structures.
2. The method of claim 1, wherein etching a portion of each of said edge support structures underlying the gaps comprises etching a central portion of each of said edge support structures to form two isolated edge support structures.
3. The method of claim 1, wherein patterning the mechanical layer to form strips comprises using a mask, and wherein etching a portion of each of said edge support structures comprises using the same mask.
4. The method of claim 1, wherein the patterned mechanical layer is used as a hard mask during the etching of a portion of each of said edge support structures.
5. The method of claim 1, additionally comprising removing said sacrificial material.
6. The method of claim 1, wherein forming a plurality of support structures comprises:
patterning the layer of sacrificial material to form apertures;
depositing a layer of support structure material over the patterned sacrificial layer and into the apertures; and
patterning the layer of support structure material to form support structures.
7. The method of claim 6, wherein patterning the layer of sacrificial material to form apertures comprises patterning the layer of sacrificial material to form tapered apertures.
8. The method of claim 6, additionally comprising depositing a reflective layer over the sacrificial layer prior to patterning the sacrificial layer.
9. The method of claim 6, additionally comprising depositing a reflective layer over the sacrificial layer after patterning the sacrificial layer.
10. The method of claim 9, wherein etching a portion of each of said edge support structures comprises using a plasma etch.
11. The method of claim 9, wherein patterning the layer of support structure material to form support structures comprises using a plasma etch or wet etch.
12. The method of claim 6, wherein patterning the layer of support structure material to form support structures comprises removing portions of the support structure layer located away from the apertures, thereby forming support structures having wing portions which extend horizontally along the sacrificial layer near the apertures.
13. The method of claim 1, wherein the electrode layer comprises indium tin oxide.
14. The method of claim 1, wherein the sacrificial layer comprises molybdenum, silicon, tungsten, or tantalum.
15. The method of claim 1, wherein the support structures comprise a material selected from the group of: SiO2 and SiNx.
16. The method of claim 1, wherein the mechanical layer comprises a material selected from the group of: nickel and aluminum.
17. The method of claim 16, wherein the mechanical layer is used as a hard mask during the etching of the portions of the edge support structures.
18. The method of claim 1, additionally comprising depositing a partially reflective layer over the substrate.
19. The method of claim 18, wherein the partially reflective layer is deposited over the electrode layer.
20. The method of claim 18, wherein the partially reflective layer comprises chromium.
21. The method of claim 1, additionally comprising depositing a dielectric layer over the electrode layer.
22. The method of claim 21, wherein the dielectric layer comprises a material selected from the group of: SiO2 and SiNx.
23. The method of claim 1, additionally comprising depositing a reflective layer over the sacrificial layer.
24. The method of claim 23, wherein the reflective layer comprises a material selected from the group of: aluminum, silver, gold, copper, palladium, platinum, and rhodium.
25. The method of claim 23, additionally comprising etching the reflective layer to remove the portions of the reflective layer located under the gaps in the mechanical layer.
26. A microelectromechanical systems device fabricated by the method of claim 1.