Author: claimsbot

1. A method comprising:
forming a high-kmetal gate stack by:
forming a high-k dielectric layer on a substrate;
forming a work function metal layer on the high-k dielectric layer;
forming a silicide on the work function metal layer; and
forming a polycrystalline silicon (poly Si) layer on the silicide.
2. The method according to claim 1, comprising forming the silicide by:
forming a reactive metal layer in situ on the work function metal layer;
forming an amorphous silicon (a-Si) layer in situ on the entire upper surface of the reactive metal layer; and
annealing concurrently with forming the poly Si layer.
3. The method according to claim 2, comprising forming the work function metal layer including titanium nitride (TiN).
4. The method according to claim 3, comprising forming the reactive metal layer to a thickness of 1 nanometer (nm) to 3 nm.
5. The method according to claim 4, comprising forming the reactive metal layer including titanium (Ti).
6. The method according to claim 5, comprising forming the reactive metal layer by physical vapor deposition (PVD) including flash evaporation.
7. The method according to claim 6, comprising forming the a-Si layer to a thickness of 5 nm to 10 nm.
8. The method according to claim 7, comprising forming the a-Si layer by PVD.
9. The method according to claim 8, further comprising surface cleaning the a-Si layer prior to forming the poly Si layer.
10. The method according to claim 9, comprising surface cleaning the a-Si layer using hydrogen fluoride (HF).
11. The method according to claim 10, comprising surface cleaning the a-Si layer using HF within no more than 8 hours after forming the a-Si layer.
12. The method according to claim 11, comprising forming the poly Si layer by low-pressure chemical vapor deposition (LPCVD) at a temperature greater than 550\xb0 C.
13. The method according to claim 12 comprising forming the poly Si layer to a thickness of 15 nm to 200 nm.
14. The method according to claim 2, further comprising:
forming a high-kmetal gate by patterning and etching the high-kmetal gate stack; and
forming sourcedrain regions on opposite sides of the high-kmetal gate.
15. A device comprising:
a substrate;
a gate electrode stack formed on the substrate, the gate electrode stack comprising:
a high-k dielectric layer formed on the substrate;
a work function metal layer formed on the high-k dielectric layer;
a silicide layer formed on the work function metal layer;
an amorphous silicon (a-Si) layer formed on the silicide layer and covering the entire upper surface of the silicide layer; and
a polycrystalline silicon (poly Si) layer formed on the a-Si layer; and

sourcedrain regions formed on opposite sides of the gate electrode stack.
16. The device according to claim 15, wherein the work function layer includes titanium nitride (TiN).
17. The device according to claim 16, wherein the silicide comprises titanium silicide (TiSi).
18. The device according to claim 17, wherein the silicide has a thickness of 0.5 nm to 3 nm.
19. The device according to claim 18, wherein the poly Si layer has a thickness of 15 nm to 210 nm.
20. A method comprising:
forming a high-kmetal gate stack by:
forming a high-k dielectric layer on a substrate;
forming a work function metal layer including TiN to a thickness of 0.5 nm to 10 nm on the high-k dielectric layer;
forming a reactive metal layer including Ti in situ by PVD including flash evaporation to a thickness of 1 nm to 3 nm on the work function metal layer;
forming an amorphous silicon (a-Si) layer in situ by PVD to a thickness of 5 nm to 10 nm on the entire upper surface of the reactive metal layer;
surface cleaning the a-Si layer using HF within no more than 8 hours after forming the a-Si layer; and
forming a polycrystalline silicon (poly Si) layer by LPCVD at a temperature greater than 550\xb0 C. to a thickness of 15 nm to 200 nm on the a-Si layer;

forming a high-kmetal gate by patterning and etching the high-kmetal gate stack; and
forming sourcedrain regions on opposite sides of the high-kmetal gate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A single chip having multiple different devices integrated thereon for a common purpose, the chip comprising:
a silicon substrate having a peripheral area, a mid-chip area, and a central area;
a plurality of field effect transistors formed in the peripheral area, each field effect transistor having a layer including a rare earth in at least one of a conductive channel, a gate insulator, or a gate stack;
a plurality of photonic devices including at least one of light emitting diodes and vertical cavity surface emitting lasers formed in the mid-chip area, each photonic device having a layer including a rare earth; and
a plurality of photo detectors formed in the central area.
2. A chip as claimed in claim 1 wherein the silicon substrate includes one of a semiconductor-on-insulator (SOI) silicon substrate or a substrate including signal andor ground planes with double buried insulator layers.
3. A chip as claimed in claim 1 wherein the plurality of field effect transistors include double gate field effect transistors.
4. A chip as claimed in claim 1 wherein the plurality of field effect transistors are incorporated into driver circuits.
5. A chip as claimed in claim 1 wherein the plurality of field effect transistors are incorporated into AD or DA circuits.
6. A chip as claimed in claim 1 wherein the plurality of field effect transistors have gate insulators including a single crystal rare earth oxide, a rare earth nitride, a rare earth phosphide, or combinations thereof.
7. A chip as claimed in claim 1 wherein the plurality of field effect transistors have gate stacks including a single crystal rare earth dielectric.
8. A chip as claimed in claim 1 wherein the common purpose of the chip is analysis and the chip further includes a liquid retaining wall surrounding the central area for receiving therein a liquid to be analyzed.
9. A chip as claimed in claim 1 wherein the plurality of photonics devices include PiN diodes.
10. A chip as claimed in claim 1 wherein the layer including a rare earth of the photonic devices includes one of a rare earth oxide (RE2O3) and a rare earth silicate (RE2SiO5).
11. A chip as claimed in claim 10 wherein the RE radical in (RE2O3) and in (RE2SiO5) includes (Gd0.9Er0.1).
12. A single chip having multiple different devices integrated thereon for a common purpose, the chip comprising:
a substrate;
a contact layer of single crystal semiconductor material positioned on the substrate, the contact layer including an area having a doped portion and an overlying differently doped portion;
a first insulating layer epitaxially deposited on the contact layer and including one of a single crystal rare earth oxide and a single crystal rare earth silicate;
a first single crystal layer of doped semiconductor material epitaxially deposited on the first insulating layer;
a second insulating layer epitaxially deposited on the first single crystal layer of doped semiconductor material and including one of a single crystal rare earth oxide and a single crystal rare earth silicate;
a second single crystal layer of doped semiconductor material epitaxially deposited on the second insulating layer;
the second single crystal layer of doped semiconductor material in conjunction with the second insulating layer and the first single crystal layer of doped semiconductor material defining at least one field effect transistor, the first layer of semiconductor material, the first insulating layer, and the contact layer defining at least one photonics device, and the doped portion and the overlying differently doped portion of the contact layer defining at least one photodetector.
13. A chip as claimed in claim 12 wherein the one of single crystal rare earth oxide and the single crystal rare earth silicate included in the first and second insulating layers include (RE2O3) and (RE2SiO5), respectively.
14. A chip as claimed in claim 13 wherein the RE radical in (RE2O3) and in (RE2SiO5) includes (Gd0.9Er0.1).
15. A chip as claimed in claim 12 wherein the first single crystal layer of doped semiconductor material includes one of silicon and germanium.

1. Process for co-production of paraxylene and metaxylene andor orthoxylene from a feedstock that contains xylenes, ethylbenzene and C9-C10 hydrocarbons, whereby the process successively comprises:
A passage of feedstock (1) in a column (2) for distillation of xylenes from where a mixture (3) that comprises the majority of metaxylene, paraxylene, ethylbenzene and at least a portion of orthoxylene is drawn off at the top, and from where a flow (4) of C9-C10 hydrocarbons and the remaining portion of orthoxylene is drawn off at the bottom;
A separation of top mixture (3) in a simulated moving bed in at least one chromatographic column (9) containing a number of beds of an adsorbent that are interconnected in a closed loop and having a different selectivity for paraxylene, ethylbenzene, metaxylene and orthoxylene, whereby said column comprises at least five zones that are delimited by injections of mixture (3) (adsorption feedstock) and a desorbent (8) and draw-offs of an extract (10) that contains paraxylene, an intermediate fraction (11) that contains ethylbenzene, a raffinate (R2) (12) that contains orthoxylene and metaxylene, whereby a paraxylene desorption zone 1 is included between the injection of the desorbent and the sampling of the extract, whereby a zone 2 for desorption of ethylbenzene, orthoxylene and metaxylene is included between the sampling of the extract and the injection of the adsorption feedstock, whereby a zone 3A for paraxylene adsorption is included between the injection of the feedstock and the draw-off of the intermediate fraction, whereby a zone 3B for ethylbenzene adsorption is included between the draw-off of the intermediate fraction and the draw-off of raffinate (R2), and whereby a zone 4 is included between the draw-off of raffinate (R2) and the injection of desorbent, whereby the process is characterized in that
Raffinate (2) is distilled to eliminate essentially all of the desorbent, and a distilled raffinate (18) is drawn off,
The extract is distilled to recover a paraxylene-enriched fraction (16).

The process is also characterized in that:
Either distilled raffinate (18) is sent at least in part to at least one crystallization zone (27), and metaxylene with a purity of at least 99% is recovered,
Or distilled raffinate (18) is sent at least in part into a second distillation zone (23), a top flow (24) that contains metaxylene and a bottom fraction (25) that contains orthoxylene (24) are recovered, the top flow is crystallized at least in part, metaxylene with a purity of at least 99% is recovered, andor said bottom fraction is crystallized at least in part, and orthoxylene with a purity of at least 98.5% is recovered.
2. A process according to claim 1, in which flow (4) is distilled in a distillation column (5) to produce a high-purity orthoxylene flow (6) at the top and a flow (7) that contains C9-C10 hydrocarbons at the bottom.
3. A process according to one of claim 1, in which the crystallization of metaxylene and the crystallization of orthoxylene are carried out in a single crystallization zone, in runs, to produce metaxylene or orthoxylene separately.
4. A process according to one of claim 1, in which the crystallization of metaxylene and the crystallization of orthoxylene are carried out in separate crystallization zones.
5. A process according to one of claim 1, in which a portion of orthoxylene-enriched bottom fraction (25) is isomerized in at least one isomerization zone, and the isomerate that is obtained is recycled in distillation column (2).
6. A process according to one of claims 1, in which the adsorbent that is used in the separation stage is a barium-exchanged X zeolite or a potassium-exchanged Y zeolite or a barium- and potassium-exchanged Y zeolite.
7. A process according to one of claims 1, in which the desorbent is selected from among paradiethylbenzene, toluene, paradifluorobenzene or mixed with diethylbenzenes.
8. A process according to one of claims 1, in which the volumetric ratio of desorbent to adsorption feedstock is between 0.5 and 2.5.
9. A process according to claim 1, in which the separation stage is conducted at a temperature that is generally between 20\xb0 C. and 250\xb0 C., and under a pressure that is between the bubble pressure of xylenes at the operating temperature and 20 bar.
10. A process according to claim 1, in which to produce high-purity metaxylene, the flow rates of zones 3A and 3B as well as the distillation of orthoxylene in column (2) andor second column (23) are regulated to obtain as a crystallization feedstock an effluent that is essentially free of ethylbenzene and desorbent, with a molar composition that is delimited by the four points: pure metaxylene, eutectic binary metaxylene-paraxylene (metaxylene 87.0%, paraxylene 13.0%), eutectic ternary meta-ortho-paraxylene (metaxylene 61.4%, orthoxylene 30.5%, paraxylene 8.1%), and eutectic binary meta-orthoxylene (metaxylene 66.6%, orthoxylene 33.4%).
11. A process according to claim 1, in which at least a portion of paraxylene-enriched fraction (16) feeds a crystallization batch vat to obtain, in runs, after passage into crystallization zone (27), a paraxylene flow (28) at at least 99.90%.
12. A process according to claim 1, in which to produce orthoxylene, the flow rates of zones 3A and 3B as well as the distillation of orthoxylene in column (2) andor second column (23) are regulated to obtain as a crystallization feedstock an effluent that is essentially free of ethylbenzene and desorbent, with a molar composition that is delimited by the four pure orthoxylene points: eutectic binary orthoxylene-paraxylene (orthoxylene 75.7%, paraxylene 24.3%), eutectic ternary meta-ortho-paraxylene (metaxylene 61.4%, orthoxylene 30.5%, paraxylene 8.1%), and eutectic binary meta-orthoxylene (metaxylene 66.6%, orthoxylene 33.4%).
13. A process according to claim 1, in which the crystallization zone or zones comprise at least one crystallizer and in which a refrigeration unit is used to operate at a temperature of between \u221245\xb0 C. and \u221260\xb0 C. in the case where it is sought to produce metaxylene, between \u221220\xb0 C. and \u221260\xb0 C. in the case where it is sought to produce orthoxylene and between 20\xb0 C. and \u221250\xb0 C. in the case where it is sought to produce paraxylene and in which the mother liquor that is separated from the crystals is entrained to a storage vat after the crystallization stage to be recycled in the isomerization unit.
14. A process according to claim 1, in which the chromatographic column contains at least 24 beds, including at least 3 beds in zone 3B.
15. A process according to claim 1, in which fraction (16) is enriched with paraxylene at at least 50% purity and is sent into at least one crystallization zone to deliver paraxylene crystals and a mother liquor, the crystals are separated from the mother liquor, optionally resuspended, washed and recovered, and the mother liquor is recycled in the chromatographic column.
16. A process according to claim 8, wherein said volumetric ratio is between 1.4 and 1.7.
17. A process according to claim 9, wherein said temperature is between 90\xb0 C. and 210\xb0 C.
18. A process according to claim 9, wherein said temperature is between 160\xb0 C. and 200\xb0 C.
19. A process according to claim 1, wherein distilled raffinate (18) is sent at least in part to at least one crystallization zone (27), and metaxylene with a purity of at least 99% is recovered.
20. A process according to claim 1, wherein distilled raffinate (18) is sent at least in part into a second distillation zone (23), a top flow (24) that contains metaxylene and a bottom fraction (25) that contains orthoxylene (24) that contains metaxylene and a bottom fraction (25) that contains orthoxylene (24) are recovered, the top flow is crystallized at least in part, metaxylene with a purity of at least 99% is recovered, andor said bottom fraction is crystallized at least in part, and orthoxylene with a purity of at least 98.5% is recovered.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of power control for a wireless terminal comprising the steps of:
receiving at least one input parameter indicative of a transmission power level;
generating a control parameter based on the at least one input parameter; and
regulating an output transmission power level of the wireless terminal based on the control parameter.
2. The method of claim 1, wherein the at least one input parameter is associated with transmission power level characteristics of a received signal.
3. The method of claim 1, wherein the at least one input parameter is associated with power fading characteristics of a received signal.
4. The method of claim 1, wherein the output transmission power level is regulated based on a predetermined minimum power level.
5. The method of claim 1, wherein the output transmission power level is regulated relative to the transmission power level indicated by the received input parameter.
6. The method of claim 1, further comprising regulating at least one power level controller based on the control parameter.
7. The method of claim 6, wherein the at least one power level controller is associated with at least one digital polar modulator for regulating the output transmission power level of the wireless terminal.
8. The method of claim 1, wherein the wireless terminal is a radiotelephone handset.
9. The method of claim 1, wherein the wireless terminal is a base station.
10. An apparatus for power control in a wireless terminal comprising:
a receiver for receiving at least one input parameter indicative of a transmission power level;
a processor for generating a control parameter based on the at least one input parameter; and
a controller for regulating an output transmission power level of the wireless terminal based on the control parameter.
11. The apparatus of claim 10, wherein the at least one input parameter is associated with transmission power level characteristics of a received signal.
12. The apparatus of claim 10, wherein the at least one input parameter is associated with power fading characteristics of a received signal.
13. The apparatus of claim 10, wherein the output transmission power level is regulated by the controller based on a predetermined minimum power level.
14. The apparatus of claim 10, wherein the output transmission power level is regulated relative to the transmission power level indicated by the received input parameter.
15. The apparatus of claim 10, further comprising the processor sending a control parameter to each of a plurality of controllers.
16. The method of claim 15, wherein each of the plurality of controllers is associated with at least one digital polar modulator for regulating the output transmission power level of the mobile terminal.
17. The method of claim 10, wherein the wireless terminal is a radiotelephone handset.
18. The method of claim 10, wherein the wireless terminal is a base station.
19. A computer-readable medium having computer executable instructions for performing steps comprising:
determining at least one parameter indicative of a power level of a transmitting wireless terminal;
generating a control parameter based on the at least one parameter; and
regulating an output transmission power level of a receiving wireless terminal based on the control parameter.
20. The computer-readable medium of claim 19, wherein the at least one input parameter is associated with power fading characteristics of the transmitting wireless terminal.