Author: claimsbot

1. A sanitary component, namely a stream regulator or stream former for flowing fluid media, comprising property-defining constructional elements which are arranged in a sandwich-like manner in the direction of flow and comprise at least one wire-mesh screen attachment, a diffuser plate system and a shell body with stream-forming segments extending over the cross-sectional area thereof and provided with openings,
wherein the property-defining constructional elements are exchangeable and combinable, for which purpose fixing means are arranged on or in the shell body and corresponding fixing means are arranged on the diffuser plate system, the diffuser plate system is provided, at least on its outside, with an optical coding specifying the flow rate class and the shell body with an optical coding defining the flow type, and wherein the wire-mesh screen attachment is connected to the diffuser plate system wherein, if a flow regulator is inserted between the wire-mesh screen attachment and the diffuser plate system, said wire-mesh screen attachment is formed to be translucent or transparent and said flow regulator has another optical coding, and, if there is no flow regulator, an optical coding of the wire-mesh screen attachment is formed to match with that of the diffuser plate system or is provided in a predefined combination.
2. The sanitary component according to claim 1, wherein the optical codings are each formed as different color codings.
3. The sanitary component according to claim 2, wherein the color shades or color differences of the respective codings comprise color temperatures visually detectable by means of opto-electronic image detection and evaluation and without auxiliary devices.
4. The sanitary component according to claim 1, wherein the color codes for the wire-mesh screen attachment comprise the colors blue, ivory, green, brown, olive, red, beige, black, pink, lilac and white if there is a non-conformity with the code of the diffuser plate system.
5. The sanitary component according to claim 2, wherein the color codes for the flow regulator comprise ten colors, namely light green, dark grey, green, lilac, dark blue, pink, orange, black, yellow and white.
6. The sanitary component according to claim 2, wherein the color codes for the diffuser plate system comprise at least eleven colors, namely dark green, burgundy, light green, light blue, yellow, dark blue, dark grey, light grey, grey, orange and neutral.
7. The sanitary component according to claim 5, wherein the wire-mesh screen attachment comprises the color codes dark green, burgundy, light green, light blue, yellow, dark blue, dark grey, light grey, grey or orange.
8. The sanitary component according to claim 2, wherein the color codes for the shell body comprise at least two colors, wherein a first color is assigned to a shell body with air supply slots provided therein and a second color is assigned to a shell body without air supply slots.
9. The sanitary component according to claim 8, wherein the first color is dark grey and the second color is light grey, wherein the shell body is dye-penetrated and made of a colored synthetic material.
10. The sanitary component according to claim 2, wherein the shell body comprises a pivotable shell base as flow rectifier on the outflow side, wherein this pivotable base has another color code.
11. The sanitary component according to claim 10, wherein the other color code deviates from the color codes for the shell body.
12. The sanitary component according to claim 2, wherein a coating made of an elastomeric material is provided on the outer outflow side of the shell body or the flow rectifier provided therein.
13. The sanitary component according to claim 12, wherein the coating is colored or has a color code andor the elastomeric properties of the coating allow a haptic coding.
14. The sanitary component according to claim 1, wherein the flow regulator comprises a control gap the flow cross-section of which can be altered by means of a ring elastically deformable under the pressure of the flowing fluid medium, wherein the transparency of the wire-mesh screen attachment is chosen such that the flow regulator itself and also the position of the deformable ring is recognizable.
15. The sanitary component according to claim 14, wherein the elastic ring likewise comprises an optically recognizable coding, especially a color coding, which is in contrast with the control gap or the surroundings thereof.
16. The sanitary component according to claim 1, wherein the wire-mesh screen attachment has a convex or conical shape on the inflow side.
17. The sanitary component according to claim 16, wherein the wire-mesh screen attachment comprises polygonal wire-mesh screen openings and an annular collar interlocking with the internal recess of the circular diffuser plate system.
18. The sanitary component according to claim 1, wherein the wire-mesh screen attachment, the diffuser plate system and the shell body have a circular cross-section.
19. The sanitary component according to claim 1, wherein the shell body comprises a male thread so that it may directly be screwed into a complementary female thread of an outflow faucet, wherein a sealing ring provided on the shell body comprises a code, especially a color code, as to define the thread type andor the thread pitch of the male thread.
20. A method of producing a sanitary component, namely a stream regulator or stream former for flowing fluid media, comprising of property-defining constructional elements which are arranged in a sandwich-like manner in the direction of flow and comprise at least one wire-mesh screen attachment, a diffuser plate system or diffuser and a shell body with stream-forming segments extending over the cross-sectional area thereof and provided with openings, wherein, for achieving an adaptability to most different user and application requirements, the property-defining constructional elements are exchangeable and combinable and locking means are arranged on or in the shell body and corresponding counter-locking means are arranged on the diffuser plate system, the diffuser plate system is provided, at least on its outside, with an optical coding specifying the flow rate class and the shell body with an optical coding defining the flow type,
wherein the wire-mesh screen attachment is connected to the diffuser plate system wherein, if a flow regulator is inserted between the wire-mesh screen attachment and the diffuser plate system, said wire-mesh screen attachment is formed to be translucent or transparent and said flow regulator has another optical coding, and, if there is no flow regulator, an optical coding of the wire-mesh screen attachment is formed to match with that of the diffuser plate system or is provided in a predefined combination, wherein, on the basis of customer specific requirements about the desired flow rate class and the respective stream pattern andor flow rate, the coding of those property-defining constructional elements corresponding to said customer-specific requirements or largely approximating the same is inferred from a code table so as to carry out the procurement of the constructional elements from a store and the assembly thereof without errors and in a controlled manner.
21. The method according to claim 20, wherein the control of the production and the quality assurance of the sanitary components are accomplished by means of picture recording and computer-aided image processing, wherein predefined colors with different color temperatures are used for the respective codes.
22. A method of using of a sanitary component, namely a stream regulator or stream former for flowing fluid media, comprising of property-defining constructional elements which are arranged in a sandwich-like manner in the direction of flow and comprise at least one wire-mesh screen attachment, a circular diffuser plate system and a cylindrical shell body with stream-forming segments extending over the cross-sectional area thereof and provided with openings,
wherein, for achieving an adaptability to most different user and application requirements, the property-defining constructional elements are exchangeable and combinable, for which purpose locking means are arranged on the inner circumference of the shell body and corresponding counter-locking means are arranged on the outer circumference of the circular diffuser plate system, the circular diffuser plate system is provided, at least on its outside, with an optical coding specifying the flow rate class and the shell body with an optical coding defining the flow type,
wherein the wire-mesh screen attachment is inserted in a surrounding internal recess of the circular diffuser plate system, wherein, if a flow regulator is inserted between the wire-mesh screen attachment and the diffuser plate system, said wire-mesh screen attachment is formed to be translucent or transparent and said flow regulator has another optical coding, and, if there is no flow regulator, an optical coding of the wire-mesh screen attachment is formed to match with that of the diffuser plate system or is provided in a predefined combination,
by means of a code table authorized by the producer, indicating the optical coding of the constructional elements identifiable without disassembling them, which corresponds to or largely approximates the respective case of use with respect to the stream pattern, flow rate restriction andor flow rate class.
23. The method according to claim 22, wherein the codings are adapted to be colors with different color temperatures.
24. A method of offering for sale a sanitary component, namely a stream regulator or stream former for flowing fluid media, comprising of property-defining constructional elements which are arranged in a sandwich-like manner in the direction of flow and comprise at least one wire-mesh screen attachment, a circular diffuser plate system and a cylindrical shell body with stream-forming segments extending over the cross-sectional area thereof and provided with openings, said method comprising:
providing a code table authorized by a producer, indicating an optical coding of the constructional elements identifiable without disassembling them, which corresponds to or largely approximates the respective case of use with respect to the stream pattern, flow rate restriction andor flow rate class.
25. The method according to claim 24, wherein the property-defining constructional elements are exchangeable and combinable, for which purpose locking means are arranged on the inner circumference of the shell body and corresponding counter-locking means are arranged on the outer circumference of the circular diffuser plate system, the circular diffuser plate system is provided, at least on its outside, with the optical coding specifying the flow rate class and the shell body with an optical coding defining the flow type.
26. The method according to claim 24, wherein the wire-mesh screen attachment is inserted in a surrounding internal recess of the circular diffuser plate system, wherein, if a flow regulator is inserted between the wire-mesh screen attachment and the diffuser plate system, said wire-mesh screen attachment is formed to be translucent or transparent and said flow regulator has another optical coding, and, if there is no flow regulator, an optical coding of the wire-mesh screen attachment is formed to match with that of the diffuser plate system or is provided in a predefined combination.
27. The method according to claim 24, wherein the codings are adapted to be colors with different color temperatures.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-10. (canceled)
11. A light-emitting device comprising:
a substrate;
a transistor formed over the substrate;
an insulating film formed over the transistor; and
a light-emitting element formed over the insulating film, electrically connected to the transistor, and comprising a first electrode, a second electrode, and a light-emitting layer interposed therebetween,
wherein the light-emitting layer comprises a pyran derivative represented by the following general formula,
and
wherein R1 is an alkoxy group.
12. The light-emitting device according to claim 11, wherein R1 is a methoxy group.
13. The light-emitting device according to claim 11, wherein the light-emitting layer further comprises rubrene.
14. The light-emitting device according to claim 11, wherein the light-emitting layer further comprises tris(8-quinolinolato)aluminum or 9,10-di(2-naphtyl)anthracene.
15. An electronic appliance comprising the light-emitting device according to claim 11.
16. A light-emitting device comprising:
a substrate;
a transistor formed over the substrate;
an insulating film formed over the transistor; and
a light-emitting element formed over the insulating film, electrically connected to the transistor, and comprising a first electrode, a second electrode, and a light-emitting layer interposed therebetween,
wherein the light-emitting layer comprises a pyran derivative represented by the following general formula,
wherein R1 is an alkoxy group,
wherein a temperature difference between a first temperature and a second temperature is within 100\xb0 C. when the Thermogravimetry-Differential Thermal Analysis is applied to the pyran derivative, and
wherein the first temperature is a temperature at the beginning of a weight loss in the pyran derivative, and the second temperature is a temperature at which weight of the pyran derivative reaches 50% compared to the weight at the beginning of a weight loss.
17. The light-emitting device according to claim 16, wherein R1 is a methoxy group.
18. The light-emitting device according to claim 16, wherein the light-emitting layer further comprises rubrene.
19. The light-emitting device according to claim 16, wherein the light-emitting layer further comprises tris(8-quinolinolato)aluminum or 9,10-di(2-naphtyl)anthracene.
20. An electronic appliance comprising the light-emitting device according to claim 16.
21. A light-emitting device comprising:
a substrate;
a transistor formed over the substrate;
an insulating film formed over the transistor; and
a light-emitting element formed over the insulating film, electrically connected to the transistor, and comprising a first electrode, a second electrode, and a light-emitting layer interposed therebetween,
wherein the light-emitting layer comprises a first substance having a dipole moment more than 4 debye, a second substance having a hole transportation property, and a pyran derivative represented by the following general formula,
and
wherein R1 is an alkoxy group.
22. The light-emitting device according to claim 21, wherein R1 is a methoxy group.
23. The light-emitting device according to claim 21, wherein the light-emitting layer further comprises rubrene.
24. The light-emitting device according to claim 21, wherein the first substance having a dipole moment more than 4 debye is tris(8-quinolinolato)aluminum.
25. The light-emitting device according to claim 21, wherein the second substance having a hole transportation property is 2,3-bis(4-diphenylaminophenyl)quinoxaline.
26. An electronic appliance comprising the light-emitting device according to claim 21.
27. A light-emitting device comprising:
a substrate;
a transistor formed over the substrate;
an insulating film formed over the transistor;
a light-emitting element formed over the insulating film, electrically connected to the transistor, and comprising a first electrode, a second electrode, and a light-emitting layer interposed therebetween; and
a bank layer formed over the insulating film and covering an edge portion of the first electrode,
wherein the light-emitting layer comprises a pyran derivative represented by the following general formula,
and
wherein R1 is an alkoxy group.
28. The light-emitting device according to claim 27, wherein R1 is a methoxy group.
29. The light-emitting device according to claim 27, wherein the light-emitting layer further comprises rubrene.
30. The light-emitting device according to claim 27, wherein the light-emitting layer further comprises tris(8-quinolinolato)aluminum or 9,10-di(2-naphtyl)anthracene.
31. An electronic appliance comprising the light-emitting device according to claim 27.

1-8. (canceled)
9. A method for producing a sulfide solid electrolyte material comprising steps of:
a providing step of providing a crystallized sulfide solid electrolyte material prepared by using a raw material composition containing Li2S and P2S5; and
an amorphization step of applying amorphization treatment to the crystallized sulfide solid electrolyte material.
10. The method for producing a sulfide solid electrolyte material according to claim 9, wherein the providing step has:
an amorphization treatment step of applying the amorphization treatment to the raw material composition and obtaining an amorphized sulfide solid electrolyte material, and
a crystallization treatment step of applying crystallization treatment by heat treatment to the amorphized sulfide solid electrolyte material and obtaining the crystallized sulfide solid electrolyte material.
11. The method for producing a sulfide solid electrolyte material according to claim 10, wherein a temperature of the heat treatment in the crystallization treatment step is not less than 300\xb0 C.
12. The method for producing a sulfide solid electrolyte material according to claim 9, wherein the providing step is a solid-phase reaction step of producing a solid phase reaction by heat treatment in the raw material composition and obtaining the crystallized sulfide solid electrolyte material.
13. The method for producing a sulfide solid electrolyte material according to claim 9, wherein a ratio of Li2S and P2S5 in the raw material composition is within a range of Li2S:P2S5=70:30 to 80:20 on a molar basis.
14. The method for producing a sulfide solid electrolyte material according to claim 9, wherein a residual amount of Li2S in the crystallized sulfide solid electrolyte material is not more than 1 mol %.
15. The method for producing a sulfide solid electrolyte material according to claim 9, wherein the amorphization treatment in the amorphization step is mechanical milling.
16. A method for producing a lithium solid state battery, which comprises a cathode active material layer containing a cathode active material, an anode active material layer containing an anode active material, and a solid electrolyte layer formed between the cathode active material layer and the anode active material layer, wherein the sulfide solid electrolyte material obtained by the method for producing a sulfide solid electrolyte material according to claim 9 is added to at least one of the cathode active material layer, the anode active material layer, and the solid electrolyte layer contains.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A random access memory (RAM) having a plurality of one-port memory cells and a control logic element operable to manipulate timing of a system clock internal to the RAM to provide a read operation capability and a write operation capability of the RAM during a single cycle of the system clock.
2. The apparatus of claim 1, wherein the random access memory is a static random access memory (SRAM).
3. The apparatus of claim 1, wherein the read operation capability occurs prior to the write operation capability.
4. The apparatus of claim 1, the random access memory further comprising:
a final decode and one or more column muxes, coupled to the plurality of one port memory cells;
one or more sense amps, coupled to the final decode and coupled to the one or more column muxes;
one or more write drivers, coupled to the final decode and coupled to the one or more column muxes;
one or more input registers coupled to the one or more write drivers, said one or more input registers operable to be coupled to one or more input data; and
one or more output registers coupled to the one or more sense amps, said one or more output registers operable to be coupled to one or more output data.
5. The apparatus of claim 4, wherein the one or more output registers are coupled to one or more output drivers prior to being coupled to the one or more output data.
6. The apparatus of claim 4, wherein the control logic element is coupled to one or more of:
the final decode and the one or more column muxes;
the one or more sense amps;
the one or more write drivers;
the one or more input registers; and
the one or more output registers.
7. The apparatus of claim 6, wherein one or more timing signals and one or more control signals of the control logic element are operable to be generated using one or more of a system clock and a delayed system clock.
8. The apparatus of claim 1, the random access memory further comprising:
plurality of bitline precharges and a plurality of rowline drivers, said plurality of bitline precharges and plurality of rowline drivers coupled to the plurality of one port memory cells;
one or more row decoders and one or more column decoders, coupled to the plurality of bitline precharges and the plurality of row drivers; and
one or more address registers, coupled to the one or more row decoders and the one or more column decoders and the plurality of row drivers, said one or more address registers further coupled to a read address and a write address.
9. The apparatus of claim 8, wherein the control logic element is coupled to one or more of:
the plurality of bitline precharges and the one or more rowline drivers;
the one or more row decoders and the one or more column decoders; and
one or more address registers.
10. A random access memory (RAM) capable of performing one or more of a one or more read operations and a one or more write operations during a single cycle of a clock signal, said one or more read operations and one or more write operations further comprising using a plurality of one-port memory cells, wherein a control logic element of the RAM controls a timing of operation of a read functionality of the plurality of one-port memory cells, a write functionality of the plurality of one-port memory cells, a sense amplifier element of the plurality of one-port memory cells to enable a read operation and a write driver element of the plurality of one-port memory cells to enable a write operation.
11. The apparatus of claim 10, wherein the RAM is a static RAM (SRAM).
12. The apparatus of claim 10, wherein the clock signal and one or more control signals of the control logic element are operable to be generated using one or more of a system clock and a delayed system clock.
13. The apparatus of claim 12, wherein the system clock is provided to one or more of:
one or more read enable registers;
one or more write enable registers;
one or more read addresses;
one or more write addresses;
one or more input registers; and
one or more output registers.
14. The apparatus of claim 10, wherein the read functionality further comprises:
a plurality of bitline precharges and a plurality of rowline drivers, said plurality of bitline precharges and plurality of rowline drivers coupled to the plurality of one port memory cells;
one or more row decoders and one or more column decoders, said one or more row decoders coupled to the plurality of rowline drivers and said one or more column decoders coupled to the plurality of bitline precharges;
one or more address registers, coupled to the one or more column decoders and coupled to the one or more row decoders,
said one or more address registers further coupled to a read address and a write address;
one or more sense amps, coupled to the plurality of bitline precharges and coupled to the one or more output registers; and
the one or more output registers operable to be coupled to one or more output data.
15. The apparatus of claim 14, wherein the one or more output registers are coupled to one or more output drivers prior to being coupled to the one or more output data.
16. The apparatus of claim 14, wherein the control logic element is coupled to one or more of:
the plurality of bitline precharges;
the one or more address registers;
the one or more row decoders and the one or more column decoders;
the one or more row drivers;
the one or more sense amps; and
the one or more output registers.
17. The apparatus of claim 10, wherein the write functionality further comprises:
a plurality of bitline precharges and a plurality of rowline drivers, said plurality of bitline precharges and plurality of row drivers coupled to the plurality of one port memory cells;
one or more row decoders and one or more column decoders, coupled to the plurality of rowline drivers and the plurality of bitline precharges;
one or more address registers, coupled to the one or more row decoders and coupled to the one or more column decoders, said one or more address registers further coupled to a read address and a write address;
one or more write drivers, coupled to the plurality of bitline precharges and coupled to one or more input registers; and
the one or more input registers operable to be coupled to one or more input data.
18. The apparatus of claim 17, wherein the control logic element is coupled to one or more of:
the plurality of bitline precharges and the one or more rowline drivers;
one or more address registers;
the one or more row decoders and the one or more column decoders;
the one or more write drivers; and
the one or more input registers.
19. A random access memory (RAM) capable of providing read and write functionality every cycle of a clock signal using a plurality of one-port memory cells, further comprising the clock signal period divided into a plurality of phases and wherein during a first phase of the clock signal period a plurality of bitlines of the plurality of one-port memory cells are pre-charged and a plurality of read addresses supplied to the plurality of one-port memory cells are decoded for a read operation, during a second phase of the clock signal period the plurality of decoded read addresses are enabled for the read operation and selected memory cells of the one-port memory cells drive one or more bitlines and one or more sense amplifiers, during a third phase of the clock signal period the one or more sense amplifiers are isolated from the bitlines of the selected memory cells of the one-port memory cells and enabled to resolve to valid read data, during the third phase one or more bitlines are pre-charged and a plurality of write addresses provided to the plurality of one-port memory cells are decoded to select a wordline and a column location for performing a write operation, and during a fourth phase of the clock signal period the wordline of selected one-port memory cells is enabled for the write operation and a write driver circuit of the write selected one-port memory cells are enabled to write.
20. The apparatus of claim 19, wherein the clock signal is divided into a plurality of phases by a control logic element.
21. The apparatus of claim 19, wherein each phase of the one or more phases is approximately the same temporal duration.
22. The apparatus of claim 19, wherein on a rising edge of the clock signal, one or more of one or more address inputs, one or more data inputs, and one or more control inputs are registered.
23. The apparatus of claim 22, wherein the rising edge occurs in the first phase.
24. The apparatus of claim 20, wherein the clock signal and one or more control signals of the control logic element are operable to be generated using one or more of a system clock and a delayed system clock.
25. A method to provide a read operation capability and a write operation capability of a 1-port random access memory (RAM) during a single cycle of a system clock, comprising:
during a first phase of a plurality of phases of a system clock period, pre-charging a plurality of bitlines of a plurality of one-port memory cells of the RAM, decoding a plurality of read addresses supplied to the plurality of one-port memory cells for a read operation;
during a second phase of the system clock period enabling the plurality of decoded read addresses for the read operation and reading selected memory cells of the plurality of one-port memory cells further comprising driving their corresponding bitlines and a corresponding sense amplifier;
during a third phase of the system clock period isolating the sense amplifier from the bitlines of the read selected memory cells of the one-port memory cells and enabling the sense amplifier to resolve to valid read data, pre-charging the plurality of bitlines and decoding a plurality of write addresses provided to the plurality of one-port memory cells to select a wordline and a column location of write selected memory cells of the one-port memory cells for performing a write operation; and
during a fourth phase of the system clock period enabling the decoded wordline of selected one-port memory cells for the write operation and enabling a write driver circuit of the write selected one-port memory cells to write.
26. The method of claim 25, further comprising dividing the system clock into the plurality of phases by a control element operable to manipulate timing of the system clock internal to the RAM.
27. The method of claim 25, further comprising registering one or more of one or more address inputs, one or more data inputs, and one or more control inputs on a rising edge of the system clock.
28. A method to provide a read operation capability and a write operation capability of a 1-port random access memory (RAM) during a single cycle of a plurality of cycles of a system clock, comprising:
loading a read enable flag and loading a write enable flag; if the read enable flag is not valid and the write enable flag is not valid, further comprising:
maintaining previously read data in one or more output registers;

if the read enable flag is valid and the write enable flag is not valid, further comprising:
loading one or more read addresses;
enabling one or more memory cells of the 1-port RAM to drive a one or more read data corresponding to the one or more read addresses onto one or more output registers;

if read enable flag is valid and write enable flag is valid, further comprising:
loading one or more read addresses;
loading one or more write addresses;
enabling one or more memory cells of the 1-port RAM to drive a one or more read data corresponding to the one or more read addresses onto one or more output registers;
driving a one or more write data corresponding to the one or more write addresses into one or more memory cells of the 1-port RAM;

if read enable flag is not valid and write enable flag is valid, further comprising:
loading one or more write addresses;
driving a one or more write data corresponding to the one or more write addresses into one or more memory cells of the 1-port RAM; and
maintaining previously read data in one or more output registers.
29. The method of claim 28, wherein if a write enable flag is valid, further comprising:
loading the one or more write data after loading the one or more corresponding write addresses;
precharging on or more bitlines;
decoding the one or more write addresses;
enabling one or more rowlines corresponding to the one or more write data; and
driving the one or more write data onto the one or more bitlines.
30. The method of claim 29, wherein if a read enable flag is valid, the one or more read data is read prior to writing the one or more write data.
31. The method of claim 29, wherein if a read enable flag is valid, a first time duration in which the one or more read data is read overlaps a second time duration in which the writing of the one or more write data occurs within a single clock cycle.
32. The method of claim 28, wherein if a read enable flag is valid, further comprising:
precharging one or more bitlines;
decoding the one or more read addresses;
enabling one or more rowlines corresponding to the one or more read addresses;
driving the one or more read data contained in one or more memory cells of the 1-port RAM corresponding to the one or more read addresses onto the one or more bitlines and a one or more enabled sense amplifiers; and
load the one or more read data onto one or more output registers;
33. The method of claim 32, wherein the one or more read data is loaded onto the one or more output registers with a rising clock edge.
34. The method of claim 32, wherein if a write enable flag is valid, the one or more write data is written after reading the one or more read data.
35. The method of claim 32, wherein if a write enable flag is valid, a first time duration in which the one or more write data is written overlaps a second time duration in which the reading of the one or more read data occurs within a single clock cycle.