Author: claimsbot

1. A granulating method for forming a particle from a liquid material by using a continuous ink-jet method comprising the steps of:
a) supplying a liquid material containing a solid component and a binder component into one or more ink-jet nozzles of a continuous ink-jet nozzle;
b) applying fluctuating pressure to eject the supplied liquid material as a continuous liquid flow from the ink-jet nozzles;
c) separating said continuous liquid flow ejected from the ink-jet nozzles to form a droplet;
d) carrying the droplet into a drying means for drying the droplet; and
e) obtaining a granulated particle(s) by drying the carried droplet.
2. The granulating method according to claim 1, which is characterized in that controlling a condition of the liquid flow from the ink-jet nozzle in order to keep a desired droplet diameter while monitoring the formed droplet.
3. The granulating method according to claim 1, which is characterized in that when two or more ink-jet nozzles are used, to set an average diameter of droplet formed from each of the ink-jet nozzles.
4. A granulating method for forming a particle from a liquid material by using a continuous ink-jet method comprising:
supplying a liquid material containing a solid component and a binder component into one or more ink-jet nozzles of a continuous ink-jet nozzle;
forming a droplet by ejecting the supplied liquid material from the ink-jet nozzles;
carrying the droplet into drying means for drying the droplet; and
obtaining a granulated particle(s) by drying the carried droplet, which is

characterized in that when two or more ink-jet nozzles are used, to form the droplet so as to change the component of the droplet formed from each ink-jet nozzle.
5. The granulating method according to claim 1, which is characterized in that the solid component of the liquid material contains one or more components selected from inorganic or organic substances.
6. The granulating method according to claim 1, which is characterized in that the liquid material is used after removing coarse particles by a filter of 500 mesh or more.
7. The granulating method according to claim 1, which is characterized in that the liquid material is used with the viscosity of 500 mPa\xb7s or less.
8. The granulating method according to claim 1, which is characterized in that to add a thickening agent to the liquid material.
9. The granulating method according to claim 1, which is characterized in that the diameter of the ink-jet nozzle is selectively-used in a range of 20 \u03bcm to 120 \u03bcm according to the particle diameter of a granulated particle(s).
10. The granulating method according to claim 1, which is characterized in that eject of the liquid material from the ink-jet nozzle is carried out such that the liquid material is continuously supplied into the ink-jet nozzle and ejected at a constant speed by a supply liquid material pressure, and applying the fluctuation pressure to a liquid material flow passing through the ink-jet nozzle.
11. The granulating method according to claim 1, which is characterized in that using the piezo element and applying pressure to the liquid material flow is made fluctuate based on controlling an applied voltage to the piezo element.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-20. (canceled)
21. A method, comprising:
determining, by a processor and based on a ranking model, a first priority score associated with a first notification and a second priority score associated with a second notification, wherein the ranking model is based at least in part on a plurality of weights, wherein each respective weight from the plurality of weights is associated with a respective characteristic value from a plurality of characteristic values, and wherein the first notification is associated with a first characteristic value from the plurality of characteristic values and the second notification is associated with a second characteristic value from the plurality of characteristic values;
outputting, by the processor and for concurrent display at a display device, the first notification and the second notification, wherein the first notification is graphically emphasized over the second notification based on the first priority score being greater than the second priority score;
receiving, by the processor, an indication of a user input responsive to display of the first notification and the second notification, the user input comprising a selection of the second notification;
responsive to receiving the indication of the user input, modifying the ranking model by decreasing the respective weight associated with the first characteristic value from the plurality of characteristic values relative to the respective weight associated with the second characteristic value from the plurality of characteristic values;
determining, by the processor and based on the ranking model, a third priority score associated with a third notification, wherein the third notification is associated with the second characteristic value from the plurality of characteristic values; and
outputting, by the processor and for concurrent display at the display device, the first notification and the third notification, wherein the third notification is graphically emphasized over the first notification based on the third priority score being greater than the first priority score.
22. The method of claim 21, wherein each respective characteristic value from the plurality of characteristic values represents a value for at least one of source application, sender, time of receipt, and notification content.
23. The method of claim 21, wherein modifying the ranking model is further based on a time at which the indication of user input is received.
24. The method of claim 21, wherein modifying the ranking model is further based on a location of the display device when the indication of user input is received.
25. The method of claim 21, wherein the second notification and the third notification are a same notification.
26. The method of claim 21, wherein the user input corresponds to a command for dismissing the second notification.
27. The method of claim 21, wherein the third notification is represented by a graphic, and wherein graphically emphasizing the third notification comprises enlarging at least a portion of the graphic.
28. The method of claim 21, wherein the first notification, the second notification, and the third notification are each represented by a respective graphic in an ordered list, the relative position of each respective graphic in the ordered list based on the respective priority score associated with the respective notification represented by the respective graphic.
29. The method of claim 21, wherein determining the third priority score is based at least in part on an orientation of the display device.
30. The method of claim 21, wherein determining the third priority score is based at least in part on an application currently being accessed at a computing device associated with the processor.
31. The method of claim 21, wherein determining the third priority score is based at least in part on a last application that was previously accessed at a computing device associated with the processor.
32. The method of claim 21, further comprising requesting explicit user feedback indicative of whether the modifying of the ranking model is correct.
33. A system, comprising:
at least one memory operatively coupled to a processor and configured for storing data and instructions that, when executed by the processor, cause the processor to perform a method comprising:
determining, by a processor and based on a ranking model, a first priority score associated with a first notification and a second priority score associated with a second notification, wherein the ranking model is based at least in part on a plurality of weights, wherein each respective weight from the plurality of weights is associated with a respective characteristic value from a plurality of characteristic values, and wherein the first notification is associated with a first characteristic value from the plurality of characteristic values and the second notification is associated with a second characteristic value from the plurality of characteristic values;
outputting, by the processor and for concurrent display at a display device, the first notification and the second notification, wherein the first notification is graphically emphasized over the second notification based on the first priority score being greater than the second priority score;
responsive to stopping output of the first notification and the second notification, determining, by the processor, an absence of user interaction with the first notification during display of the first notification and the second notification;
responsive to determining the absence of user interaction, modifying the ranking model by decreasing the respective weight associated with the first characteristic value from the plurality of characteristic values relative to the respective weight associated with the second characteristic value from the plurality of characteristic values;
determining, by the processor and based on the ranking model, a third priority score associated with a third notification, wherein the third notification is associated with the second characteristic value from the plurality of characteristic values; and
outputting, by the processor and for concurrent display at the display device, the first notification and the third notification, wherein the third notification is graphically emphasized over the first notification based on the third priority score being greater than the first priority score.
34. The system of claim 33, wherein each respective characteristic value from the plurality of characteristic values represents a value for at least one of source application, sender, time of receipt, and notification content.
35. The system of claim 33, wherein the second notification and the third notification are a same notification.
36. The system of claim 33, wherein the third notification is represented by a graphic, and wherein graphically emphasizing the third notification comprises enlarging at least a portion of the graphic.
37. The system of claim 33, wherein the first notification, the second notification, and the third notification are each represented by a respective graphic in an ordered list, the relative position of each respective graphic in the ordered list based on the respective priority score associated with the respective notification represented by the respective graphic.
38. The system of claim 33, wherein determining the third priority score is based at least in part on a last application that was previously accessed at a computing device associated with the processor.
39. The system of claim 33, the method further comprising requesting explicit user feedback indicative of whether the modifying of the ranking model is correct.
40. A non-transitory computer readable medium that stores instructions that, when executed by a computing device, cause the computing device to perform a method comprising:
determining, by a processor and based on a ranking model, a first priority score associated with a first notification and a second priority score associated with a second notification, wherein the ranking model is based at least in part on a plurality of weights, wherein each respective weight from the plurality of weights is associated with a respective characteristic value from a plurality of characteristic values, and wherein the first notification is associated with a first characteristic value from the plurality of characteristic values and the second notification is associated with a second characteristic value from the plurality of characteristic values;
outputting, by the processor and for concurrent display at a display device, the first notification and the second notification, wherein the first notification is graphically emphasized over the second notification based on the first priority score being greater than the second priority score;
receiving, by the processor, an indication of a user input responsive to display of the first notification and the second notification, the user input comprising a selection of the second notification;
responsive to receiving the indication of the user input, modifying the ranking model by decreasing the respective weight associated with the first characteristic value from the plurality of characteristic values relative to the respective weight associated with the second characteristic value from the plurality of characteristic values;
determining, by the processor and based on the ranking model, a third priority score associated with a third notification, wherein the third notification is associated with the second characteristic value from the plurality of characteristic values; and
outputting, by the processor and for concurrent display at the display device, the first notification and the third notification, wherein the third notification is graphically emphasized over the first notification based on the third priority score being greater than the first priority score.

1. A semiconductor integrated circuit comprising:
a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory;
a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal; and
a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory.
2. The circuit of claim 1, wherein the timing circuit adjusts a timing of at least one of the first and the second data in consideration of a time required for writing the writing data to the memory and a time required for reading out the written data from the memory.
3. The circuit of claim 1, wherein the failure data generation circuit comprises:
a bit inversion circuit configured to decide whether to invert the first data; and
a failure bit setting circuit configured to set whether the bit inversion circuit performs a bit inversion operation based on the failure injection indication signal.
4. The circuit of claim 3, wherein the first data and the second data have a plurality of bits, respectively,
a plurality of bit inversion circuits are provided corresponding to each bit of the first data, and
the failure bit setting circuit controls the plurality of bit inversion circuits to perform the bit inversion operation by turns.
5. The circuit of claim 3, further comprising an address generation circuit configured to generate an address signal for setting a location of the memory to write the first or the second data,
wherein a failure address setting input signal indicative of a specific address to inject failure data in the memory is inputted to the failure bit setting circuit, and
the failure bit setting circuit is configured to control the bit inversion circuits corresponding to the specific address to perform the bit inversion operation when the failure address setting input signal coincides with the address signal generated by the address generation circuit.
6. The circuit of claim 3, wherein the first data and the second data have a plurality of bits, respectively,
a plurality of bit inversion circuits are provided corresponding to each bit of the first data, and
the failure bit setting circuit generates a failure setting signal for setting whether each of the plurality of bit inversion circuits performs the bit inversion operation to based on the failure injection indication signal,
the plurality of bit inversion circuits decides whether to inverse a corresponding bit of the first data according to a value of each bit of the failure setting signal, and
the memory decides whether to perform a writing of the failure data according to the value of each bit of the failure setting signal in units of one bit.
7. The circuit of claim 6, wherein:
the memory has a BWE (Bit Write Enable) terminal of a plurality of bits, the BWE terminal being capable of deciding whether to write data by a unit of a bit, and
the failure setting signal is inputted to the BWE terminal of the memory.
8. The circuit of claim 7 further comprising a result analysis circuit configured to determine whether the BWE terminal of the memory works correctly using the failure setting signal.
9. A circuit function verification device comprising:
a data generation circuit configured to generate first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory having a redundancy part;
a failure data generation circuit configured to generate second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal;
a timing circuit configured to adjust timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory;
a comparison circuit configured to read out data written in the memory to compare the read-out data with the output expected value; and
a passfail determination circuit configured to determine whether at least one failure bit is present in the memory based on a comparison result of the comparison circuit.
10. The device of claim 9, wherein the timing circuit adjusts a timing of at least one of the first and the second data in consideration of a time required for writing the writing data to the memory and a time required for reading out the written data from the memory.
11. The device of claim 9 further comprising:
a repair analysis circuit configured to determine whether the failure bit can be repaired using the redundancy part based on the comparison result of the comparison circuit when at least one failure bit is present in the memory and to generate a repair solution indicative of a location in the redundancy part to replace the failure bit if the failure bit can be repaired; and
a test equipment configured to determine whether the repair analysis circuit works correctly by comparing the repair solution with an expected value of the repair solution generated in advance.
12. The device of claim 9, wherein the failure data generation circuit comprises:
a bit inversion circuit configured to decide whether to invert the first data; and
a failure bit setting circuit configured to set whether the bit inversion circuit performs a bit inversion operation based on the failure injection indication signal.
13. The device of claim 12, wherein the first data and the second data have a plurality of bits, respectively,
a plurality of bit inversion circuits are provided corresponding to each bit of the first data, and
the failure bit setting circuit controls the plurality of bit inversion circuits to perform the bit inversion operation by turns.
14. The device of claim 12 further comprising a address generation circuit configured to generate an address signal for setting a location of the memory to write the first or the second data,
wherein a failure address setting input signal indicative of a specific address to inject failure data in the memory is inputted to the failure bit setting circuit, and
the failure bit setting circuit is configured to control the bit inversion circuits corresponding to the specific address to perform the bit inversion operation when the failure address setting input signal coincides with the address signal generated by the address generation circuit.
15. The device of claim 9 further comprising:
a repair analysis circuit configured to determine whether the failure bit can be repaired using the redundancy part based on the comparison result of the comparison circuit when at least one failure bit is present in the memory and to generate a repair solution indicative of a location in the redundancy part to replace the failure bit if the failure bit can be repaired;
a programming circuit configured to program the repair solution in a memory device;
a transfer circuit configured to transfer the programmed repair solution to the memory; and
a repair control circuit configured to determine whether the repair solution is transferred to the memory correctly.
16. A method of verifying circuit function comprising:
generating first data used for function verification of a built-in self test circuit and a built-in redundancy allocation circuit of a memory having a redundancy part;
generating second data for conducting a built in self test by inverting at least one bit of the first data based on a failure injection indication signal by a failure data generation circuit;
adjusting timing of at least one of the first and the second data in order to use one of the first and the second data as writing data to the memory and to use the other as an output expected value compared with data read out from the memory;
reading out data written in the memory to compare the read-out data with the output expected value; and
determining whether at least one failure bit is present in the memory based on a comparison result.
17. The method of claim 16 further comprising:
determining whether the failure bit can be repaired using the redundancy part based on the comparison result when at least one failure bit is present in the memory;
generating a repair solution indicative of a location in the redundancy part to replace the failure bit if the failure bit can be repaired; and
determining whether a function of generating the repair solution works correctly by comparing the repair solution with an expected value of the repair solution generated in advance.
18. The method of claim 16, wherein the first and the second data have a plurality of bits, respectively, and
upon generating the second data, the second data is generated by inverting each of the plurality of bits by turns.
19. The method of claim 16 further comprising:
generating an address signal for setting a location of the memory to write the first or the second data, and
inputting a failure address setting input signal indicative of a specific address to inject failure data in the memory
wherein upon generating the second data, a bit corresponding to the specific address is inverted when the failure address setting input signal coincides with the address signal.
20. The method of claim 16 further comprising:
determining whether the failure bit can be repaired using the redundancy part based on the comparison result when at least one failure bit is present in the memory;
setting a location in the redundancy part for allocating the failure bit when the failure bit can be repaired; and
verifying whether a replacement to the redundancy part is performed correctly by writing to and reading from the memory.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A nozzle arrangement for an inkjet printhead, the nozzle arrangement comprising:
a substrate assembly incorporating an electrical drive circuitry layer and defining an ink inlet channel;
a nozzle chamber structure extending from the substrate assembly and defining a nozzle chamber in fluid communication with the ink inlet channel and an ink ejection port in fluid communication with the nozzle chamber, the nozzle chamber being rectangular in plan;
an anchor extending from the substrate assembly;
a thermal bend actuator extending from the anchor and electrically coupled to the drive circuitry layer; and
a lever arm coupled to the thermal bend actuator, pivotally supported by the substrate assembly and terminating in a paddle within the nozzle chamber, wherein upon receipt of a driving signal from the drive circuitry layer, the thermal bend actuator bends to induce movement of the paddle and effect ejection of ink in the nozzle chamber through the ink ejection port, and
the paddle has a rectangular profile substantially corresponding to the nozzle chamber.
2. A nozzle arrangement as claimed in claim 1, wherein the lever arm defines a sealing portion which forms part of an ink sealing wall of the nozzle chamber structure.
3. A nozzle arrangement as claimed in claim 1, wherein the paddle is interposed between the ink inlet channel ink and the ejection port.
4. A nozzle arrangement as claimed in claim 1, wherein the nozzle chamber structure defines a protruding rim bounding the ink ejection port.
5. A nozzle arrangement as claimed in claim 4, wherein the nozzle chamber structure further defines a recess positioned about the rim to inhibit ink spread.
6. A nozzle arrangement as claimed in claim 1, wherein the substrate assembly includes an ink passivation layer positioned on the drive circuitry layer.