Author: claimsbot

1. A semiconductor chip, comprising:
a body unit including one or more circuit units;
a first bonding pad disposed on a first face of the body unit in a bonding pad region and connected to a circuit unit of the one or more circuit units; and
a second bonding pad disposed on the first face of the body unit in the bonding pad region so as to be positioned in an adjacent surrounding area of the first bonding pad such that the second bonding pad borders at least one side face of the first bonding pad while being insulated from the first bonding pad, the second bonding pad being connected to a circuit unit of the one or more circuit units.
2. The semiconductor chip according to claim 1, further comprising:
a first insulation layer interposed between the first bonding pad and the second bonding pad to insulate the first bonding pad from the second bonding pad.
3. The semiconductor chip according to claim 1, wherein the first bonding pad has a circular, elliptic or polygonal shape when viewed from the top.
4. The semiconductor chip according to claim 1, wherein the second bonding pad has a closed loop shape of a ring or a rectangle so as to surround the first bonding pad when viewed from the top.
5. The semiconductor chip according to claim 1, wherein the second bonding pad has a \u201cC\u201d shape or an \u201cL\u201d shape to border at least one side face of the first bonding pad when viewed from the top.
6. The semiconductor chip according to claim 1, wherein the first bonding pad and the second bonding pad are disposed in the first face of the body unit in plural pairs, the pair comprising the first bonding pad and the second bonding pad.
7. A semiconductor package, comprising:
a semiconductor chip comprising:
a body unit including one or more circuit units;
a first bonding pad disposed in a first face of the body unit in a bonding pad region and connected to a circuit unit of the one or more circuit units; and
a second bonding pad disposed in the first face of the body unit in the bonding pad region so as to be positioned in an adjacent surrounding area of the first bonding pad such that the second bonding pad borders at least one side face of the first bonding pad while being insulated from the first bonding pad, the second bonding pad being connected to a circuit unit of the one or more circuit units;

a first connection terminal attached onto the first bonding pad; and
a second connection terminal attached onto the second bonding pad and positioned in an adjacent surrounding area of the first connection terminal such that the second connection terminal borders at least one side face of the first connection terminal while being insulated from the first connection terminal.
8. The semiconductor package according to claim 7, further comprising:
a second insulation layer interposed between the first connection terminal and the second connection terminal to insulate the first connection terminal from the second connection terminal.
9. The semiconductor package according to claim 7, further comprising:
a substrate comprising:
a first connection pad disposed in a portion of the substrate corresponding to the first connection terminal that is connected to the first bonding pad; and
a second connection pad disposed in a portion of the substrate corresponding to the second connection terminal that is connected to the second bonding pad, the second connection pad being attached to the second connection pad and positioned in an adjacent surrounding area of the first connection pad such that the second connection pad borders at least one side face of the first connection pad while being insulated with the first connection pad.
10. The semiconductor package according to claim 9, further comprising:
a first insulation layer interposed between the first bonding pad and the second bonding pad to insulate the first bonding pad from the second bonding pad; and
a third insulation layer interposed between the first connection pad and the second connection pad to insulate the first connection pad from the second connection pad.
11. The semiconductor package according to claim 9, wherein the first bonding pad, the first connection terminal and the first connection pad have shapes corresponding to one another; and the second bonding pad, the second connection terminal and the second connection pad have shapes corresponding to one another.
12. The semiconductor package according to claim 9, wherein the first bonding pad, the first connection terminal and the first connection pad each have a circular, elliptic or polygonal shape when viewed from the top.
13. The semiconductor package according to claim 9, wherein the second bonding pad, the second connection terminal and the second connection pad each have a closed loop ring shape or a closed loop rectangle shape so as to surround the first bonding pad, the first connection terminal and the first connection pad, respectively, when viewed from the top.
14. The semiconductor package according to claim 9, wherein the second bonding pad, the second connection terminal and the second connection pad each have a \u201cC\u201d shape or a \u201cL\u201d shape to border at least one side face of the first bonding pad, the first connection terminal and the first connection pad, respectively, when viewed from the top.
15. The semiconductor package according to claim 7, wherein the first bonding pad and the second bonding pad are disposed in the first face of the body unit in plural pairs, the pair comprising the first bonding pad and the second bonding pad.
16. The semiconductor package according to claim 9, wherein the first and second connection pads are disposed in a first face of the substrate that faces the first face of the body unit; and wherein the substrate comprises a first ball land disposed in a second face of the substrate that is opposite to the first face of the substrate and a second ball land disposed in the second face and positioned in an adjacent surrounding area of the first ball land such that the second ball land borders at least one side face of the first ball land while being insulated from the first ball land.
17. The semiconductor package according to claim 16, further comprising:
a fourth insulation layer interposed between the first ball land and the second ball land to insulate the first ball land from the second ball land, wherein the fourth insulation layer is protruded from the first and second ball lands.
18. The semiconductor package according to claim 16, further comprising:
a first external connection terminal attached onto the first ball land, and
a second external connection terminal attached onto the second ball land and positioned in an adjacent surrounding area of the first external connection terminal such that the second external connection terminal borders at least one side face of the first external connection terminal while being insulated from the first external connection terminal.
19. The semiconductor package according to claim 18, further comprising:
a fifth insulation layer interposed between the first external connection terminal and the second external connection terminal to insulate the first external connection terminal from the second connection terminal.
20. The semiconductor package according to claim 18, wherein the first ball land and the first external connection terminal have shapes corresponding to each other, and the second ball land and the second external connection terminal have shapes corresponding to each other.
21. The semiconductor package according to claim 18, wherein the first ball land and the first external connection terminal each have a circular, elliptic or polygonal shape when viewed from the top.
22. The semiconductor package according to claim 18, wherein the second ball land and the second external connection terminal each have a closed loop ring shape or a closed loop rectangle shape so as to surround the first ball land and the first external connection terminal, respectively, when viewed from the top.
23. The semiconductor package according to claim 18, wherein the second ball land and the second external connection terminal each have a \u201cC\u201d shape or a \u201cL\u201d shape to border at least one side face of the first ball land and the first external connection terminal, respectively, when viewed from the top.
24. The semiconductor package according to claim 16, wherein the first ball land and the second ball land are disposed in the first face of the body unit in plural pairs, the pair comprising the first ball land and the second ball land.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A pedal comprising;
(a) a pedal shaft having first and second oppositely disposed ends, and an axis extending through the first end and the second end, the first end being connectable to a bicycle crank;
(b) pedal housing mounted to rotate around said shaft about the axis of said shaft, said housing having top and bottom oppositely disposed sides;
(c) pedal frame pivotally mounted on the housing on a longitudinal axis substantially perpendicular to the axis of the shaft;
(d) housing projection extending transversely from between said top and bottom housing sides, said housing projection having a projection surface directed towards said pedal frame;
(e) pivot stop extending between the pedal frame and said projection surface, wherein the housing projection extends from between the top and bottom housing sides as a means to allow extension of said pivot stop to limit pivotal movement of the pedal frame relative to the pedal housing on said longitudinal axis.
2. The pedal according to claim 1, wherein said pedal frame provides freedom for toe in and toe out pivoting via an attachment means on the pedal frame for connection to a cyclist’s shoe.
3. The pedal according to claim 1, wherein a cushioningdampening means between the projection surface and the pedal frame provides cushioning when the pedal frame is pivoted relative to the projection surface.
4. The pedal according to claim 1, wherein the longitudinal axis pivoting movement is between about 1 and 24 degrees.
5. The pedal according to claim 1, wherein the pedal frame has a top contact surface with clamping means for connection to a cyclist’s shoe.
6. The pedal according to claim 1, wherein the pivot stop is a set screw that threads into the pedal frame and extends from the pedal frame to the projection surface.
7. The pedal according to claim 1, wherein the pivot stop is a set screw that threads into said housing projection and extends from the projection surface to the pedal frame.
8. The pedal according to claim 1, wherein the pivot stop is a solid block fastened to the pedal frame to extend to the projection surface.
9. The pedal according to claim 1, wherein the pivot stop is a solid block fastened to the projection surface to extend towards the pedal frame.
10. The pedal according to claim 1, wherein the pedal housing has a hub that is pivotally mounted to the pedal frame with a clamp.
11. The pedal according to claim 10, wherein said hub is covered by a bushing.
12. The pedal according to claim 10, wherein a ring shaped seal is fit around said hub.
13. The pedal according to claim 1, wherein the pedal frame has a forward cleat retainer and a spring loaded rear cleat retainer to hold the cleat of a cyclist’s shoe.
14. The pedal according to claim 1, wherein the pedal frame has a cleat retainer spring tension adjustment screw.
15. The pedal according to claim 1, wherein the projection surface has connection means to attach to the pivot stop.
16. The pedal according to claim 1, wherein the pedal frame has connection means to attach to the pivot stop.
17. The pedal according to claim 1, wherein the projection surface has a connection means to attach a steel rivot.
18. The pedal according to claim 1, wherein the pedal housing has approximately square top and bottom sides.
19. The pedal according to claim 1, wherein the pedal frame has a pivot stop region oppositely disposed to the projection surface to interface with the pivot stop.

1. A Node B comprising:
circuitry configured to receive a first Iub signal from a radio network controller (RNC) indicating a maximum transmit power level for all channel codes transmitted by the Node B; wherein the circuitry is further configured to receive a second Iub signal from the RNC indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; wherein the circuitry is further configured to transmit at least the HS-DSCH and HS-SCCH codes at a power level that does not exceed the maximum transmit power level for HS-DSCH and HS-SCCH codes of the Node B; and wherein the circuitry is further configured to transmit an Iub signal to the RNC indicating a power associated with the HS-DSCH.
2. The Node B of claim 1 wherein the circuitry is further configured to schedule HS-DSCH transmissions to wireless transmitreceive units (WTRUs).
3. A radio network controller (RNC) comprising:
circuitry configured to transmit a first Iub signal to a Node B indicating a maximum transmit power level for all channel codes transmitted by the Node B; wherein the circuitry is further configured to transmit a second Iub signal to the Node B indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; and the circuitry is further configured to receive an Iub signal from the Node B indicating a power associated with the HS-DSCH.
4. A method, performed by a Node B, of providing high speed downlink packet access (HSDPA) services, the method comprising:
receiving a first Iub signal from a radio network controller (RNC) indicating a maximum transmit power level for all channel codes transmitted by the Node B;
receiving a second Iub signal from the RNC indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B;
transmitting at least the HS-DSCH and HS-SCCH codes at a power level that does not exceed the maximum transmit power level for HS-DSCH and HS-SCCH codes of the Node B; and
transmitting an Iub signal to the RNC indicating a power associated with the HS-DSCH.
5. The method of claim 4 further comprising:
scheduling HS-DSCH transmissions to wireless transmitreceive units (WTRUs).
6. A method, performed by a radio network controller (RNC), of providing high speed downlink packet access (HSDPA) services, the method comprising:
transmitting a first Iub signal to a Node B indicating a maximum transmit power level for all channel codes transmitted by the Node B;
transmitting a second Iub signal to the Node B indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; and
receiving an Iub signal by the RNC from the Node B indicating a power associated with the HS-DSCH.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A circuit for electrostatic discharge clamping, comprising:
a detection module coupled with a first power line of a first power source and a second power line of the first power source, wherein a third terminal of the detection module is coupled to a first power line of a second power source;
a control module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the control module is coupled to a voltage division terminal of the detection module; and
a clamping module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the clamping module is coupled to a fourth terminal of the control module;
wherein the voltage division terminal provides a voltage to the control module according to an electrostatic discharge event on the first power line of the first power source, and the control module then controls the clamping module to couple the first power line of the first power source to the second power line of the first power source.
2. The circuit according to claim 1, wherein the detection module is a resistor, a capacitor, a transistor, or a diode.
3. The circuit according to claim 2, wherein the transistor is a bipolar junction transistor or a field effect transistor.
4. The circuit according to claim 1, wherein a first terminal of the detection module is coupled to a first terminal of a first transistor, a third terminal of the first transistor is coupled to a first terminal of a first resistor, a second terminal of the first resistor is coupled to the first power line of the second power source, and a second terminal of the first transistor is coupled to the voltage division terminal.
5. The circuit according to claim 1, wherein the voltage division terminal is connected with a first terminal of a second resistor, and a second terminal of the second resistor is coupled to the second power line of the first power source.
6. The circuit according to claim 1, wherein the control module coupled between the first power line of the first power source and the second power line of the first power source comprises at least two inverters.
7. The circuit according to claim 6, wherein the at least two inverters comprise a first pair of transistors with opposite polarities and a second pair of transistors with opposite polarities, a third terminal of the first pair of transistors is coupled to the voltage division terminal, a second terminal of the first pair of transistors is coupled to a third terminal of the second pair of transistors, and a second terminal of the second pair of transistors is coupled to the third terminal of the clamping module.
8. The circuit according to claim 1, wherein the clamping module is a second transistor which is coupled with the first power line of the first power source and the second power line of the first power source, a third terminal of the second transistor is coupled to the fourth terminal of the control module, and the second transistor is controlled by the control module.
9. The circuit according to claim 8, wherein the detection module comprises a first transistor and a second resistor, a first terminal of the first transistor is coupled with the first power line of the first power source, a third terminal of the first transistor is electrically connected to the first power line of the second power source, the voltage division terminal is coupled with a first terminal of a second resistor and a second terminal of the first transistor, and a second terminal of the second resistor is coupled with the second power line of the first power source; and when the electrostatic discharge event occurs, the first transistor is in an on state and cooperates with the second resistor, to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
10. The circuit according to claim 1, wherein the detection module comprises a first capacitor and a second capacitor, a first terminal of the first capacitor is coupled to the first power line of the first power source, a second terminal of the second capacitor is coupled to the second power line of the first power source, and a first terminal of the second capacitor coupled to a second terminal of the first capacitor is the voltage division terminal.
11. The circuit according to claim 10, wherein the first capacitor comprises a third transistor, the second capacitor comprises a fourth transistor, polarities of the third transistor and the fourth transistor are opposite, a third terminal of the third transistor coupled to a third terminal of the fourth transistor is the voltage division terminal, a first and a second terminal of the third transistor are coupled to the first power line of the first power source, a first and a second terminal of the fourth transistor are coupled to the second power line of the first power source.
12. The circuit according to claim 10, wherein the voltage division terminal is coupled to a second terminal of a fifth transistor, a first terminal of the fifth transistor is coupled to the first power line of the second power source, and a third terminal of the fifth transistor is coupled to the second power line of the first power source through a third resistor.
13. The circuit according to claim 12, wherein the control module is at least one inverter.
14. The circuit according to claim 13, wherein the inverter comprises a third pair of transistors with opposite polarities, a second terminal of the third pair of transistors is coupled to the third terminal of the clamping module, a third terminal of the third pair of transistors is coupled to the voltage division terminal.
15. The circuit according to claim 12, wherein the clamping module is a second transistor, when the electrostatic discharge event occurs, the fifth transistor is in an off state and cooperates with the first capacitor and the second capacitor to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
16. The circuit according to claim 10, wherein the voltage division terminal is coupled to a second terminal of a sixth transistor, a third terminal of the sixth transistor is coupled to a terminal of a fourth resistor, another terminal of the fourth resistor is coupled to the first power line of the second power source, and a first terminal of the sixth transistor is coupled to the second power line of the first power source.
17. The circuit according to claim 16, wherein the clamping module is a second transistor, when the electrostatic discharge event occurs, the sixth transistor is in an off state and cooperates with the first capacitor and the second capacitor to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
18. The circuit according to claim 1, wherein at least one diode is connected with the first power line of the second power source in series, in order to decrease a voltage difference between a first terminal and a third terminal of a transistor in the detection module.
19. The circuit according to claim 1, wherein the control module is electrically connected to the first power line of the first power source through at least one diode, in order to decrease the voltage received by the control module from the first power source.
20. A method for electrostatic discharge clamping, comprising the following steps:
generating a voltage on a voltage division terminal of a detection module according to an electrostatic discharge event on a first power line of a first power source; and
providing the voltage to a control module for controlling a clamping module;
wherein a third terminal of the detection module is coupled to a first power line of a second power source, and when the control module is driven by the voltage to control the clamping module to be in an on state, the first power line of the first power source couples to a second power line of the first power source.
21. The method according to claim 20, wherein the voltage on the voltage division terminal of a detection module is generated by using resistors or capacitors.