Author: claimsbot

1. A method for reducing leakage power of a system on chip, the method comprising:
monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip, each of the thermoelectric coolers dedicated to a corresponding one of a plurality of chip sections on the SoC; and
controlling the plurality of thermoelectric coolers based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.
2. The method of claim 1, wherein the monitoring the temperature differential comprises determining a junction cold-side temperature of the corresponding chip section and a hot-side temperature of the corresponding thermoelectric cooler.
3. The method of claim 2, further comprising:
if the temperature differential across one of the thermoelectric coolers exceeds a predetermined critical operating point, turning on the corresponding thermoelectric cooler.
4. The method of claim 3, further comprising:
controlling an input current of the corresponding thermoelectric cooler to operate the corresponding thermoelectric cooler at an optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
5. The method of claim 2, further comprising:
controlling an input current of the corresponding thermoelectric cooler to maintain the temperature differential below a predetermined optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
6. The method of claim 5, wherein the predetermined optimal operating point comprises a calculated temperature differential associated with the corresponding chip section.
7. The method of claim 1, wherein the plurality of chip sections comprise one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor, a mobile display processor, and a video encoder.
8. The method of claim 1, wherein the SoC resides on a portable communication device.
9. The method of claim 8, wherein the portable communication devices comprises one of a smart phone, a mobile phone, a tablet computer, and a portable game console.
10. A system for reducing leakage power of a system on chip (SoC), the system comprising:
means for monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC), each of the thermoelectric coolers dedicated to a corresponding one of a plurality of chip sections on the SoC; and
means for controlling the plurality of thermoelectric coolers based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.
11. The system of claim 10, wherein the means for monitoring the temperature differential comprises means for determining a junction cold-side temperature of the corresponding chip section and a hot-side temperature of the corresponding thermoelectric cooler.
12. The system of claim 11, further comprising:
means for turning on the corresponding thermoelectric cooler if the temperature differential across one of the thermoelectric coolers exceeds a predetermined critical operating point.
13. The system of claim 12, further comprising:
means for controlling an input current of the corresponding thermoelectric cooler to operate the corresponding thermoelectric cooler at an optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
14. The system of claim 11, further comprising:
means for controlling an input current of the corresponding thermoelectric cooler to maintain the temperature differential below a predetermined optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
15. The system of claim 14, wherein the predetermined optimal operating point comprises a calculated temperature differential associated with the corresponding chip section.
16. The system of claim 10, wherein the plurality of chip sections comprise one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor, a mobile display processor, and a video encoder.
17. The system of claim 10, wherein the SoC resides on a portable communication device.
18. The system of claim 17, wherein the portable communication devices comprises one of a smart phone, a mobile phone, a tablet computer, and a portable game console.
19. A computer program embodied in a computer-readable medium and executed by a processor for reducing leakage power of a system on chip (SoC), the computer program comprising logic configured to:
monitor a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC), each of the thermoelectric coolers dedicated to a corresponding one of a plurality of chip sections on the SoC; and
control the plurality of thermoelectric coolers based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.
20. The computer program of claim 19, wherein the logic configured to monitor the temperature differential comprises logic configured to determine a junction cold-side temperature of the corresponding chip section and a hot-side temperature of the corresponding thermoelectric cooler.
21. The computer program of claim 20, further comprising logic configured to:
if the temperature differential across one of the thermoelectric coolers exceeds a predetermined critical operating point, turn on the corresponding thermoelectric cooler.
22. The computer program of claim 21, further comprising logic configured to:
control an input current of the corresponding thermoelectric cooler to operate the corresponding thermoelectric cooler at an optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
23. The computer program of claim 20, further comprising logic configured to:
control an input current of the corresponding thermoelectric cooler to maintain the temperature differential below a predetermined optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
24. The computer program of claim 23, wherein the predetermined optimal operating point comprises a calculated temperature differential associated with the corresponding chip section.
25. The computer program of claim 19, wherein the plurality of chip sections comprise one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor, a mobile display processor, and a video encoder.
26. The computer program of claim 19, wherein the SoC resides on a portable communication device.
27. The computer program of claim 19, wherein the portable communication devices comprises one of a smart phone, a mobile phone, a tablet computer, and a portable game console.
28. A system for reducing leakage power of a system on chip (SoC), the system comprising:
a system on chip (SoC) comprising a plurality of chip sections, each chip section having a dedicated and separately controlled thermoelectric cooler; and
a thermoelectric cooler controller comprising logic configured to:
monitor a temperature differential across each of the respective thermoelectric coolers on the SoC; and
control the plurality of thermoelectric coolers based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers on the SoC.
29. The system of claim 28, wherein the logic configured to monitor the temperature differential comprises logic configured to determine a junction cold-side temperature of the corresponding chip section and a hot-side temperature of the corresponding thermoelectric cooler.
30. The system of claim 29, wherein the thermoelectric cooler controller further comprises logic configured to:
if the temperature differential across one of the thermoelectric coolers exceeds a predetermined critical operating point, turn on the corresponding thermoelectric cooler.
31. The system of claim 30, wherein the thermoelectric cooler controller further comprises logic configured to:
control an input current of the corresponding thermoelectric cooler to operate the corresponding thermoelectric cooler at an optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
32. The system of claim 29, wherein the thermoelectric cooler controller further comprises logic configured to:
control an input current of the corresponding thermoelectric cooler to maintain the temperature differential below a predetermined optimal operating point at which a sum of the power consumption of the corresponding chip section and the thermoelectric cooler are minimized.
33. The system of claim 32, wherein the predetermined optimal operating point comprises a calculated temperature differential associated with the corresponding chip section.
34. The system of claim 28, wherein the plurality of chip sections comprise one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor, a mobile display processor, and a video encoder.
35. The system of claim 28, wherein the SoC resides on a portable communication device.
36. The system of claim 35, wherein the portable communication device comprises one of a smart phone, a mobile phone, a tablet computer, and a portable game console.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A lock comprising:
a first half comprising a hollow interior;
a second half comprising a hollow interior and rotatably coupled to the first half, wherein the first half is secured to the second half to prevent access to an item housed within the lock;
a first tube coupled to the first half;
a second tube coupled to the second half and axially aligned with the first tube; a pin passing through the first and second tubes to hingly secure the first half to the second half;
a securing device for preventing unauthorized separation of the first and second halves, wherein the securing device comprises:
a first channel coupled to the first half; and
a second channel coupled to the second half, the first and second channels being aligned when the first half is secured to the second half;
a locking mechanism passing through the first and second channels and located completely within the first and second channels, wherein an interior surface of at least one of the first channel or second channel has a locking member aperture for securing the locking mechanism;
a cover coupled to the lock for covering at least one of the first or second channels to prevent damage to the locking mechanism when the locking mechanism is located completely within the first and second channels; and
a tampering mechanism coupled to one of the first and second halves for preventing insertion of a device between the first and second halves, wherein the tampering mechanism comprises:
a first end coupled to an underside of a top surface of one of the first and second halves; and
a second end proximate an underside of a top surface of an opposing half when the first half is secured to the second half.
2. (canceled)
3. The lock of claim 1 further comprising a collar formed on a bottom surface of the first and second halves.
4. The lock of claim 3 wherein a length of the first and second halves extending below the collar.
5. The lock of claim 3 further comprising a rubber coating applied to the bottom surface of the first and second halves.
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. The lock of claim 1 wherein the cover is coupled to the lock by a leash.
12. (canceled)
13. (canceled)
14. The lock of claim 1 further comprising an interior collar disposed in the hollow interiors of the first and second halves.
15. A lock comprising:
a first half comprising a hollow interior;
a second half comprising a hollow interior and hingably coupled to the first half, wherein the first half is secured to the second half to prevent access to an item housed within the lock;
a collar formed on a bottom surface of the first and second halves;
an interior collar disposed in the hollow interiors of the first and second halves;
a securing device for preventing unauthorized separation of the first and second halves; and
a tampering mechanism coupled to one of the first and second halves for preventing insertion of a device between the first and second halves.
16. The lock of claim 15 wherein the securing device comprises:
a first channel coupled to the first half; and
a second channel coupled to the second half, the first and second channels being aligned when the first half is secured to the second half.
17. The lock of claim 16 further comprising a locking mechanism passing through the first and second channels, and wherein an interior surface of at least one of the first and second channels has a locking member aperture for securing the locking mechanism.
18. The lock of claim 16 further comprising:
a leash coupled to a portion of the lock; and
a cover coupled to the leash for covering at least one of the first or second channels.
19. (canceled)
20. A lock comprising:
a first half comprising a hollow interior;
a second half comprising a hollow interior and hingly coupled to the first half, wherein the first half is secured to the second half to prevent access to an item housed within the lock;
a collar formed on a bottom surface of the first and second halves;
a securing device for preventing unauthorized separation of the first and second halves comprising:
a first channel coupled to the first half; and
a second channel coupled to the second half, the first and second channels being aligned when the first half is secured to the second half;
an amount of rubber coating adhered to the bottom surface of the first and second halves;
a locking mechanism passing through the first and second channels, wherein an interior surface of at least one of the first and second channels has a locking member aperture for securing the locking mechanism;
a leash coupled to a portion of the lock;
a cover coupled to the leash for covering at least one of the first or second channels;
a tampering mechanism coupled at a first end to one of the first and second halves for preventing insertion of a device between the first and second halves when the first half is secured to the second half; and
an interior collar disposed in the hollow interiors of the first and second halves.

1. A p-hydroxyphenylacetic acid salt of amlodipine.
2. The p-hydroxyphenylacetic acid salt of amlodipine as defined in claim 1, wherein the salt is in crystalline form.
3. A method for preparing a p-hydroxyphenylacetic acid salt of amlodipine, comprising the step of reacting amlodipine with p-hydroxyphenylacetic acid in an inert solvent.
4. A pharmaceutical composition for the treatment of ischemic cardiac disorders or hypertension, comprising a therapeutically effective amount of the p-hydroxyphenylacetic acid salt of claim 1, and a pharmaceutically acceptable diluent or carrier.
5. The pharmaceutical composition as defined in claim 4, wherein the composition is in the form of tablets or capsules.
6. The pharmaceutical composition as defined in claim 4, wherein the composition is in the form of solutions or injectables.
7. A pharmaceutical composition for the treatment of ischemic cardiac disorders or hypertension, comprising a therapeutically effective amount of the p-hydroxyphenylacetic acid salt of claim 2, and a pharmaceutically acceptable diluent or carrier.
8. The pharmaceutical composition as defined in claim 7, wherein the composition is in the form of tablets or capsules.
9. The pharmaceutical composition as defined in claim 7, wherein the composition is in the form of solutions or injectables.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computer comprising:
a processor;
storage; and
a logical structure stored in the storage encapsulating multiple data streams, data from said data streams being incorporated in packets, wherein:
the data incorporated in the packets are of a new media type;
the logical structure includes an identifier for the new media type; and
the identifier being used to determine a renderer to use to render data of the new media type; and
a clock license being encapsulated into at least one packet for advancing a clock at a destination when processed at the destination
the computer, utilizing the processor and storage functionality, transmit, the packets of the logical structure on a packet-by-packet basis over a network from the computer to a destination computer.
2. The computer of claim 1, wherein the logical structure holds a field for a maximum packet size and a field for a minimum packet size.
3. The computer of claim 1, wherein the multiple streams of data in the logical structure are Active Stream Format (ASF) data streams.
4. The computer of claim 1, wherein the logical structure holds a value that specifies a maximum bit rate at which the multiple streams of data may be rendered.
5. A system comprising:
a processor;
storage functionally coupled to the processor, wherein a logical structure is stored in the memory, the logic structure encapsulating multiple streams of data, said streams of data being stored in packets, by:
storing samples of data from multiple data streams in the packets;
storing replicas of information in at least some of the packets;
storing error correcting data in the at least some of the packets, wherein the error correcting data identifies an error correcting method for the at least some of the packets; setting a flag in the packets that hold the replicas;
storing in the logical structure a field for a maximum packet size and a field for a minimum packet size; and
encapsulating the packets into the logical structure, wherein at least some of the packets hold the replicas;
storing clock licenses that dictate advancement of a clock in multiple ones of the packets;

the system, utilizing the processor and storage functionality, transmit, the packets of the logical structure on a packet-by-packet basis over a network from the source computer to the destination computer; and
for each packet that holds a clock license, advancing the clock at the destination computer as dictated by the clock license in response to receiving the packet at the destination computer.
6. The system as defined in claim 5, wherein the replicas of information hold property information regarding the samples of data.
7. The system of claim 5 wherein portions of a sample are stored in selected packets and a replica of property information regarding the sample is stored in each packet in which a portion of the sample is stored.
8. The system of claim 5, further comprising the step of examining one of the replicas of information at the destination computer when one of the packets is lost during the transmitting.
9. The system of claim 5, further comprising using the error correcting data in the at least some of the packets to correct an error when the transmitted logical structure is received at the destination.
10. The system as defined in claim 5, wherein the multiple streams of data in the logical structure are Active Stream Format (ASF) data streams.
11. The system of claim 5, wherein:
the logical structure includes a header section and a data section; and
the error correcting data is stored in multiple packets in the data section.
12. The system of claim 11, wherein information in the header section of the logical structure indicates what error correcting methodology is used with the error correcting data stored in the multiple packets in the data section.
13. The system of claim 11, wherein the header section holds information regarding multiple error correcting methods.
14. The system of claim 11, wherein the error correcting data identifies one of a plurality of error correcting methods.
15. The system of claim 11, wherein the error correcting data holds parity bits.
16. A computer comprising:
A processor;
storage; and
a logical structure stored in the storage encapsulating multiple data streams, data from said data streams being of a new media type and incorporated in packets, wherein the logical structure includes an identifier of the new media type from which a renderer can be determined to render the data of the new media type; and
a clock license being encapsulated into at least one packet for advancing a clock at a destination when processed at the destination, wherein:
the streams of data stored in the packets are samples of data from multiple data streams in the packets for transmission on a packet-by-packet basis over a network;
replicas of information are stored in at least some of the packets;
error correcting data is stored in the at least some of the packets;
the error correcting data identifies an error correcting method for the at least some of the packets; and
a flag is stored in each said packet that holds the replicas; and

the computer, utilizing the processor and storage functionality, transmit, the packets of the logical structure on a packet-by-packet basis over a network from the computer to a destination computer.
17. A computer comprising:
a processor;
storage;
a logical structure stored in the storage encapsulating multiple data streams, wherein:
the data from said data streams is incorporated in packets; and
the multiple streams of data in the logical structure are Active Stream Format (ASF) data streams;
a clock license being encapsulated into at least one packet for advancing a clock at a destination when processed at the destination, wherein portions of a sample are stored in selected packets and a replica of property information regarding the sample is stored in each packet in which a portion of the sample is stored; and
the computer, utilizing the processor and storage functionality, transmit, the packets of the logical structure on a packet-by-packet basis over a network from the computer to a destination computer.
18. The computer of claim 17, wherein:
the logical structure includes a header section and a data section, and
the error correcting data is stored in multiple packets in the data section.
19. The computer of claim 18, wherein information in the header section of the logical structure indicates what error correcting methodology is used with the error correcting data stored in the multiple packets in the data section.
20. The data processing system as defined in claim 18, wherein the header section holds information regarding multiple error correcting methods.
21. The computer of claim 18, wherein the error correcting data identifies a plurality of error correcting methods.
22. The computer of claim 18, wherein the error correcting data holds parity bits.
23. The computer of claim 18, wherein the logical structure includes a field for a maximum packet size and a field for a minimum packet size.
24. The computer of claim 18, wherein the multiple streams of data in the logical structure are Active Stream Format (ASF) data streams.
25. The computer of claim 18, wherein the logical structure includes a field for holding a value that specifies a maximum bit rate at which the multiple streams of data may be rendered.
26. The data processing system as defined in claim 18, wherein the logical structure includes a field for an identifier of a new media type for the data from said data streams incorporated in the packets and from which a renderer can be determined to render the data of the new media type.