Author: claimsbot

1. A system for the control of transmit power in a wireless communication device having a transmitter and a receiver, the receiver having a calibrated receiver signal pathway capable of determining the strength of a received signal, the system comprising:
a variable gain radio frequency (RF) transmitter amplifier having an amplifier input and an amplifier output and a variable gain control input, the variable gain control input initially receiving a control signal indicative of a desired transmit power level;
a mixer coupled to the amplifier output and receiving a local oscillator signal having an oscillator frequency corresponding to an operational frequency of the receiver, the mixer generating a signal at operational frequency of the receiver and corresponding to a signal at the amplifier output; and
a coupling circuit to couple the signal generated by the mixer to the receiver signal pathway to permit power measurement of the signal using the calibrated receiver signal pathway.
2. The system of claim 1, further comprising a linearizer containing linearization data indicative of a difference between the control signal indicative of the desired transmit power level and the power measured using the calibrated receiver signal pathway.
3. The system of claim 1 wherein the coupling circuit comprises a switch to couple the signal generated by the mixer to the receiver signal pathway.
4. The system of claim i wherein the receiver signal pathway comprises an intermediate frequency (IF) stage coupled to a demodulator stage, the coupling circuit coupling the signal generated by the mixer to the receiver signal pathway following the IF stage.
5. The system of claim 4, further comprising a bandpass filter intermediate the mixer and the coupling circuit to provide IF filtering.
6. The system of claim 1 wherein the oscillator frequency is selected to permit the signal generated by the mixer to match an intermediate frequency (IF) of the receiver.
7. The system of claim 1 wherein the coupling circuit comprises a single-pole-single-throw (SPST) type switch to couple the signal generated by the mixer to the receiver signal pathway
8. The system of claim 6 wherein the wireless communication device has a transmitter calibration mode, the coupling circuit being selected activated when in the transmitter calibration mode to permit the signal generated by the mixer to be coupled to the receiver signal pathway.
9. The system of claim 1 wherein the coupling circuit comprises a single-pole-double-throw (SPDT) type switch to couple the signal generated by the mixer to the receiver signal pathway.
10. The system of claim 9 wherein the receiver comprises a receiver variable gain amplifier in the receiver signal pathway, the SPDT type switch having a first terminal coupled to the output of the mixer to receiver the signal generated by the mixer, a second terminal coupled to a radio frequency (RF) stage of the receiver and a switch common terminal coupled to the receiver signal pathway.
11. The system of claim 10 wherein the second terminal is coupled to the RF stage via an intermediate frequency (IF) stage wherein the oscillator frequency is selected to permit the signal generated by the mixer to match an intermediate frequency (IF) of the receiver.
12. A method for the control of transmit power in a wireless communication device having a transmitter and a receiver, the receiver having a calibrated receiver signal pathway capable of determining the strength of a received signal, the method comprising:
setting a desired gain level of a variable gain radio frequency (RF) transmitter amplifier;
detecting an output of the variable gain transmitter amplifier indicating an actual gain level;
converting the frequency of the detected output to a frequency corresponding to an operational frequency of the receiver;
coupling the converted signal to the receiver signal pathway to permit power measurement of the signal using the calibrated receiver signal pathway.
13. The method of claim 12, further comprising determining linearization data indicative of a difference between the desired gain level and an actual gain level measured using the calibrated receiver signal pathway.
14. The method of claim 12 wherein the receiver signal pathway comprises an intermediate frequency (IF) stage coupled to a demodulator stage and coupling the converted signal to the receiver signal pathway comprises coupling the converted signal to the receiver signal pathway following the IF stage.
15. The method of claim 12 wherein converting the frequency of the detected output comprises converting the frequency of the detected output to match an intermediate frequency (IF) of the receiver.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A pressure sensor for measuring an external stress comprising:
a) a substrate having:
i) a bottom surface;
ii) a recess formed in the bottom surface of the substrate; and
iii) a top surface having a first area and a second area, the first area is located directly above the recess and the second area is located around the first area; and

b) an apparatus having a first resistor and a second resistor, the first resistor is located on the top surface of the substrate in the first area and the second resistor is located in the top surface of the substrate in the second area surrounding the first area,
wherein, when the pressure sensor is exposed to the external stress, the first resistor measuring the external stress by varying a first oscillating signal input into a first end of the first resistor and outputting a varied first oscillating signal from a second end thereof, and the second resistor receiving an input second oscillating signal in a first end thereof and outputting an output second oscillating signal from a second end thereof, the input second oscillating signal and the output second oscillating signal are unaffected by the external force.
2. A pressure sensor for measuring an external stress comprising:
a) a substrate having:
i) a bottom surface;
ii) a recess formed in the bottom surface of the substrate; and
iii) a top surface having a first area and a second area, the first area is located directly above the recess and the second area is located around the first area; and

b) an apparatus having a first resistor, a second resistor, and a third resistor, the third resistor is on the top surface of the substrate in a middle portion of the first area, the first resistor is located on the top surface of the substrate in the first area and spaced a predetermined distance from the third resistor, and the second resistor is located in the top surface of the substrate in the second area surrounding the first area,
wherein, when the pressure sensor is exposed to the external stress, the first resistor measuring the external stress by varying a first oscillating signal input into a first end of the first resistor and outputting a varied first oscillating signal from a second end thereof, the second resistor receiving an input second oscillating signal in a first end thereof and outputting an output second oscillating signal from a second end thereof, the input second oscillating signal and the output second oscillating signal are unaffected by the external force, the third resistor receiving an input third oscillating signal and outputting an output third oscillating signal decreasing as the external stress increases.

1. A thin film solar cell module of a see-through type having a plurality of cells connected in series on an opaque substrate and a plurality of holes formed in the opaque substrate among the cells, the thin film solar cell module comprising:
the opaque substrate having the holes;
a first electrode disposed on the opaque substrate and composed of a first comb electrode and a two-dimensional array composed of a plurality of block-like first electrodes;
a second electrode disposed above the first electrode and composed of a second comb electrode and a two-dimensional array composed of a plurality of block-like second electrodes, and a portion of the block-like first electrodes, a portion of the opaque substrate, and the holes being exposed between the second comb electrode and the block-like second electrodes,
wherein the second comb electrode and the first comb electrode are disposed symmetrically, and the block-like first electrodes and the block-like second electrodes are disposed by parallel displacement; and
a photoelectric conversion layer disposed between the first electrode and the second electrode,
wherein a top surface and sidewalls of the first electrode around the plurality of holes are covered by the photoelectric conversion layer and not in direct contact with the second electrode, and a top surface and sidewalls of the photoelectric conversion layer around the plurality of holes are covered by the second electrode, and the second electrode and the photoelectric conversion layer do not extend over sidewalls of the plurality of holes in the opaque substrate.
2. The thin film solar cell module of the see-through type of claim 1, wherein the first electrode is a transparent conductive oxide layer or a metal layer.
3. The thin film solar cell module of the see-through type of claim 2, wherein a material of the transparent conductive oxide layer comprises ZnO, SnO2, indium tin oxide (ITO), or In2O3; and a material of the metal layer comprises Al, Ag, Cu, Mo, or an alloy thereof.
4. The thin film solar cell module of the see-through type of claim 1, wherein the photoelectric conversion layer is a single-layered structure or a multi-layered structure.
5. The thin film solar cell module of the see-through type of claim 1, wherein a material of the photoelectric conversion layer comprises amorphous silicon and amorphous silicon alloy, CdS, CuInGaSe2 (CIGS), CuInSe2 (CIS), CdTe, or an organic material.
6. The thin film solar cell module of the see-through type of claim 1, wherein the second electrode is a transparent conductive oxide layer.
7. The thin film solar cell module of see-through type of claim 6, wherein a material of the transparent conductive oxide layer comprises ZnO, SnO2, indium tin oxide (ITO), or In2O3.
8. The thin film solar cell module of the see-through type of claim 6, wherein a plurality of comb-teeth portions of the second comb electrode and the block-like second electrodes arranged in a direction are respectively connected by a plurality of connecting portions.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor structure comprising
a substrate;
a source region formed in the substrate;
a drain region formed in the substrate, the drain region having a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, which is lower than the first doping concentration;
a drain contact in contact with the first drain portion;
a channel region between the source region and the second drain portion, the channel region bordering on the source region and on the second drain portion;
a gate above the channel region; and
a conductive field plate laterally spaced apart from the junction between the channel region and the second drain portion and disposed across the junction between the first drain portion and the second drain portion to reduce a gradient of the electric field at the junction, the field plate being disposed at a distance from the gate and the drain contact.
2. The semiconductor structure according to claim 1, wherein an isolating layer is disposed on the substrate, whereon the field plate is disposed.
3. The semiconductor structure of claim 1, wherein the field plate is disposed on the substrate.
4. The semiconductor structure of claim 1, wherein a voltage can be applied to the field plate.
5. The semiconductor structure of claim 4, wherein the voltage applicable to the field plate is in the range of 20 V to 80 V.
6. The semiconductor structure of claim 5, wherein a breakdown voltage of the drain region is set depending on a voltage applied to the field plate.
7. The semiconductor structure of claim 4, wherein the voltage applicable to the field plate is controlled depending on the drain voltage.
8. The semiconductor structure of claim 1, wherein the first drain portion has an intermediate region with a third doping concentration, which is higher than the second doping concentration and lower than the first doping concentration, the intermediate region being disposed adjacent to the second drain portion.
9. The semiconductor structure of claim 8, wherein the first doping concentration lies in the range of 1\xd71020 atomscm3, the second doping concentration lies in a range of 1\xd71020 atomscm3, and the third doping concentration in the range of 1\xd71017 atomscm3 and 2\xd71020 atomscm3.
10. The semiconductor structure of claim 8, wherein the field plate extends across the intermediate portion.
11. The semiconductor structure of claim 1, wherein the field plate is made of polysilicon.
12. The semiconductor structure of claim 1, wherein the filed plate has a thickness of 0.3 \u03bcm and 1.5 \u03bcm.
13. A semiconductor structure comprising
a substrate;
a source region formed in the substrate;
a drain region formed in the substrate, the drain region having a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, which is lower than the first doping concentration;
a drain contact coupled to the first drain portion;
a channel region between the source region and the second drain portion, the channel region bordering on the source region and on the second drain portion and forming a first junction with the second drain portion;
a gate above the channel region; and
a conductive field plate laterally spaced apart from the first junction between the channel region and the second drain portion and disposed across a second junction between the first drain portion and the second drain portion to reduce a gradient of the electric field at the second junction, the field plate being disposed at a distance from the gate and the drain contact.
14. The semiconductor structure of claim 13, wherein a voltage can be applied to the field plate.
15. The semiconductor structure of claim 14, wherein a breakdown voltage of the drain region is set depending on a voltage applied to the field plate.
16. The semiconductor structure of claim 14, wherein the voltage applicable to the field plate is controlled depending on a voltage applied to the drain.
17. A semiconductor structure comprising
a substrate;
a source region formed in the substrate;
a drain region formed in the substrate, the drain region having a first drain portion with a first doping concentration and an intermediate region with a third doping concentration, which is lower than the first doping concentration, and a second drain portion with a second doping concentration, which is lower than the first doping concentration, and wherein the intermediate region of the first drain portion is disposed adjacent to the second drain portion and the third doping concentration is higher than the second doping concentration;
a drain contact coupled to the first drain portion;
a channel region between the source region and the second drain portion, the channel region bordering on the source region and on the second drain portion and forming a first junction with the second drain portion;
a gate above the channel region; and
a conductive field plate laterally spaced apart from the first junction between the channel region and the second drain portion and disposed across a second junction between the first drain portion and the second drain portion to reduce a gradient of the electric field at the second junction, the field plate being disposed at a distance from the gate and the drain contact.
18. The semiconductor structure of claim 17, wherein the first doping concentration is on the order of 1\xd71020 atomscm3, the second doping concentration is on the order of 1\xd71020 atomscm3, and the third doping concentration is in the range of about 1\xd71017 atomscm3 to about 2\xd71020 atomscm3.
19. The semiconductor structure of claim 17, wherein the field plate extends across the intermediate portion.