What is claimed is:
1. A flow sensor for sensing flow rate of moving crop material within a duct of a harvester, comprising:
a microwave transceiver attached to the harvester for transmitting a transmitted microwave signal and receiving a reflected microwave signal;
an in-phase mixer electrically connected to the microwave transceiver for combining the transmitted microwave signal and the reflected microwave signal and outputting an in-phase Doppler signal;
a quadrature mixer electronically connected to the microwave transceiver for combining the transmitted microwave signal and a delayed reflected microwave signal and outputting a quadrature Doppler signal; and
an electronic circuit electrically connected to the in-phase mixer and the quadrature mixer and having a flow rate output.
2. The flow sensor of claim 1 wherein the electronic circuit further comprises an intelligent control.
3. The flow sensor of claim 2 wherein the intelligent control is a digital signal processor.
4. The flow sensor of claim 2 wherein the intelligent control includes a set of instructions for sampling the in-phase Doppler signal and the quadrature Doppler signal and computing an FFT.
5. A flow sensor system for sensing flow rate of moving crop material, comprising:
a microwave transparent duct for containing flowing crop material;
a microwave transceiver for transmitting a transmitted microwave signal towards the transparent duct and receiving a reflected signal;
an in-phase mixer electrically connected to the microwave transceiver for combining the transmitted microwave signal and the reflected microwave signal and outputting an in-phase Doppler signal;
a quadrature mixer electronically connected to the microwave transceiver for combining the transmitted microwave signal and a delayed reflected microwave signal and outputting a quadrature Doppler signal; and
an electronic circuit electrically connected to the in-phase mixer and the quadrature mixer and having a flow rate output.
6. The flow sensor system of claim 5 wherein the microwave transceiver includes a narrow beam antenna.
7. The flow sensor system of claim 5 wherein the electronic circuit further comprises an intelligent control.
8. The flow sensor system of claim 7 wherein the intelligent control includes a set of instructions for sampling the in-phase Doppler signal and the quadrature Doppler signal and computing a FFT.
9. The flow sensor system of claim 5 further comprising a harvester wherein the transparent duct is mounted on the harvester.
10. The flow sensor of claim 5 wherein the crop material is selected from the set comprising cotton and grain.
11. A method of measuring crop material flow rate within a duct comprising:
transmitting a first microwave signal towards the crop material duct;
receiving a reflected microwave signal;
mixing the first microwave signal and the reflected microwave signal to produce an in-phase Doppler signal;
mixing the first microwave signal and a delayed reflected microwave signal to produce a quadrature Doppler signal;
sampling the in-phase Doppler signal and the quadrature Doppler signal to form a set of complex numbers;
computing a frequency domain spectrum having corresponding amplitude components and phase components;
computing a frequency domain power spectrum; and
summing the products of the components of the power spectrum and their corresponding frequencies to produce a crop material flow rate.
12. The method of claim 11 further comprising summing a plurality of flow rates to compute a net crop material flow rate.
13. The method of claim 11 further comprising compensating the in-phase Doppler signal with the DC offset of the in-phase mixer.
14. The method of claim 11 further comprising compensating the quadrature Doppler signal with the DC offset of the quadrature mixer.
15. The method of claim 11 further comprising comparing the flow rate to a threshold.
16. The method of claim 11 further comprising applying a calibration function to the flow rate.
17. The method of claim 11 wherein the duct is attached to a harvester.
18. The method of claim 17 wherein the crop material is cotton and the harvester is a cotton harvester.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A storage medium for storing a compiler for compiling a source program, said compiler comprising the steps of:
detecting a parallelization directive in said source program; and
if said parallelization directive is detected, generating a front-end intermediate language for said parallelization directive by positioning on a storage region, each processing code of at least part of the parallelization directive with a hierarchical structure in accordance with an internal structure of said parallelization directive.
2. The storage medium according to claim 1, further comprising a step of adding to said front-end intermediate language of a statement to which the parallelization directive is applied, reference information from said front-end intermediate language of said statement to which the parallelization directive is applied, to said front-end intermediate language for the parallelization directive.
3. The storage medium according to claim 1, further comprising a step of, by using a processing table which stores one or a plurality of items of processing information for each of said processing codes, acquiring the processing information corresponding to a current processing content based on said processing code within the front-end intermediate language for said parallelization directive.
4. The storage medium according to claim 3, wherein said current processing content is one of type analysis, syntactic analysis, semantic analysis, and generation of a compiler intermediate language.
5. The storage medium according to claim 1, wherein said hierarchical structure is a list structure.
6. The storing medium according to claim 1, wherein
said part of said parallelization directive comprises a directive, a clause, and a line, and
a processing code for said directive is linked downward to a processing code for said clause, and
said processing code for said clause is linked downward to a processing code for said lines.
7. A compiling method for compiling a source program, said compiling method comprising the steps of:
detecting a parallelization directive in said source program; and
if said parallelization directive is detected, generating a front-end intermediate language for said parallelization directive by positioning on a storage region, each processing code of at least part of the parallelization directive with a hierarchical structure in accordance with an internal structure of said parallelization directive.
8. The compiling method according to claim 7, further comprising a step of adding to said front-end intermediate language of a statement to which the parallelization directive is applied, reference information from said front-end intermediate language of said statement to which the parallelization directive is applied, to said front-end intermediate language for the parallelization directive.
9. The compiling method according to claim 7, further comprising a step of, by using a processing table which stores one or a plurality of items of processing information for each of said processing codes, acquiring the processing information corresponding to a current processing content based on said processing code within the front-end intermediate language for said parallelization directive.
10. The compiling method according to claim 9, wherein said current processing content is one of type analysis, syntactic analysis, semantic analysis, and generation of a compiler intermediate language.
11. The compiling method according to claim 7, wherein said hierarchical structure is a list structure.
12. The compiling method according to claim 7, wherein
said part of said parallelization directive comprises a directive, a clause, and a line, and
a processing code for said directive is linked downward to a processing code for said clause, and
said processing code for said clause is linked downward to a processing code for said lines.
13. A compiling apparatus for compiling a source program, comprising:
means for detecting a parallelization directive in said source program; and
means for generating a front-end intermediate language for said parallelization directive by positioning on a storage region, each processing code of at least part of the parallelization directive with a hierarchical structure in accordance with an internal structure of said parallelization directive if said parallelization directive is detected.
14. The compiling apparatus according to claim 13, further comprising means for adding to said front-end intermediate language of a statement to which the parallelization directive is applied, reference information from said front-end intermediate language of a statement to which the parallelization directive is applied, to said front-end intermediate language for the parallelization directive.
15. The compiling apparatus according to claim 13, further comprising means for, by using a processing table which stores one or a plurality of items of processing information for each of said processing codes, acquiring the processing information corresponding to a current processing content based on said processing code within the front-end intermediate language for said parallelization directive.
16. The compiling apparatus according to claim 15, wherein said current processing content is one of type analysis, syntactic analysis, semantic analysis, and generation of a compiler intermediate language.
17. The compiling apparatus according to claim 13, wherein said hierarchical structure is a list structure.
18. The compiling apparatus according to claim 13, wherein
said part of said parallelization directive comprises a directive, a clause, and a line, and
a processing code for said directive is linked downward to a processing code for said clause, and said processing code for said clause is linked downward to a processing code for said lines.