Author: claimsbot

1. A process for the recovery of drilling fluid additives from a mixture of materials, wherein the mixture comprises drilling fluids, drilled solids, and one or more drilling fluid additives from a mud system, the process comprising:
separating at least a portion of the drilled solids from the mixture to form a first effluent and a drilled solids fraction;
separating at least a portion of the one or more drilling fluid additives from the first effluent to form a second effluent and one or more recovered additives fractions;
recycling at least a portion of the one or more recovered additives fractions to the mud system;
wherein the one or more drilling fluid additives have a specific gravity of at least 1.4; and
wherein the one or more drilling fluid additives have an average particle size of at least 2 microns.
2. The process of claim 1, wherein the one or more drilling fluid additives are selected from the group consisting of industrial carbon, calcium carbonate, cellulose fibers, natural fibers, minerals, polysaccharides, and combinations thereof.
3. The process of claim 1, comprising diluting the first effluent with an internal olefin, a portion of the second effluent, or combinations thereof.
4. The process of claim 1, comprising recycling at least a portion of the second effluent to the active mud system.
5. The process of claim 1, wherein the separating at least a portion of the drilled solids is performed in an apparatus selected from the group consisting of screen separators, hydrocyclones, desilters, desanders, mud cleaners, mud conditioners, dryers, drying shakers, centrifuges, hydrocyclone shakers, multi-deck shakers, and combinations thereof.
6. The process of claim 1, wherein the separating at least a portion of the one or more drilling fluid additives is performed in an apparatus selected from the group consisting of screen separators, hydrocyclones, desilters, desanders, mud cleaners, mud conditioners, dryers, drying shakers, centrifuges, hydrocyclone shakers, multi-deck shakers, and combinations thereof.
7. The process of claim 1, wherein the one or more recovered additives fractions comprise at least 60 weight percent drilling fluid additives.
8. The process of claim 1, wherein the recovered additives fraction comprises at least 80 weight percent drilling fluid additives.
9. The process of claim 1, wherein the recovered additives fraction comprises at least 90 weight percent drilling fluid additives.
10. The process of claim 1, wherein the drilled solids fraction comprises particles having an average particle size of 1000 microns or greater.
11. The process of claim 1, wherein the one or more drilling fluid additives comprise particles having an average particle size in the range of 5 to 1000 microns.
12. The process of claim 1, wherein 50 weight percent or more of the one or more drilling fluid additives in the mixture are recovered in the one or more recovered additives fractions.
13. The process of claim 1, wherein the one or more recovered additives fraction comprises an industrial carbon fraction comprising at least 50 weight percent industrial carbon.
14. The process of claim 1, wherein the one or more recovered additives fraction comprises a calcium carbonate fraction comprising at least 50 weight percent calcium carbonate.
15. The process of claim 1, wherein the one or more recovered additives fraction comprises a fraction comprising at least 50 weight percent of a mixture of minerals, fibers, and polysaccharides.
16. The process of claim 1, wherein the one or more recovered additives fraction comprises a cellulose fiber fraction comprising at least 50 weight percent cellulose fiber.
17. A system for the recovery of drilling fluid additives from a mixture of materials, wherein the mixture comprises drilling fluids, drilled solids, and one or more drilling fluid additives from a mud system, the system comprising:
means for separating at least a portion of the drilled solids from the mixture to form a first effluent and a drilled solids fraction;
means for separating at least a portion of the one or more drilling fluid additives from the first effluent to form a second effluent and a recovered additives fraction;
means for recycling at least a portion of the recovered additives fraction to the mud system;
wherein the one or more drilling fluid additives have a specific gravity of at least 1.4; and
wherein the one or more drilling fluid additives have an average particle size of at least 2 microns.
18. A system for the recovery of drilling fluid additives from a mixture of materials, wherein the mixture comprises drilling fluids, drilled solids, and one or more drilling fluid additives from a mud system, wherein the one or more drilling fluid additives have a specific gravity of at least 1.4 and an average particle size of at least 2 microns, the system comprising:
a first separator for separating at least a portion of the drilled solids from the mixture to form a first effluent and a drilled solids fraction;
a second separator in fluid connection with the first separator, wherein the second separator separates at least a portion of the one or more drilling fluid additives from the first effluent to form a second effluent and one or more recovered additives fraction; and
a fluid connection from the second separator to the mud system for conveying at least a portion of the recovered additives fraction to the mud system.
19. The system of claim 18, wherein the first separator and the second separator are integrated in a single separation apparatus.
20. The system of claim 19, wherein the single separation apparatus is a multi-deck shaker.
21. The system of claim 18, wherein the first separator is selected from the group consisting of screen separators, hydrocyclones, desilters, desanders, mud cleaners, mud conditioners, dryers, drying shakers, centrifuges, hydrocyclone shakers, multi-deck shakers, and combinations thereof.
22. The system of claim 18 wherein the second separator is selected from the group consisting of screen separators, hydrocyclones, desilters, desanders, mud cleaners, mud conditioners, dryers, drying shakers, centrifuges, hydrocyclone shakers, multi-deck shakers, and combinations thereof.
23. The system of claim 18, further comprising a third separator in fluid connection with the second separator, wherein the third separator separates at least a weighting agent from the second effluent to form a third effluent and a weighting agent fraction.
24. The system of claim 23, further comprising a fluid connection from the third separator to the mud system for conveying at least a portion of the weighting agent fraction to the mud system.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A chip package, comprising:
an electrically conducting chip carrier;
at least one semiconductor chip attached to the electrically conducting chip carrier;
an insulating laminate structure embedding the electrically conducting chip carrier and the at least one semiconductor chip; and
a passive electronic device comprising a first structured electrically conducting layer, wherein the first structured electrically conducting layer extends directly on a surface of the laminate structure.
2. The chip package of claim 1, wherein the first structured electrically conducting layer is electrically coupled to a contact pad of the at least one semiconductor chip.
3. The chip package of claim 1, wherein the first structured electrically conducting layer forms a first coil.
4. The chip package of claim 1, wherein the passive electronic device further comprises a second structured electrically conducting layer.
5. The chip package of claim 4, wherein the first structured electrically conducting layer forms a first coil, the second structured electrically conducting layer forms a second coil, and the second coil is electrically coupled to the first coil.
6. The chip package of claim 3, further comprising:
a magnetic core embedded in the insulating laminate structure.
7. The chip package of claim 6, wherein the magnetic core is attached to the electrically conducting chip carrier.
8. The chip package of claim 6, wherein the magnetic core passes through a plane coplanar with a main surface of the electrically conducting chip carrier.
9. The chip package of claim 6, wherein the magnetic core comprises a ferromagnetic material or a high magnetic permeability material.
10. The chip package of claim 1, wherein the first structured electrically conducting layer forms a first plate of a capacitor.
11. The chip package of claim 10, further comprising a high electric permittivity dielectric material applied to the first plate of the capacitor.
12. The chip package of claim 10, wherein a second plate of the capacitor is formed by the electrically conducting chip carrier.
13. The chip package of claim 10, wherein the electrically conducting chip carrier is formed by a first part of a carrier, a second plate of the capacitor is formed by a second part of the carrier, and the first part of the carrier and the second part of the carrier are separated from each other.
14. The chip package of claim 1, wherein the first structured electrically conducting layer forms a resistor.
15. The chip package of claim 1, wherein the at least one semiconductor chip comprises a logic chip and a power chip.
16. A chip package, comprising:
an electrically conducting chip carrier;
at least one semiconductor chip attached to the electrically conducting chip carrier;
an insulating layer extending over the electrically conducting chip carrier;
a passive electronic device comprising a first structured electrically conducting layer, wherein the first structured electrically conducting layer extends over the insulating layer; and
an insulating laminate structure embedding the electrically conducting chip carrier, the at least one semiconductor chip, and the passive electronic device.
17. The chip package of claim 16, wherein the first structured electrically conducting layer is electrically coupled to a contact pad of the at least one semiconductor chip.
18. The chip package of claim 17, wherein the first structured electrically conducting layer forms a first plate of a capacitor.
19. The chip package of claim 18, wherein a second plate of the capacitor is formed by the electrically conducting chip carrier.
20. The chip package of claim 16, wherein the insulating layer comprises a high electric permittivity dielectric material.
21. The chip package of claim 16, wherein the first structured electrically conducting layer forms a resistor.
22. The chip package of claim 16, wherein the at least one semiconductor chip comprises a logic chip and a power chip.

What is claimed is:

1. An air conditioner for a vehicle, comprising:
a compressor for compressing and discharging refrigerant;
an exterior heat exchanger for cooling refrigerant discharged from the compressor in a cooling mode;
an air conditioning case in which air flows toward a passenger compartment;
an interior heat exchanger for cooling air by absorbing heat from air in the cooling mode, the interior heat exchanger being disposed in the air conditioning case to heat air in a heating mode where the refrigerant discharged from the compressor is introduced into the interior heat exchanger through a hot-gas heater cycle while bypassing the exterior heat exchanger;
a switching member disposed to selectively switch one of the cooling mode and the heating mode;
an accumulator for separating refrigerant into gas refrigerant and liquid refrigerant and for storing the separated liquid refrigerant therein, the accumulator being disposed between an outlet of the interior heat exchanger and a suction port of the compressor, wherein:
the accumulator includes a heating device for heating the liquid refrigerant stored in the accumulator.
2. The air conditioner according to claim 1, further comprising
a heating heat exchanger for heating air using hot water from an engine of the vehicle as a heating source, the heating heat exchanger being disposed in the air conditioning case at a downstream air side of the interior heat exchanger,
wherein the compressor is driven by the engine.
3. The air conditioner according to claim 2, wherein the heating device is a hot water pipe into which hot water from the engine is circulated.
4. The air conditioner according to claim 3, wherein the hot water pipe is disposed to heat an outer peripheral surface of the accumulator at a position where the liquid refrigerant is stored.
5. The air conditioner according to claim 1, wherein:
the accumulator includes a tank body in which the liquid refrigerant is stored; and
the heating device is provided to heat an outer peripheral surface of the tank body at a position where the separated liquid refrigerant is stored.
6. The air conditioner according to claim 5, wherein:
the heating device is provided to heat the outer peripheral surface of the tank body and a bottom outer surface of the tank body.
7. The air conditioner according to claim 5, wherein:
the tank body has a cylindrical outer shape.
8. The air conditioner according to claim 1, wherein the heating device is an electric heater.
9. The air conditioner according to claim 8, wherein:
the electric heater includes a heater body having a thin plate shape, and a film member covering the heater body; and
the heater body has an electrical resistance material.
10. The air conditioner according to claim 9, wherein:
the accumulator includes a tank body in which the separated liquid refrigerant is stored;
the tank body has a cylindrical outer peripheral surface; and
the electric heater is cylindrically bent to be attached to the outer peripheral surface of the tank body at a lower side position.
11. The air conditioner according to claim 8, further comprising:
a pressure detection device for detecting pressure of refrigerant at a high-pressure side of the hot-gas heater cycle in the heating mode; and
a heater control unit for controlling an operation state of the electric heater based on the pressure detected by the pressure detection device so that the pressure of refrigerant at the high-pressure side becomes higher than a predetermined pressure.
12. The air conditioner according to claim 1, wherein the accumulator has a tank body in which the separated liquid refrigerant is stored, the air conditioner further comprising:
a surface temperature detection device for detecting an outer surface temperature of the tank body, wherein:
when the temperature detected by the surface temperature detecting device is lower than a predetermined temperature, the heating device heats the liquid refrigerant in the tank body of the accumulator.
13. The air conditioner according to claim 2, further comprising
a water temperature detecting device for detecting temperature of water flowing from the engine to the heating heat exchanger, wherein:
when the temperature detected by the water temperature sensor is lower than a predetermined temperature, the heating device heats the liquid refrigerant in the accumulator.
14. The air conditioner according to claim 1, further comprising
an air temperature detecting device for detecting at least one of an air temperature immediately blown from the interior heat exchanger and an air temperature in the passenger compartment, in the heating mode,
when the air temperature detected by the air temperature detecting device is lower than a predetermined temperature, the heating device heats the liquid refrigerant in the accumulator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A DRAM semiconductor memory device comprising:
a plurality of memory cells, each memory cell including a selection transistor and a storage capacitor, the plurality of memory cells being arranged in a memory cell array with bit lines and word lines, wherein a drain region of each selection transistor is connected to a respective bit line and a gate of each selection transistor is connected to a respective word line;
a plurality of bit lines including at least a pair of first and second bit lines, wherein each of the first and second bit lines includes a memory cell connected to the bit line and a further memory cell connected to the bit line;
a plurality of sense amplifiers including a sense amplifier being connected to the pair of first and second bit lines; and
a driving circuit device connected to the gate of each further memory cell connected to the first and second bit lines, wherein the driving circuit is configured to simultaneously switch on the gates of the further memory cells in response to initiating a precharge operation for charging the pair of first and second bit lines to an equalization voltage.
2. The DRAM semiconductor memory device of claim 1, wherein, during a read operation of the memory cell connected to one of the pair of first and second bit lines, the driving circuit device is configured to turn on the gate of the further memory cell that is connected to the other of the pair of first and second bit lines.
3. The DRAM semiconductor memory device of claim 1, further comprising:
a bit line equalization circuit device that connects a variable voltage source to the pair of first and second bit lines and short-circuits the pair of first and second bit lines during the precharge operation, wherein a resistance of the connection between the voltage source and the pair of first and second bit lines is a plurality of orders of magnitude greater than the resistance between the short-circuited pair of first and second bit lines.
4. The DRAM semiconductor memory device of claim 3, wherein the variable voltage source comprises laser fuses to set an output voltage.
5. The DRAM semiconductor memory device of claim 4, further comprising:
a charge circuit device that charges the storage capacitors of the further memory cells to a specific voltage.
6. The DRAM semiconductor memory device of claim 5, wherein the charge circuit device includes a variable voltage source to provide the specific voltage.
7. The DRAM semiconductor memory device of claim 1, wherein the further memory cells are arranged in an edge region of the memory cell array.
8. The DRAM semiconductor memory device of claim 1, wherein the further memory cells comprise redundant DRAM memory cells.
9. The DRAM semiconductor memory device of claim 1, further comprising:
two lines running parallel to adjacent sense amplifiers, wherein one of the two lines drives the gate of the further memory cell connected to the first bit line and the other of the two lines drives the gate of the further memory cell connected to the second bit line.
10. An electric device comprising the DRAM semiconductor device of claim 1.
11. A method for increasing the reading accuracy of a DRAM memory cell comprising:
providing a memory cell array that comprises bit lines, word lines, memory cells, with each memory cell including a selection transistor and a storage capacitor, the drain regions of the selection transistors being connected to the bit lines and the gates of the selection transistors being connected to the word lines, and a plurality of sense amplifiers connected to respective pairs of bit lines, where each pair of bit lines includes a first bit line and a second bit line, with a memory cell and a further memory cell being connected to each of the first and second bit lines of each pair of bit lines;
charging the storage capacitors of the further memory cells prior to a precharge operation of the pairs of bit lines; and
switching on the gates of the further memory cells connected to a selected pair of first and second bit lines in response to a precharge operation for charging the first and second bit lines of the selected pair to an equalization voltage that is different from half of a bit line high voltage level value.
12. The method of claim 11, wherein, during the precharge operation, the first and second bit lines of the selected pair are connected to a variable voltage source to set an output voltage, and the first and second bit lines of the selected pair are short-circuited with one another, such that a resistance of the connection between the variable voltage source and the first and second bit lines of the selected pair is a plurality of orders of magnitude greater than the resistance between the short-circuited first and second bit lines of the selected pair.
13. The method of claim 12, wherein, during a test mode of the DRAM in which the variable voltage source is deactivated, the variable voltage source is set to the equalization voltage by measuring the equalization voltage at an equalization voltage pad, and the variable voltage source is set to the measured equalization voltage.
14. The method of claim 12, wherein the variable voltage source is set to the equalization voltage via laser fuses.
15. The method of claim 11, wherein the further memory cells are selected from memory cells in an edge region of the memory cell array.
16. The method of claim 11, wherein the further memory cells comprise redundant memory cells.
17. The method of claim 11, wherein a plurality of further memory cells are connected to each bit line, and the further memory cells connected to each bit line are jointly driven.
18. A method for increasing the reading accuracy of a DRAM memory cell in a memory cell array comprising:
providing a memory cell array that comprises bit lines, word lines, memory cells, with each memory cell including a selection transistor and a storage capacitor, the drain regions of the selection transistors being connected to the bit lines and the gates of the selection transistors being connected to the word lines, and a plurality of sense amplifiers connected to respective pairs of bit lines, where each pair of bit lines includes a first bit line and a second bit line, with a memory cell and a further memory cell being connected to each of the first and second bit lines of each pair of bit lines;
switching on the gates of the further memory cells connected to a selected pair of first and second bit lines in response to a precharge operation for charging the first and second bit lines of the selected pair to an equalization voltage; and
in response to a read operation of a memory cell connected to the first bit line of the selected pair of first and second bit lines, switching on the gate of the further memory cell connected to the second bit line of the selected pair of first and second bit lines.
19. The method of claim 18, wherein the further memory cells comprise memory cells located in an edge region of the memory cell array.
20. The method of claim 18, wherein the further memory cells comprise redundant memory cells.
21. The method of claim 18, wherein a plurality of further memory cells are connected to each bit line, and the further memory cells connected to each bit line are jointly driven.