Author: claimsbot

1. A portable terminal device characterized by having:
an audio output portion outputting an audio signal and, when an audio output device at which a speaker is arranged is connected to it, able to output the audio signal toward the audio output device so as to make it output audio in accordance with the audio signal from said speaker and
an output restriction portion restricting the output of the audio signal to the audio output device if the type of the audio signal output from the audio output portion is a specific type.
2. A portable terminal device as set forth in claim 1, characterized in that
an audio judgment portion judging whether or not the type of the audio signal output from the audio output portion is the specific type is provided, and
the output restriction portion restricts the output of the audio signal to the audio output device if it is judged at the audio judgment portion that the type of the audio signal is the specific type.
3. A portable terminal device as set forth in claim 1, characterized in that
a communication portion executing communication with another communication apparatus and
a signal reception detection portion for detecting signal reception from the other communication apparatus are provided,
the audio output portion outputs an audio signal of a signal reception sound when signal reception is detected at the signal reception detection portion, and
the output restriction portion restricts the output of the audio signal to the audio output device if the audio signal output from the audio output portion is the audio signal of the signal reception sound.
4. A portable terminal device as set forth in claim 3, characterized in that
the reception detection portion detects a sender with respect to the signal reception, and
the output restriction portion does not restrict the output of the audio signal of the signal reception sound to the audio output device if it is detected at the signal reception detection portion that the sender with respect to the signal reception is a specific sender.
5. A portable terminal device as set forth in claim 4, characterized in that
the output restriction portion does not restrict the output of the audio signal of the signal reception sound to the audio output device if it is detected at the signal reception detection portion that the sender with respect to the signal reception is the specific sender in that case that the audio output portion is set so as to output an audio signal of a signal reception sound corresponding to the specific sender if it is detected at the reception detection portion that the sender with respect to the signal reception is the specific sender.
6. A portable terminal device as set forth in claim 1, characterized in that
an alarm function portion able to output an alarm sound is provided,
the audio output portion outputs an audio signal of an alarm sound when a counted time reaches a time set at the alarm function portion, and
the output restriction portion restricts the output of the audio signal to the audio output device if the audio signal output from the audio output portion is the audio signal of an alarm sound.
7. An audio output device characterized by having
a speaker able to output audio in accordance with an audio signal output from a connectable portable terminal device when the portable terminal device is connected and
an output restriction portion restricting the output of the audio from the speaker if the type of the audio signal output from the portable terminal device is a specific type.
8. An audio output device as set forth in claim 7, characterized in that
an audio judgment portion for judging whether or not the type of the audio signal output from the portable terminal device is the specific type is provided, and
the output restriction portion restricts the output of the audio from the speaker if it is judged at the audio judgment portion that the type of the audio signal is the specific type.
9. An audio output device as set forth in claim 7, characterized in that
the output restriction portion restricts the output of the audio from the speaker if the audio signal output from the portable terminal device is an audio signal of a reception sound accompanying signal reception at a communication portion provided in the portable terminal device.
10. An audio output device as set forth in claim 7, characterized in that
the output restriction portion restricts the output of the audio from the speaker if the audio signal output from the portable terminal device is an audio signal of an alarm sound by an alarm function portion provided in the portable terminal device.
11. An audio device characterized by having
a portable terminal device,
an audio output device configured so that it can be connected to the portable terminal device and can output audio in accordance with an audio signal output from the portable terminal device from the speaker when it is connected to the portable terminal device, and
an output restriction portion restricting the output of the audio from the speaker if the type of the audio signal output from the portable terminal device is a specific type.
12. An audio device as set forth in claim 11, characterized in that
an audio judgment portion for judging whether or not the type of the audio signal output from the portable terminal device is the specific type is provided, and
the output restriction portion restricts the output of the audio from the speaker if it is judged at the audio judgment portion that the type of the audio signal is the specific type.
13. An audio device as set forth in claim 11, characterized in that
the portable terminal device has a communication portion able to communicate with another communication apparatus, and
the output restriction portion restricts the output of the audio from the speaker if the audio signal output from the portable terminal device is an audio signal of a signal reception sound accompanying signal reception at the communication portion.
14. An audio device as set forth in claim 11, characterized in that
the portable terminal device has an alarm function portion able to output an alarm sound, and
the output restriction portion restricts the output of the audio from the speaker if the audio signal output from the portable terminal device is an audio signal of the alarm sound.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A power integrated device comprising:
a channel region disposed in a first region of a substrate;
a drift region disposed in a second region of the substrate and adjacent to the channel region;
a source region disposed in a third region of the substrate and coupled to the channel region;
a drain region disposed in a first region of the drift region;
a stacked gate including a gate insulation layer and a gate electrode and extending from over the channel region to over the drift region;
a trench isolation layer disposed in a second region of the drift region and adjacent to a first side of the drain region; and
a deep trench field insulation layer disposed in a third region of the drift region and adjacent to a second side of the drain region,
wherein the drift region has an opposite conductivity as the channel region, and
wherein a height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.
2. The power integrated device of claim 1, wherein the deep trench field insulation layer is disposed in the drift region between the channel region and the drain region.
3. The power integrated device of claim 2, wherein the drain region is disposed between the trench isolation layer and the deep trench field insulation layer, and
wherein the drain region contacts the trench isolation layer and the deep trench field insulation layer.
4. The power integrated device of claim 2, wherein the deep trench field insulation layer overlaps with the stacked gate including the gate insulation layer and the gate electrode.
5. The power integrated device of claim 1, wherein the height of the deep trench field insulation layer is at least 1.2 times greater than the width of the bottom surface of the deep trench field insulation layer.
6. The power integrated device of claim 1, wherein each of the trench isolation layer, the deep trench field insulation layer, the source region, the drain region, the gate insulation layer, and the gate electrode extends in a first direction and has a stripe shape.
7. The power integrated device of claim 1, further comprising a body region disposed in the substrate and surrounding sidewalls and the bottom surface of the source region,
wherein the channel region is disposed in an upper surface region of the body region between the source region and the drift region.
8. The power integrated device of claim 1, wherein the channel region includes a first channel region and a second channel region,
wherein the first channel region contacts the source region, and
wherein the second channel region contacts the drift region.
9. The power integrated device of claim 8, further comprising:
a body region disposed in the substrate and surrounding sidewalls and a bottom surface of the source region; and
a well region disposed in the substrate, surrounding sidewalls and a bottom surface of the body region, and contacting a sidewall of the drift region,
wherein the first channel region is disposed in an upper surface region of the body region and the second channel region is disposed in an upper surface region of the well region.
10. The power integrated device of claim 9,
wherein the body region and the well region have the same conductivity type and,
wherein an impurity concentration of the well region is lower than an impurity concentration of the body region.
11. A power integrated device comprising:
a support substrate;
a buried insulation layer over the support substrate;
a drift layer over the buried insulation layer,
a body region disposed in the drift layer;
a source region disposed in the body region;
a drain region disposed in the drift layer and spaced apart from the body region;
a stacked gate including a gate insulation layer and a gate electrode and extending from over the body region between the source region and the drift layer to over the drift layer;
a trench isolation layer disposed in the drift layer and adjacent to a first side of the drain region; and
a deep trench field insulation layer disposed in the drift layer and adjacent to a second side of the drain region,
wherein a height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.
12. A power integrated device comprising:
a well region having a first conductivity and disposed in a substrate;
a body region having a second conductivity and disposed in a first region of the well region;
a drift region having the first conductivity, disposed in a second region of the well region, and spaced apart from the body region;
a source region having the first conductivity and disposed in the body region;
a drain region having the first conductivity and disposed in the drift region;
a stacked Rate including a gate insulation layer and a gate electrode and extending from over the body region between the source region and the well region to over the well region;
a trench isolation layer disposed in a third region of the well region and adjacent to a first side of the drain region; and
a deep trench field insulation layer disposed in a fourth region of the well region and adjacent to a second side of the drain region,
wherein a height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.
13. The power integrated device of claim 12, further comprising an impurity region having the first conductivity, disposed in the well region, and surrounding sidewalls and a bottom surface of the deep trench field insulation layer.
14. The power integrated device of claim 13, wherein an impurity concentration of the impurity region is higher than an impurity concentration of the well region.
15. The power integrated device of claim 13,
wherein an impurity concentration of the drift region is higher than an impurity concentration of the well region, and
wherein an impurity concentration of the impurity region is substantially equal to the impurity concentration of the drift region.
16. The power integrated device of claim 12, wherein the deep trench field insulation layer is disposed in the well region between the body region and the drain region.
17. The power integrated device of claim 16, wherein the trench isolation layer contacts the drain region.
18. The power integrated device of claim 16, wherein the deep trench field insulation layer overlaps with the stacked gate including the gate insulation layer and the gate electrode.
19. The power integrated device of claim 12, wherein the height of the deep trench field insulation layer is at least 1.2 times greater than the width of the deep trench field insulation layer.
20. A power integrated device comprising:
a substrate;
a buried layer having a first conductivity and disposed over the substrate;
an active layer having second conductivity and disposed over the buried layer;
a well region having the first conductivity and disposed in a first region of the active layer;
a body region having the second conductivity and disposed in a first region of the well region;
a drift region having the first conductivity, disposed in a second region of the well region, and spaced apart from the body region;
a source region having the first conductivity and disposed in the body region;
a drain region having the first conductivity and disposed in the drift region;
a stacked gate including a gate insulation layer and a gate electrode and extending from over the body region between the source region and the well region to over the well region;
a trench isolation layer disposed in a third region of the well region and adjacent to a first side of the drain region;
a deep trench field insulation layer disposed in a fourth region of the well region and adjacent to a second side of the drain region;
a contact region having the first conductivity, disposed in a second region of the active layer, and spaced apart from the well region; and
a sink region having the first conductivity, vertically penetrating the active layer, connecting the contact region to the buried layer,
wherein a height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.
21. The power integrated device of claim 1,
wherein the deep trench field insulation layer is disposed between the stacked gate and the drain region.

1. An array substrate comprising:
a first test line formed on a substrate and extending along a first direction;
a second test line disposed substantially in parallel with the first test line;
a first source line extending along a second direction substantially perpendicular to the first direction, the first source line being electrically connected to the first test line;
a second source line extending along the second direction, the second source line being electrically connected to the second test line;
a plurality of gate lines, each gate line extending along the first direction;
a first shorting bar extending along the first direction, the first source line extending from the first shorting bar along the second direction, the second source line extending along the second direction such that the second source line is separated from the first shorting bar; and
a switching device formed on a region surrounded by the first source line, the second source line, and the plurality of gate lines.
2. The array substrate of claim 1, further comprising:
a pixel electrode layer electrically coupled to the switching device,
wherein the first test line and the first source line are electrically connected to each other by a first bridge pattern being composed of a same material as that of the pixel electrode layer, and
wherein the second test line and the second source line are electrically connected to each other by a second bridge pattern being composed of a same material as that of the pixel electrode layer.
3. The array substrate of claim 1, wherein the first source line comprises odd numbered source lines and the second source line comprises even numbered source lines.
4. The array substrate of claim 1, wherein the first source line comprises even numbered source lines and the second source line comprises odd numbered source lines.
5. The array substrate of claim 1, wherein the first test line and the second test line are formed in a first peripheral region surrounding a display region on which the switching device is formed, and the first shorting bar is formed in a second peripheral region surrounding the first peripheral region.
6. The array substrate of claim 1, further comprising:
a third test line formed on the substrate and extending along the second direction;
a fourth test line disposed substantially in parallel with the third test line; and
a second shorting bar extending along the second direction,
wherein the plurality of gate lines comprises:
a first gate line extending from the second shorting bar along the first direction, the first gate line being electrically connected to the third test line;
a second gate line extending along the first direction, the second gate line being electrically connected to the fourth test line.
7. The array substrate of claim 6, further comprising:
a pixel electrode layer electrically coupled to the switching device,
wherein the third test line and the first gate line are electrically connected to each other by a third bridge pattern being composed of a same material as that of the pixel electrode layer, and
wherein the fourth test line and the second gate line are electrically connected to each other by a fourth bridge pattern being composed of a same material as that of the pixel electrode layer.
8. The array substrate of claim 6, wherein the first gate line comprises odd numbered gate lines and the second gate line comprises even numbered gate lines.
9. The array substrate of claim 6, wherein the first gate line comprises even numbered gate lines and the second gate line comprises odd numbered gate lines.
10. The array substrate of claim 6, wherein the third test line and the fourth test line are formed in a first peripheral region surrounding a display region on which the switching device is formed, and the second shorting bar is formed in a second peripheral region surrounding the first peripheral region.
11. An array substrate comprising:
a first test line disposed on a substrate;
a second test line disposed on the substrate;
a first shorting bar disposed on the substrate;
a first gate line extending along a first direction;
a third test line disposed on the substrate and extending along a second direction that is substantially perpendicular to the first direction, the third test line being electrically connected to the first gate line;
a fourth test line disposed substantially in parallel with the third test line;
a second gate line extending along the first direction, the second gate line being electrically connected to the fourth test line;
a plurality of source lines extending along the second direction;
a second shorting bar extending along the second direction, the first gate line extending from the second shorting bar along the first direction, the second gate line extending along the first direction such that the second gate line is separated from the second shorting bar; and
a switching device formed on a region surrounded by the first gate line, the second gate line, and the plurality of source lines.
12. The array substrate of claim 11, further comprising:
a pixel electrode layer electrically coupled to the switching device,
wherein the third test line and the first gate line are electrically connected to each other by a first bridge pattern being composed of a same material as that of the pixel electrode layer, and
wherein the fourth test line and the second gate line are electrically connected to each other by a second bridge pattern being composed of the same material as that of the pixel electrode layer.
13. The array substrate of claim 11, wherein the first gate line comprises odd numbered gate lines and the second gate line comprises even numbered gate lines.
14. The array substrate of claim 11, wherein the first gate line comprises even numbered gate lines and the second gate line comprises odd numbered gate lines.
15. The array substrate of claim 11, wherein the third test line and the fourth test line are formed in a first peripheral region surrounding a display region on which the switching device is formed, and the second shorting bar is formed in a second peripheral region surrounding the first peripheral region.
16. The array substrate of claim 11, wherein
the first test line extends along the first direction,
the second test line is disposed substantially in parallel with the first test line,
the first shorting bar extends along the first direction,

the plurality of source lines comprises
a first source line extending from the first shorting bar along the second direction, the first source line being electrically connected to the first test line, and
the plurality of source lines further comprises a second source line extending along the second direction, the second source line being electrically connected to the second test line.
17. The array substrate of claim 16, further comprising:
a pixel electrode layer electrically coupled to the switching device,
wherein the first test line and the first source line are electrically connected to each other by a third bridge pattern being composed of a same material as that of the pixel electrode layer, and
wherein the second test line and the second source line are electrically connected to each other by a fourth bridge pattern being composed of a same material as that of the pixel electrode layer.
18. The array substrate of claim 16, wherein the first source line comprises odd numbered source lines and the second source line comprises even numbered source lines.
19. The array substrate of claim 16, wherein the first source line comprises even numbered source lines and the second source line comprises odd numbered source lines.
20. The array substrate of claim 16, wherein the first test line and the second test line are formed in a first peripheral region surrounding a display region on which the switching device is formed, and the first shorting bar is formed in a second peripheral region surrounding the first peripheral region.
21. An array substrate comprising:
a first test line formed on a substrate and extending along a first direction;
a second test line disposed substantially in parallel with the first test line;
a first source line extending along a second direction substantially perpendicular to the first direction, the first source line being electrically connected to the first test line;
a second source line extending along the second direction, the second source line being electrically connected to the second test line;
a first shorting bar extending along the first direction, the first source line extending from the first shorting bar along the second direction, the second source line extending along the second direction such that the second source line is separated from the first shorting bar;
a third test line extending along the second direction;
a fourth test line disposed substantially in parallel with the third test line;
a first gate line extending along the first direction, the first gate line being electrically connected to the third test line;
a second gate line extending along the first direction, the second gate line being electrically connected to the fourth test line;
a second shorting bar extending along the second direction, the first gate line extending from the second shorting bar, the second gate line extending such that the second gate line is separated from the second shorting bar; and
a switching device formed on a region surrounded by the first gate line, the second gate line, the first source line, and the fourth source line.
22. The array substrate of claim 21, further comprising:
a pixel electrode layer electrically coupled to the switching device,
wherein the first test line and the first source line are electrically connected to each other by a first bridge pattern being composed of a same material as that of the pixel electrode layer,
wherein the second test line and the second source line are electrically connected to each other by a second bridge pattern being composed of a same material as that of the pixel electrode layer,
wherein the third test line and the first gate line are electrically connected to each other by a third bridge pattern being composed of a same material as that of the pixel electrode layer, and
wherein the fourth test line and the second gate line are electrically connected to each other by a fourth bridge pattern being composed of a same material as that of the pixel electrode layer.
23. The array substrate of claim 21, wherein the first source line comprises odd numbered source lines and the second source line comprises even numbered source lines.
24. The array substrate of claim 21, wherein the first source line comprises even numbered source lines and the second source line comprises odd numbered source lines.
25. The array substrate of claim 21, wherein the first gate line comprises odd numbered gate lines and the second gate line comprises even numbered gate lines.
26. The array substrate of claim 21, wherein the first gate line comprises even numbered gate lines and the second gate line comprises odd numbered gate lines.
27. The array substrate of claim 21, wherein the first test line, the second test line, the third test line, and fourth test line are formed in a first peripheral region surrounding a display region on which the switching device is formed, and the first shorting bar and the second shorting bar are formed in a second peripheral region surrounding the first peripheral region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electronic shopping mall that includes one or more virtual shops and is provided on a communication network to offer and sell products or services to a customer in response to an access provided by the customer via the communication network, comprising:
a shopping mall server that manages the electronic shopping mall and a shop server that manages the one or more of the virtual shops in the electronic shopping mall; and
wherein the shopping mall server comprises:
primary offering means for, in response to a request provided by the customer, offering a product or a service that the customer desires to purchase after being selected by the customer from the products or the services handled by the one or more of the virtual shops in the electronic shopping mall together with a price of the product or the service that the customer desires to purchase;
primary-discount means for, in response to an initial discount request provided by the customer, providing a reply on a discount to be borne by the electronic shopping mall to the customer; and
secondary-discount negotiation means for, in response to a further discount over the discount to be borne by the electronic shopping mall requested by the customer, carrying out a negotiation with the shop server for a discount to be borne by the one or more of the virtual shops managed by the shop server, and providing a result of the negotiation to the customer,
wherein the shop server comprises secondary-discount means for, in response to a discount request provided by the shopping mall server, providing a reply on the discount to be borne by the one or more of the virtual shops managed by the shop server to the shopping mall server.
2. An electronic shopping mall according to claim 1, wherein the shopping mall server further comprises customer information database configuration means for providing the customer with a questionnaire about personal information of the customer and configuring a customer information database by registering the personal information of the customer based on a result of the questionnaire, and
wherein the primary-discount means creates an answer on the discount to be borne by the electronic shopping mall at least referring to the customer information database, to the discount request provided by the customer.
3. An electronic shopping mall according to claim 1, wherein the shopping mall server further comprises primary advertisement means for, while the shopping mall server is creating the reply on the discount to be borne by the electronic shopping mall in response to the initial discount request provided by the customer, providing an advertisement of the electronic shopping mall managed by the shopping mall server to the customer.
4. An electronic shopping mall according to claim 1, wherein the shopping mall server further comprises secondary advertisement means for, while the shopping mall server is negotiating with the shop server for the further discount to be borne by the one or more of the virtual shops, providing an advertisement of the one or more of the virtual shops managed by the shop server to the customer.
5. An electronic shopping mall according to claim 1, wherein the shopping mall server further comprises direct negotiation offering means for mediating a direct negotiation between the customer and the shop sever.