Author: claimsbot

1. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate, wherein said memory modules are arranged in parallel so that said memory modules be installed on a mother board by mounting peripheral sides of said substrates to corresponding connectors provided on the mother board;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules so that each memory module is put between the corresponding pair of the heat radiation plates and said memory elements are thermally coupled to the corresponding heat radiation plate, respectively, wherein said plural pairs are arranged spacedly from each other so that the heat radiates from the faces of the heat radiation plates to the air between the neighboring memory modules;
a connecting member disposal at, and thermally coupled to, said heat radiation plates at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector so that the heat generated at the memory elements is conducted from the heat radiation plates, with which the memory elements are thermally coupled, to the other heat radiation plates via said connecting member; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that said radiation plates closely adhere to the corresponding memory elements.
2. A memory module assembly of claim 1,
wherein each of said heat radiation plates includes a protruding portion which protrudes beyond an extent of the substrate of the corresponding memory module at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector,
wherein said connecting member is disposed at, and thermally coupled to, said heat radiation plates at said protruding portions.
3. A memory module assembly of claim 1, wherein the connecting member is exposed to the air at the surface opposite to the surface facing to the memory modules.
4. A memory module assembly of claim 1, further comprising force-applying means engaged to the corresponding heat radiation plates so that each pair of said radiation plates closely adhere to the memory elements.
5. A memory module assembly of claim 1, further comprising a pair of inner heat radiation plates installed on each of the memory modules so that each inner heat radiation plate is positioned between, and thermally coupled to, a corresponding memory element and a corresponding heat radiation plate.
6. A memory module assembly of claim 1, wherein said heat radiation plates as well as said connecting member are formed of the same material.
7. A memory module assembly of claim 1, wherein said connecting member is provided with plural slits so that the air flows between the heat radiation plates.
8. A memory module assembly of claim 1, wherein the connecting member includes copper.
9. A memory module assembly of claim 4, wherein said force applying means includes a spring.
10. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules, each memory module being put between the corresponding pair of the heat radiation plates and said memory elements being thermally coupled to the corresponding heat radiation plate, respectively;
a connecting member coupled to pairs of heat radiation plates of the neighboring memory modules installed on a mother board to be inserted to corresponding connectors; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that radiation plates closely adhere to the corresponding memory elements.
11. A memory module assembly of claim 10, wherein each of said heat radiation plates includes a protruding portion which protrudes beyond an extent of the substrate of the corresponding memory module at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector,
wherein said connecting member is disposed at, and thermally coupled to, said heat radiation plates at said protruding portions.
12. A memory module assembly of claim 10, wherein the connecting member is exposed to the air at the surface opposite to the surface facing to the memory modules.
13. A memory module assembly of claim 1, further comprising force-applying means engaged to the corresponding heat radiation plates so that each pair of said radiation plates closely adhere to the memory elements.
14. A memory module assembly of claim 10, further comprising a pair of inner heat radiation plates installed on each of the memory modules so that each inner heat radiation plate is positioned between, and thermally coupled to, a corresponding memory element and a corresponding heat radiation plate.
15. A memory module assembly of claim 1, wherein said heat radiation plates as well as said connecting member are formed of the same material.
16. A memory module assembly of claim 1, wherein said connecting member is provided with plural slits so that the air flows between the heat radiation plates.
17. A memory module assembly of claim 1, wherein the connecting member includes copper.
18. A memory module assembly of claim 13, wherein said force-applying means includes a spring.
19. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules, the memory module being put between the corresponding pair of the heat radiation plates and said memory elements being thermally coupled to the corresponding heat radiation plate, respectively,
a connecting member coupled to at least two pairs of heat radiation plates of the neighboring memory modules installed on a mother board to be inserted to corresponding connectors; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that radiation plates closely adhere to the corresponding memory elements.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for clock synchronization, comprising:
computing an offset value between a local clock time of a real-time clock circuit and a reference clock time;
loading the offset value into a register that is associated with the real-time clock circuit; and
summing the local clock time with the value in the register so as to give an adjusted value of the local clock time that is synchronized with the reference clock.
2. The method according to claim 1, wherein the local clock time is associated with a slave device and the reference clock time is provided by a master device coupled to the slave device via a network.
3. The method according to claim 2, wherein the slave device comprises:
a host processor which is configured to compute the offset value and load the offset value into the register; and
a network interface device comprising the real-time clock circuit.
4. The method according to claim 2, wherein computing the offset value comprises:
exchanging a first set of messages between the master device and the slave device to determine a first time difference comprising the offset value and a transmission delay;
exchanging a second set of messages between the master device and the slave device to determine a second time difference comprising the transmission delay; and
calculating the offset value based on the first and second time differences.
5. The method according to claim 1, wherein the local clock time is maintained by incrementing a counter at intervals determined by a clock source, and wherein summing the local clock time comprises adding the value in the register to the local clock time at one of the intervals.
6. The method according to claim 5, wherein the real-time clock circuit comprises an adder providing a summed output to the counter, and having a first adder input coupled to receive a clock output from the counter, and a second adder input coupled to a multiplexed output from a multiplexer, which has a first multiplexer input coupled to receive a default increment amount and a second multiplexer input coupled to receive the offset value from the register.
7. A real-time clock circuit, comprising:
a counter, which is configured to output a local clock time;
a register, which is coupled to receive an offset value computed by a host processor; and
an adder, which is configured to provide a new local clock time for input to the counter by periodically adding a fixed increment to the local clock time that is output by the counter and alternatively, after the host processor has written the offset value to the register, by summing the offset value from the register with the local clock time.
8. The real-time clock circuit according to claim 7, and comprising a multiplexer having a first multiplexer input coupled to receive a default increment amount and a second multiplexer input coupled to receive the offset value from the register and configured to provide a multiplexed output, wherein the adder has a first input coupled to receive the local clock time that is output by the counter and a second input coupled to the multiplexed output from the multiplexer.
9. The real-time clock circuit according to claim 7, and comprising a local oscillator coupled to output pulses to the counter so as to cause the counter to be incremented at intervals indicated by the pulses.
10. The real-time clock circuit according to claim 7, and comprising a further register, which is coupled to receive an initial time value from a host processor, and a multiplexer, having a first multiplexer input coupled to receive the initial time value from the register, and a second multiplexer input coupled to receive the new local clock time from the adder, and configured to provide a multiplexed output to the counter.
11. An apparatus comprising:
a real-time clock circuit, which is configured to output a local clock time, and which comprises a register, which is coupled to receive an offset value, and an adder, which is coupled to sum the local clock time with the offset value in the register so as to give an adjusted value of the local clock time; and
a host processor configured to compute the offset value between the local clock time and a reference clock time, and to load the offset value into the register.
12. The apparatus according to claim 11, wherein the apparatus comprises a slave device, comprising the real-time clock circuit and the host processor, and the reference clock time is provided by a master device coupled to the slave device via a network.
13. The apparatus according to claim 12, wherein the slave device comprises a network interface device comprising the real-time clock circuit.
14. The apparatus according to claim 12, wherein the host processor is configured to exchange a first set of messages with the master device to determine a first time difference comprising the offset value and a transmission delay, to exchange a second set of messages with the master device to determine a second time difference comprising the transmission delay, and to calculate the offset value based on the first and second time differences.
15. The apparatus according to claim 11, wherein the real-time clock circuit comprises a counter and a clock source and is configured to maintain the local clock time by incrementing the counter at intervals determined by the clock source, and alternatively adding the value in the register to the local clock time at one of the intervals.

1. A content recording device comprising:
a tuner that receives a content program signal from a content provider;
an encoder that encodes the content program signal into a first data format;
a storage device that stores the encoded content program data;
transcoder circuitry operable to convert the encoded content program data into a second format suitable for transfer to and video playback on a portable communication device.
2. The content recording device according to claim 1, further comprising:
a communication interface operable to transfer the transcoded content program data to a portable communication device.
3. The content recording device according to claim 1, further comprising:
a device operable to prevent a copy of the content program data from being stored simultaneously on the content recording device and the portable communication device.
4. The content recording device according to claim 2, wherein the communication interface is a wireless communication interface.
5. The content recording device according to claim 4, wherein the wireless communication interface is a short-range radio frequency communication interface.
6. The content recording device according to claim 4, wherein the wireless communication interface is a Bluetooth communication interface.
7. The content recording device according to claim 2, wherein the wireless communication interface is a Global System for Mobile Communications (GSM) interface operable to communicate with a mobile telephone via a mobile network.
8. The content recording device according to claim 2, wherein the content recording device is a personal video recorder (PVR).
9. The content recording device according to claim 2, wherein the portable communication device is a mobile telephone.
10. A communication system comprising the content recording device according to claim 2 and a mobile telephone.
11. A program stored on a machine readable medium, the program being suitable for use in a portable communication device, wherein when the program is loaded in memory in the portable communication device and executed causes the portable communication device to:
receive program content data from a content recording device for playback on the portable communication device.
12. The program according to claim 11, wherein the program causes the portable communication device to return the program content data to the content recording device.
13. The program according to claim 11, wherein the program causes the portable communication device to:
receive an electronic program guide (EPG);
display the EPG; and
transmit a content selection command to the content recording device, the content selection command instructing the content recording device to record a selected content program.
14. The program according to claim 11, wherein the program causes the portable communication device to transmit remote control signals to the content recording device.
15. The program according to claim 11, wherein the content recording device is a personal video recorder (PVR), and the portable communication device is a mobile phone.
16. A portable communication device comprising a memory and a processor that executes an application program according to claim 11 within the memory, wherein the application program causes the portable communication device to display the program content data on a display of the portable communication device.
17. A method of remotely viewing a program recorded on a content recording device, the method comprising:
converting the program data into a data format suitable for transfer to and video playback on a portable communication device; and
transferring the converted program to a portable communication device for viewing.
18. The method according to claim 17, wherein the content recording device is a personal video recorder (PVR), and the portable communication device is a mobile phone.
19. A method of remotely controlling a content recording device using a portable communication device, the method comprising:
transmitting a content selection command to a content provider, the content provider directing the content recording device to record a selected program.
20. The method according to claim 19, wherein the content selection command is transmitted via a mobile network.
21. A digital video recording device comprising:
a device operable to receive and store digital program data in a first format; and
a device operable to convert the digital program data into a second format suitable for transfer to and video playback on a portable communication device.
22. The digital recording device according to claim 21, further comprising:
a device operable to transmit the converted digital program data to a portable communication device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of analyzing cells of a memory device, said method comprising the steps of:
applying voltages according to a first test pattern to nodes of a cell of said memory device;
applying voltages according to a second test pattern to said nodes of said cell of said memory device;
analyzing fail data for said cell of said memory device related to said first test pattern and said second test pattern;
determining a fail signature for said cell; and
determining a type of failure of said cell based upon the analysis of said fail data.
2. The method of claim 1 wherein said steps of applying voltages comprises steps of applying voltages to a node of a cell of a dynamic random access memory.
3. The method of claim 1 further comprising a step of establishing a plurality of fail signatures, each fail signature being associated with a type of failure.
4. The method of claim 3 wherein said step of determining a type of failure comprises a step of comparing a fail signature of a cell to said plurality of fail signatures.
5. A method of analyzing cells of a memory device, said method comprising the steps of:
establishing a plurality of fail signatures, each fail signature being associated with a type of failure;
applying voltages according to a plurality of test patterns to nodes of a cell of said memory device; analyzing fail data of said cell for said plurality of patterns;
determining a fail signature of said cell; and
determining a type of failure of said cell based upon said plurality of fail signatures.
6. The method of claim 5 wherein said step of establishing a plurality of fail signatures comprises a step of establishing fail signatures for nominal operation.
7. The method of claim 6 wherein said step of establishing a plurality of fail signatures for nominal operation comprises establishing fail signatures associated with complete failure of cells during nominal operation.
8. The method of claim 5 wherein said step of establishing a plurality of fail signatures comprises a step of establishing induced fail signatures.
9. The method of claim 8 wherein said step of establishing induced fail signatures comprises a step of establishing fail signatures indicating a leakage condition.
10. A method of analyzing cells of a memory device, said method comprising the steps of:
establishing a plurality of fail signatures for said memory device, each fail signature being associated with a type of failure of a cell;
applying voltages according to a plurality of test patterns to nodes of a plurality of cells of said memory device;
analyzing fail data for said plurality of test patterns applied to said cells; determining a fail signature of said plurality of cells;
comparing said fail signatures of said plurality of cells to said plurality of fail signatures; and
determining a type of failure for each failing cell of said plurality of cells.
11. The method of claim 10 wherein said step of establishing a plurality of fail signatures comprises a step of establishing fail signatures indicating failures during nominal operation.
12. The method of claim 10 wherein said step of establishing a plurality of fail signatures comprises a step of establishing fail signatures indicating leakage conditions.
13. The method of claim 10 further comprising a step of generating a first bit map having both hard fails and soft fails.
14. The method of claim 13 further comprising a step of generating a second bit map based upon said first bit map, said second bit map eliminating hard fails.
15. A system for analyzing cells of a memory device, said system comprising:
a plurality of probes applying different test voltages to a cell of said memory device;
a control circuit varying the voltages applied to said cell, said control circuit comparing the failures of said cell as the test voltages applied to said cell are varied to an artificial bit fail map; and
an output device generating an output indicating a type of failure of said cell.
16. The system of claim 15 wherein said control circuit varies the voltage applied to said cell according to a plurality of test patterns.
17. The system of claim 15 wherein said plurality of probes apply test voltages to a plurality of cells.
18. The system of claim 15 wherein said output device comprises a printer.
19. The system of claim 15 wherein said output device comprises a display.