Author: claimsbot

1. A compound of the formula I
wherein R1 and R2 are selected, independently, from hydrogen, (C1\u2013C10)straight or branched alkyl, (C1\u2013C10)straight or branched alkoxyalkyl, phenyl-(C1\u2013C3)straight or branched alkyl and phenyl-(C1\u2013C3)straight or branched alkoxyalkyl, wherein said phenyl moieties can optionally be substituted with one or two substituents selected, independently, from halo or (C1\u2013C3)alkyl;
or R1 and R2, together with the carbon to which they are attached, form a cyclopentyl, cyclohexyl or cycloheptyl ring which can optionally be substituted with one or two substituents selected, independently, from the group of substituents named in the definition of R1 and R2 above; and
R3 and R4 are selected, independently, from hydrogen and methyl;
with the proviso that at least one of R1, R2, R3 and R4 is other than hydrogen;

or a pharmaceutically acceptable salt thereof.
2. A compound or salt according to claim 1 that is selected from the following compounds and their pharmaceutically acceptable salts:
1-Aminomethyl-spiro2.4heptane-1-carboxylic acid;
1-Aminomethyl-spiro2.5octane-1-carboxylic acid;
1-Aminomethyl-spiro2.6nonane-1-carboxylic acid;
1-Aminomethyl-5-methyl-spiro2.4heptane-1-carboxylic acid;
1-Aminomethyl-2-methyl-spiro2.6nonane-1-carboxylic acid;
1-Aminomethyl-2,2-dimethyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2,2-di-n-propyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-isopropyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclopropyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-isobutyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(1-ethyl-propyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclohexyl-cyclopropanecarboxylic acid; and
1-Aminomethyl-2-(2-phenethyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-spiro2.3hexane-1-carboxylic acid;
1-Aminomethyl-spiro2.7decane-1-carboxylic acid;
1-Aminomethyl-5,6-dimethyl-spiro2.4heptane-1-carboxylic acid;
1-Aminomethyl-5-methyl-spiro2.5octane-1-carboxylic acid;
1-Aminomethyl-5,7-dimethyl-spiro2.5octane-1-carboxylic acid;
1-Aminomethyl-2,2-dimethyl-spiro2.6nonane-1-carboxylic acid;
1-Aminomethyl-2,2-diethyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2,2-di-n-butyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2,2-diisobutyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-n-propyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2-methyl-butyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2,2-dimethyl-butyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2-methyl-pentyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2,2-dimethyl-pentyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(3-ethyl-pentyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(4-ethyl-hexyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(1-methyl-cyclopropylmethyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(1-ethyl-cyclopropylmethyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(1-propyl-cyclopropylmethyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2-methyl-hexyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2,2-dimethyl-hexyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2,6-dimethyl-heptyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(3,7-dimethyl-octyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-n-butyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclobutyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclopentyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cycloheptyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclopropylmethyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-cyclohexylmethyl-cyclopropanecarboxylic acid;
1-Aminomethyl-2-(2-cyclohexyl-ethyl)-cyclopropanecarboxylic acid;
1-Aminomethyl-2-phenyl-cyclopropanecarboxylic acid; and
1-Aminomethyl-2-benzyl-cyclopropanecarboxylic acid.
3. A pharmaceutical composition comprising a therapeutically effective amount of a compound of the formula I
wherein R1 and R2 are selected, independently, from hydrogen, (C1\u2013C10) straight or branched alkyl, (C1\u2013C10) straight or branched alkoxyalkyl, phenyl-(C1\u2013C3) straight or branched alkyl and phenyl-(C1\u2013C3) straight or branched alkoxyalkyl, wherein said phenyl moieties can optionally be substituted with one or two substituents selected, independently, from halo or (C1\u2013C3)alkyl;
or R1 and R2, together with the carbon to which they are attached, form a cyclopentyl, cyclohexyl or cycloheptyl ring which can optionally be substituted with one or two substituents selected, independently, from the group of substituents named in the definition of R1 and R2 above; and
R3 and R4 are selected, independently, from hydrogen and methyl;
with the proviso that at least one of R1, R2, R3 and R4 is other than hydrogen;

or a pharmaceutically acceptable salt thereof.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A half-rate phase detecting method, the method comprising:
receiving a stream of binary data;
dividing the data by two;
latching the divided data with a first half-rate clock, creating a first latch output Q1;
latching the divided data with a second half-rate clock, the inverse of the first clock, creating a second latch output Q2;
latching Q1 with the second clock, creating a third latch output Q3;
latching Q2 with the first clock, creating a fourth latch output Q4;
performing an exclusive-OR operation on Q1 and Q2 to create phase signals having a first width; and,
performing an exclusive-OR operation on Q3 and Q4 to create reference signals, corresponding to the phase signals, having a second width that is twice the first width.
2. The method of claim 1 wherein receiving a stream of binary data includes receiving a stream of differential binary data;
wherein dividing the data by two includes dividing the differential data steam by two;
wherein creating output Q1 includes creating differential outputs Q1p and Q1n, the inverse of Q1p;
wherein creating output Q2 includes creating differential outputs Q2p and Q2n, the inverse of Q2p;
wherein creating output Q3 includes creating differential outputs Q3p and Q3n, the inverse of Q3p;
wherein creating output Q4 includes creating differential outputs Q4p and Q4n, the inverse of Q4p;
wherein performing an exclusive-OR operation on Q1 and Q2 to create phase signals includes performing exclusive-OR operations on the Q1 and Q2 differential outputs to create differential phase signal outputs; and,
wherein performing an exclusive-OR operation on Q3 and Q4 to create reference signals includes performing exclusive-OR operations on the Q3 and Q4 differential outputs to create differential reference signal outputs.
3. The method of claim 1 wherein dividing the stream of data by two includes introducing a first processing delay into the divided data;
the method further comprising:
in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks;
delaying the received stream of binary data a period of time equal to the first processing delay; and,
using the first and second clocks to sample the delayed binary data.
4. The method of claim 3 wherein receiving a stream of binary data includes receiving binary data pulses;
the method further comprising:
modifying the timing of the reference signals with respect to the phase signals; and,
wherein using the first and second clocks to sample the received data includes changing the binary data pulse sampling position in response to the modified reference signals.
5. A half-rate phase detector system with reduced data transition density, the system comprising:
a divide-by-two device D flip-flop having a clock input to accept a stream of binary data, a QB output connected to the D input, and a Q output to supply the data, divided by two;
a first latch (L1) having an input connected to the divide-by-two device output, an input to accept a first clock signal, and an output (Q1) to supply the divided data latched by the first clock;
a second latch (L2) having an input connected to the divide-by-two output, an input to accept a second clock signal, the inverse of the first clock, and an output (Q2) to supply the divided data latched by the second clock;
a third latch (L3) having an input connected to the first latch output, an input to accept the second clock signal, and an output (Q3) to supply the Q1 signal latched by the second clock;
a fourth latch (L4) having an input connected to the second latch output, an input to accept the first clock signal, and an output (Q4) to supply the Q2 signal latched by the first clock;
a first exclusive-OR (XOR) (X1) having an input to accept Q1, an input to accept Q2, and an output to supply a phase signal; and,
a second XOR (X2) having an input to accept Q3, and input to accept Q4, and an output to supply a reference signal.
6. The system of claim 5 wherein the divide-by-two device has a first processing delay;
the system further comprising:
a decision circuit including:
a delay buffer having an input to accept the stream of binary data and an output to supply the data with the first delay;
a fifth latch (L5) having an input connected to the delay buffer output, an input to accept the first clock signal, and an output (Q5) to supply the delayed data latched by the first clock;
a sixth latch (L6) having an input connected to the delay buffer output, an input to accept the second clock signal, and an output (Q6) to supply the delayed data latched by the second clock;
a seventh latch (L7) having an input connected to the fifth latch output, an input to accept the second clock signal, and an output (Q7) to supply the Q5 signal latched by the second clock; and,
an eighth latch (L8) having an input connected to the sixth latch output, an input to accept the first clock signal, and an output (Q8) to supply the Q6 signal latched by the first clock.
7. The system of claim 5 wherein the divide-by-two device has an input to accept a stream of differential binary data and an output to supply differential data divided by two;
wherein the first latch has an input connected to the divide-by-two output to accept the differential divided data and an output (Q1p and Q1n) to supply differential divided data latched by the first clock;
wherein the second latch has an input connected to the divide-by-two output to accept the differential divided data and an output (Q2p and Q2n) to supply differential divided data latched by the second clock;
wherein the third latch has an input connected to the first latch output to accept Q1p and Q1n signals and an output (Q3p and Q3n) to supply the differential Q1 signal latched by the second clock;
wherein the fourth latch has an input connected to the second latch output to accept Q2p and Q2n and an output (Q4p and Q4n) to supply the differential Q2 signal latched by the first clock;
wherein the first XOR has an input to accept the differential Q1 and differential Q2 signals and an output to supply differential phase signals; and,
wherein the second XOR has an input to accept the differential Q3 and differential Q4 signals and an output to supply differential reference signals.
8. The system of claim 7 wherein the delay buffer has an input to accept a stream of differential binary data and an output to supply delayed differential data;
wherein the fifth latch has an input connected to the delay buffer output to accept the differential divided data and an output (Q5p and Q5n) to supply differential divided data latched by the first clock;
wherein the sixth latch has an input connected to the delay buffer output to accept the differential divided data and an output (Q6p and Q6n) to supply differential divided data latched by the second clock;
wherein the seventh latch has an input connected to the fifth latch output to accept Q5p and Q5n signals and an output (Q7p and Q7n) to supply the differential Q5 signal latched by the second clock; and,
wherein the eighth latch has an input connected to the sixth latch output to accept Q6p and Q6n and an output (Q8p and Q8n) to supply the differential Q6 signal latched by the first clock.
9. The system of claim 7 wherein the divide-by-two device is a differential D flip-flop having a differential clock inputs (CLKp and CLKn) to receive the stream of digital data, a Qn output connected to the positive D input (Dp) to supply divided data, and a Qp output connected to the negative D input (Dn) to supply the divided data.
10. The system of claim 7 wherein the second XOR includes:
a first differential pair of transistors, with a first transistor gate to accept Q3p, a second transistor gate to accept Q3n, a first transistor source to supply a reference signal QP, and a second transistor source to supply a reference signal QN;
a second differential pair of transistors, with a third transistor gate to accept Q3n, a fourth transistor gate to accept Q3p, a third transistor source connected to the first transistor source, and a fourth transistor source connected to the second transistor source;
a fifth transistor having a drain connected to the sources of the first differential pair and a gate to receive the Q4p signal;
a sixth transistor having a drain connected to the sources of the second differential pair and a gate to receive the Q4n signal;
a seventh transistor having a drain connected to the sources of the fifth and sixth transistors, and a gate to accept a voltage bias signal (Vbias); and,
an eighth transistor having a drain connected to the second source and a gate to accept the voltage bias signal.
11. The system of claim 10 wherein the first XOR includes:
a third differential pair of transistors, with a ninth transistor gate to accept Q1p, a tenth transistor gate to accept Q1n, a ninth transistor source to supply a phase signal QPP, and a tenth transistor source to supply the phase signal QNP;
a fourth differential pair of transistors, with an eleventh transistor gate to accept Q1n, a twelfth transistor gate to accept Q1p, an eleventh transistor source connected to the ninth transistor source, and a twelfth transistor source connected to the tenth transistor source;
a thirteenth transistor having a drain connected to the sources of the third differential pair and a gate to receive the Q2p signal;
a fourteenth transistor having a drain connected to the sources of the fourth differential pair and a gate to receive the Q2n signal;
a fifteenth transistor having a drain connected to the sources of the thirteenth and fourteenth transistors, and a gate to accept a voltage bias signal (VbiasP).
12. The system of claim 11 wherein the current through the seventh and eighth transistors of the second XOR is approximately equal to the current through the fifteenth transistor of the first XOR.
13. A half-rate phase detecting method, the method comprising:
receiving a stream of binary data;
dividing the data by two and introducing a first processing delay;
latching the divided data with a first half-rate clock, creating a first latch output Q1;
latching the divided data with a second half-rate clock, the inverse of the first clock, creating a second latch output Q2;
latching Q1 with the second clock, creating a third latch output Q3;
latching Q2 with the first clock, creating a fourth latch output Q4;
performing an exclusive-OR operation on Q1 and Q2 to create phase signals;
performing an exclusive-OR operation on Q3 and Q4 to create reference signals, corresponding to the phase signals;
in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks;
delaying the received stream of binary data a period of time equal to the first processing delay; and,
using the first and second clocks to sample the delayed binary data.

1. A method for granting access to memory contents of an RFID transponder, the memory contents including an identifier, comprising:
sending a first communication to the RFID transponder;
sending a second communication to the RFID transponder that includes a security key for validation by the RFID transponder;
receiving at least the identifier included in the memory contents in response to the second communication and as a result of validation of the security key; and
comparing the identifier to an identifier stored in a database to determined if the two identifiers are related.
2. The method of claim 1, wherein the security key is based on information received from the RFID transponder.
3. The method of claim 1, further comprising receiving a response from the RFID transponder in response to the first communication and that includes the security key.
4. The method of claim 1, further comprising sending a third communication to the RFID transponder that includes a second security key for validation by the RFID transponder and receiving further memory contents in response to the third communication and as a result of validation of the second security key.
5. The method of claim 4, wherein the second security key is based on information received from the RFID transponder.
6. The method of claim 4, further comprising receiving a second response from the RFID that includes the second security key.
7. The method of claim 1, wherein the identifier is a toll identifier.
8. The method of claim 1, wherein the identifier is a vehicle identifier.
9. The method of claim 1, wherein the identifier is an account identifier.
10. A toll system, comprising:
a central data base configured to:
store toll accounts,
receive identifiers related to toll accounts, and
compare the received identifiers to identifiers associated with the toll accounts to determine if a match exists;

an RFID reader comprising a radio and an antenna, the RFID reader configured to:
send a first communication to a RFID transponder that includes a memory the contents of which include an identifier,
send a second communication to the RFID transponder that includes a security key for validation by the RFID transponder,
receive at least the identifier included in the memory contents in response to the second communication and as a result of validation of the security key, and
transmit the identifier to the central database.
11. The system of claim 10, wherein the security key is based on information received from the RFID transponder.
12. The system of claim 10, wherein the RFID reader is further configured to receive a response from the RFID transponder in response to the first communication and that includes the security key.
13. The system of claim 10, wherein the RFID reader is further configured to send a third communication to the RFID transponder that includes a second security key for validation by the RFID transponder and receive further memory contents in response to the third communication and as a result of validation of the second security key.
14. The system of claim 13, wherein the second security key is based on information received from the RFID transponder.
15. The system of claim 13, wherein the RFID reader is further configured to receive a second response from the RFID transponder that includes the second security key.
15. The system of claim 10, wherein the identifier is a toll identifier.
16. The system of claim 10, wherein the identifier is a vehicle identifier.
17. The system of claim 10, wherein the identifier is an account identifier.
18. A method for granting access to memory contents of an RFID transponder, the memory contents including an identifier, comprising:
receiving a first communication from a RFID reader;
receiving a second communication from the RFID reader that includes a security key;
granting access to the memory contents based on the security key; and
sending at least the identifier included in the memory contents in response to the second communication.
19. The method of claim 18, further comprising sending a response to the first communication and that includes the security key.
20. The method of claim 18, further comprising receiving a third communication from the RFID transponder that includes a second security key, granting access to the memory based on the second security key, and sending further memory contents in response to the third communication.
21. The method of claim 20, further comprising sending a second response that includes the second security key.
22. A RFID transponder, comprising;
a memory the contents of which includes an identifier;
a radio front end and an antenna; and
a processor coupled with the radio front end and the memory, the processor configured to:
receive a first communication from a RFID reader via the radio front end and an antenna;
receive a second communication from the RFID reader that includes a security key via the radio front end and an antenna;
grant access to the memory contents based on the security key; and
send at least the identifier included in the memory contents in response to the second communication.
23. The RFID transponder of claim 22, wherein the processor is further configured to send a response to the first communication and that includes the security key.
24. The RFID transponder of claim 22, wherein the processor is further configured to receive a third communication from the RFID transponder via the radio front end and an antenna that includes a second security key, grant access to the memory based on the second security key, and send further memory contents in response to the third communication.
25. The RFID transponder of claim 24, wherein the processor is further configured to send a second response that includes the second security key.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A request processing device comprising:
a request sender that sends a write request or a read request to a storage device;
a response processor that receives a response to a request which the request sender has sent; and
a test request processor that converts a read response which is a response to a read request, into a test write request, and converts a write response which is a response to a write request into a test read request, from among responses that the response processor has received or from among responses that have been input from a device which is provided outside the request processing device.
2. The request processing device according to claim 1, wherein the test request processor is capable of operating in two operation modes, which are a test mode and a normal mode, and
when the test request processor operates in the test mode, the test request processor selectively performs conversion of the read response into a test write request and conversion of the write response into a test read request.
3. The request processing device according to claim 1, wherein the test request processor rewrites an Opecode field that the write response or a packet of the write response has, and performing the conversion.
4. The request processing device according to claim 1, further comprising
a test address processor that specifies a write address in the test write request and a read address in the test read request.
5. The request processing device according to claim 4, wherein the test address processor repeatedly specifies an address range that is specified in advance.
6. A request processing system comprising:
a request sender that sends a write request or a read request to a storage device;
a response processor that receives a response to a request which the request sender has sent; and
a test request processor that, from among responses that the response processor has received, converts a read response, which is a response to a read request, into a test write request, and converts a write response, which is a response to a write request, into a test read request.
7. The request processing system according to claim 6, further comprising a return input unit that has two operation modes, which are a test mode and a normal mode, and that, when the return input unit operates in the test mode, returns and inputs a response which the response processor has received to the test request processor,
wherein the test request processor has two operation modes, which are a test mode and a normal mode, and, in the test mode, the test request processor selectively performs conversion of the read response into a test write request and conversion of the write response into a test read request.
8. The request processing system according to claim 6, further comprising a test management unit that manages at least the details of an operation which is performed by the test request processor.
9. An access testing method for testing access to a storage device, the method comprising:
sending a write request or a read request to a storage device;
receiving a response to a request that has been sent;
converting, when a response that has been received is a read response which is a response to the read request, the read response into a test write request, and converting, when the response that has been received is a write response which is a response to the write request, the write response into a test read request; and
sending the test write request or the test read request to the storage device.