Author: claimsbot

1. A method for a network switch port for receiving and storing data included in incoming packets that vary in size and then forwarding the data from the network switch port, the method comprising the steps of:
a. receiving each incoming packet and generating a cell sequence curresponding to the incoming packet, wherein each cell of the cell sequence contains a separate portion of the data included in the incoming packet, and wherein each cell of each generated cell sequence is of a uniform size;
b. making a determination with respect to at least one cell of each cell sequence generated at step a as to whether to discard the cell or to store the cell in a memory, and then one of storing the cell in the memory or discarding the cell in accordance with the determination;
c. reading cells out of the memory and forwarding them from the network switch port; and
d. repetitively generating an estimate of an average number of cells stored in the memory during a period immediately preceding generation of the estimate, wherein the determination made at step b is a function of the generated estimate.
2. The method in accordance with claim 1 wherein step b comprises the substeps of:
b1. assigning the cell a discard weight that is a function of the estimated average number of cells stored in the memory generated at step d;
b2. generating a random number;
b3. comparing the cell’s assigned discard weight to the random number to produce result data indicting whether the discard weight exceeds a value of the random number,
b4. making the determination as to whether to discard the cell or to store the cell in the memory as a function of the result data; and
b5. one of storing or discarding the cell in the memory in accordance with the determination made at step b4.
3. The method in accordance with claim 2 wherein the discard weight assigned to the cell at step b1 is a function of an amount by which the estimated average number of cells stored in the memory exceeds a threshold level.
4. The method in accordance with claim 2 wherein step b1comprises the substeps of:
b11. allocating a separate discard weight for each of a plurality of separate number ranges,
b12. determining which particular number range of the plurality of separate number ranges includes the estimated average number of cells stored in the memory, and
b13. assigning the allocated discard weight of the particular number range to the cell.
5. The method in accordance with claim 4 wherein the discard weight for each of said plurality of number ranges is allocated at step b11 as an increasing function of magnitude of number values spanned by the number range.
6. The method in accordance with claim 1 wherein step b comprises the step of:
b1. making the determination with respect to a first cell of the cell sequence as to whether to discard that first cell and all other cells of the cell sequence based on a comparison of the first cell’s assigned discard weight and the random number, and on whether a current number of cells stored in the cell memory at the time the determination is made exceeds a predetermined threshold level; and
b2. one of discarding all cells of the cell sequence or storing all cells of the sequence in the memory in accordance with the determination made at step b1.
7. The method in accordance with claim 1 wherein the step d of repetitively generating an estimate of an average number of cells stored in the memory during a period immediately preceding generation of the estimate comprises the substeps of:
a1. multiplying a last computed average number of cells stored in the memory by a value of a parameter X between 0 and 1 to produce a first value,
a2. multiplying a number of cells currently stored in the memory by a quantity (1\u2212X) to produce a second value, and
a3. generating a next estimate of the average number of cells stored in the memory, as a sum of the first and second value, and
a4. iteratively repeating steps a1 through a3.
8. The method in accordance with claim 1 wherein step b comprises the substeps of:
b1. allocating a separate discard weight for each of a plurality of separate number ranges;
b2. determining which particular number range of the plurality of separate number ranges includes the estimated average number of cells stored in the memory;
b3. assigning the allocated discard weight of the particular number range to a first cell of each sequence,
b4. generating a random number;
b5. comparing said at least one cell’s assigned discard weight to the random number to produce result data indicting whether the discard weight exceeds a value of the random number;
b6. making the determination with respect to the first cell of the cell sequence as to whether to discard that first cell and all other cells of the cell sequence based on a comparison of the first cell’s assigned discard weight and the random number; and
b7. one of discarding all cells of the cell sequence or storing all cells of the sequence in the memory in accordance with the determination made at step b6.
9. The method in accordance with claim 8 wherein the step d of repetitively generating art estimate of an average number of cells stored in the memory during a period immediately preceding generation of the estimate comprises the substeps of:
a1. multiplying a last computed average number of cells scored in the memory by a value of a parameter X between 0 and 1 to produce a first value,
a2. multiplying a number of cells currently stored in the memory by a quantity (1\u2212X) to produce a second value, and
a3. generating a next estimate of the average number of cells stored in the memory, as a sum of the first and second value, and
a4. iteratively repeating steps a1 through a3.
10. The method in accordance with claim 1 wherein the estimated of the average number of cells stored in the memory is estimated at step d whenever there is a change in a number of cells currently stored in the memory.
11. An apparatus for receiving, storing and then forwarding data in a plurality of incoming packets that vary in size, the apparatus comprising:
a memory;
first means for receiving each incoming packet and for generating a cell sequence corresponding to the incoming packet, wherein each cell of the cell sequence packet contains a separate portion of the data included in the incoming packet, and wherein each cell of each generated cell sequence is of a uniform size;
second means for making a determination with respect to at least one cell of each generated cell sequence to whether to discard the cell or to store the cell in the memory;
third means for one of storing or discarding the cell in the memory in accordance with the determination made by the second means, and for reading cells out of the memory and forwarding the cell; and
fourth means for repetitively generating an estimate of an average number of cells stored in the memory during a period immediately preceding generation of the estimate,
wherein the determination made by the second means is a function of the generated estimate.
12. The apparatus in accordance with claim 11 wherein the second means comprises:
fifth means for assigning each cell a discard weight that is a function of the estimate generated by the fourth means;
sixth means generating a random number;
seventh means for comparing the cell’s assigned discard weight to the random number to produce result data indicting whether the discard weight exceeds a value of the random number,
eighth means for making the determination as to whether to discard the cell or to store the cell in the memory in response to the result data.
13. The apparatus in accordance with claim 12 wherein the discard weight assigned to each cell is a variable function of the estimated average number.
14. The apparatus in accordance with claim 12 wherein the fifth means allocates a separate discard weight for each of a plurality of separate number ranges, determines which particular number range of the plurality of separate number ranges includes the estimated average number of cells stored in the memory, and assigns the allocated discard weight of the particular number range to the cell.
15. The apparatus in accordance with claim 14 wherein the fifth means allocates the discard weight for each of the plurality of number ranges as an increasing function of magnitude of number values spanned by the number range.
16. The apparatus in accordance with claim 12 wherein the eighth means makes making a determination with respect to a first cell of each cell sequence as to whether to discard that first cell and all other cells of the cell sequence based on a comparison of the first cell’s assigned discard weight and the random number, and on whether a current number of cells stored in the cell memory at the time the determination is made exceeds a predetermined threshold level.
17. The apparatus in accordance with claim 11 wherein the fourth means comprises:
means for multiplying a previously generated estimate of an average number of cells stored in the memory by a value of a parameter X between 0 and 1 to produce a first value,
means for multiplying a number of cells currently stored in the memory by a quantity (1\u2212X) to produce a second value, and
means for generating a next estimate of the average number of cells stored in the memory, as a sum of the first and second value.
18. The apparatus in accordance with claim 11 wherein the second means comprises:
fifth means for allocating a separate discard weight for each of a plurality of separate number ranges;
sixth means for determining which particular number range of the plurality of separate number ranges includes the estimated average number of cells stored in the memory;
seventh means for assigning the allocated discard weight of the particular number range to a first cell of each sequence;
eighth means for generating a random number;
ninth means for comparing said at least one cell’s assigned discard weight to the random number to produce result data indicting whether the discard weight exceeds a value of the random number; and
tenth means for making the determination with respect to the first cell of the cell sequence as to whether to discard that first cell and all other cells of the cell sequence based on a comparison of the first cell’s assigned discard weight and the random number, and
wherein the third means one of discards all cells of the cell sequence or stores all cells of the sequence in the memory in accordance with the determination wade by the tenth means.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A magnetoresistive element comprising:
a nonmagnetic conductive layer having two end faces in a direction along which the nonmagnetic conductive layer extends;
a first magnetic layer connected to the nonmagnetic conductive layer near one end face of the two end faces;
a second magnetic layer connected to the nonmagnetic conductive layer so as to be distant from the first magnetic layer in the direction;
a third magnetic layer connected to the nonmagnetic conductive layer so as be distant from the first magnetic layer in the direction;
a first magnetic electrode connected to the first magnetic layer;
a second magnetic electrode connected to the second magnetic layer; and
a third magnetic electrode connected to the third magnetic layer, a voltage being applied between the third magnetic electrode and the first magnetic electrode through the third magnetic layer, the nonmagnetic conductive layer, and the first magnetic layer, and a current being caused to flow between the third electrode and the second magnetic electrode through the third magnetic layer, the nonmagnetic conductive layer, and the second magnetic layer,
the nonmagnetic conductive layer decreasing in volume toward the one end face.
2. The element according to claim 1, wherein the first magnetic layer and the second magnetic layer are disposed on opposite sides of the nonmagnetic conductive layer, and the third magnetic layer is disposed on the same side as the second magnetic layer on the nonmagnetic conductive layer.
3. The element according to claim 1, wherein:
the first magnetic layer has a first surface, a second surface that is opposed to the first surface, and a third surface that is different from the first surface and the second surface; and
the nonmagnetic conductive layer is connected to at least one of the second surface and the third surface of the first magnetic layer.
4. The element according to claim 3, wherein:
the nonmagnetic conductive layer is connected to the third surface of the first magnetic layer; and
the nonmagnetic conductive layer decreases in thickness from the second surface to the first surface, or the one face of the nonmagnetic conductive layer is recessed in a direction from the first surface to the second surface.
5. The element according to claim 3, wherein the one face of the nonmagnetic conductive layer is connected to the second surface of the first magnetic layer.
6. The element according to claim 5, wherein the second surface of the first magnetic layer is tilted relative to the first surface.
7. The element according to claim 3, wherein the nonmagnetic conductive layer is connected to the second surface and the third surface of the first magnetic layer.
8. A magnetoresistive element comprising:
a nonmagnetic conductive layer having two end faces in a direction along which the nonmagnetic conductive layer extends;
a first magnetic layer connected to the nonmagnetic conductive layer near one end face of the two end faces;
a second magnetic layer connected to the nonmagnetic conductive layer so as to be distant from the first magnetic layer in the direction;
a first magnetic electrode connected to the first magnetic layer;
a second magnetic electrode connected to the second magnetic layer; and
a nonmagnetic electrode, a voltage being applied between the nonmagnetic electrode and the first magnetic electrode through the nonmagnetic conductive layer and the first magnetic layer, and a current being caused to flow between the nonmagnetic electrode and the second magnetic electrode through the nonmagnetic conductive layer and the second magnetic layer,
the nonmagnetic conductive layer decreasing in volume toward the one face.
9. The element according to claim 8, wherein the first magnetic layer and the second magnetic layer are disposed on the same side of the nonmagnetic conductive layer.
10. The element according to claim 8, wherein:
the first magnetic layer has a first surface, a second surface that is opposed to the first surface, and a third surface that is different from the first surface and the second surface; and
the nonmagnetic conductive layer is connected to at least one of the second surface and the third surface of the first magnetic layer.
11. The element according to claim 10, wherein:
the nonmagnetic conductive layer is connected to the third surface of the first magnetic layer; and
the nonmagnetic conductive layer decreases in thickness from the second surface to the first surface, or the one face of the nonmagnetic conductive layer is recessed in a direction from the first surface to the second surface.
12. The element according to claim 10, wherein the one face of the nonmagnetic conductive layer is connected to the second surface of the first magnetic layer.
13. The element according to claim 12, wherein the second surface of the first magnetic layer is tilted relative to the first surface.
14. The element according to claim 10, wherein the nonmagnetic conductive layer is connected to the second surface and the third surface of the first magnetic layer.
15. A magnetoresistive element comprising:
a nonmagnetic conductive layer having two end faces in a direction along which the nonmagnetic conductive layer extends;
a first magnetic layer connected to the nonmagnetic conductive layer near one end face of the two end faces;
a second magnetic layer connected to the nonmagnetic conductive layer so as to be distant from the first magnetic layer in the direction;
a first magnetic electrode connected to the first magnetic layer;
a second magnetic electrode connected to the second magnetic layer;
a first nonmagnetic electrode connected to the nonmagnetic conductive layer, a voltage being applied between the first nonmagnetic electrode and the first magnetic electrode through the first magnetic layer; and
a second nonmagnetic electrode connected to the nonmagnetic conductive layer, a current being caused to flow between the second nonmagnetic electrode and the second magnetic electrode through the second magnetic layer,
the nonmagnetic conductive layer decreasing in volume toward the one face.
16. The element according to claim 15, wherein the first magnetic layer and the second magnetic layer are on the same side of the nonmagnetic conductive layer.
17. The element according to claim 15, wherein:
the first magnetic layer has a first surface, a second surface that is opposed to the first surface, and a third surface that is different from the first surface and the second surface; and
the nonmagnetic conductive layer is connected to at least one of the second surface and the third surface of the first magnetic layer.
18. The element according to claim 17, wherein:
the nonmagnetic conductive layer is connected to the third surface of the first magnetic layer; and
the nonmagnetic conductive layer decreases in thickness from the second surface to the first surface, or the one face of the nonmagnetic conductive layer is recessed in a direction from the first surface to the second surface.
19. The element according to claim 17, wherein the one face of the nonmagnetic conductive layer is connected to the second surface of the first magnetic layer.
20. The element according to claim 19, wherein the second surface of the first magnetic layer is tilted relative to the first surface.

1. A block noise detector that receives an input video signal including pixel values and a horizontal synchronizing signal, and detects block boundaries due to block noise with an assumed block width, comprising:
a spatial difference comparator for calculating spatial differences by calculating differences between the pixel values of mutually adjacent pixels in the input video signal, detecting edges by comparing the calculated spatial differences, and outputting a decision signal indicating, for each calculated spatial difference, whether an edge is detected at a corresponding position;
a phased accumulator including a plurality of counters for cyclically receiving the decision signal, counting edges detected at different phases in the receiving cycle, and outputting count values at a timing synchronized with the horizontal synchronizing signal; and
a maximum sum and phase detector for outputting a maximum value signal having a maximum value among the count values output by the counters at said timing, and a maximum phase signal indicating a phase at which the maximum value occurs; wherein
the block noise detector outputs a detected block phase signal indicating a detected block phase at which block boundaries occur, based on the maximum phase signal.
2. The block noise detector of claim 1, wherein the spatial difference comparator compares each spatial difference separately with a predetermined number of left-neighboring spatial differences and with a predetermined number of right-neighboring spatial differences, and detects an edge if a predetermined condition is satisfied with respect to either the left-neighboring spatial differences or the right-neighboring spatial differences.
3. The block noise detector of claim 2, wherein the predetermined condition is that the spatial difference be greater than all of the left-neighboring spatial differences, or greater than all of the right-neighboring spatial differences.
4. The block noise detector of claim 1, wherein the maximum phase signal is output as the detected block phase signal.
5. The block noise detector of claim 1, wherein the assumed block width is N pixels and the phased accumulator includes N counters, N being a positive integer.
6. The block noise detector of claim 5, wherein N is eight.
7. The block noise detector of claim 1, further comprising a phase consistency tester including a phase signal condition tester for receiving and comparing the maximum phase signal output by the maximum sum and phase detector for a plurality of consecutive horizontal lines, and outputting the detected block phase signal only if the maximum phase signal has identical values for all of the consecutive horizontal lines.
8. The block noise detector of claim 1, further comprising a thresholder for comparing the maximum value signal with a threshold value and outputting the maximum phase signal as the detected block phase signal, but outputting the detected block phase signal only when the maximum value signal is greater than the threshold value.
9. A block noise reducer including the block noise detector of claim 1 and a horizontal smoother, the horizontal smoother comprising:
a smoothing processor for smoothing the input video signal to generate a smoothed signal; and
a selector for selecting the input video signal and the smoothed signal for output as an output video signal, the smoothed signal being selected in a predetermined continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, the input video signal being selected for phases outside the predetermined continuous range.
10. A block noise reducer comprising the block noise detector of claim 1, a luminance horizontal smoother, a blue color difference horizontal smoother, and a red color difference horizontal smoother, wherein:
the input video signal includes an input luminance signal, an input blue color difference signal, and an input red color difference signal;
the block noise detector outputs the detected block phase signal according to the input luminance signal;
the luminance horizontal smoother includes a smoothing processor for smoothing the input luminance signal to generate a smoothed luminance signal, and a selector for outputting the smoothed luminance signal as an output luminance signal in a first continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, and outputting the input luminance signal as the output luminance signal for phases outside the first continuous range;
the blue color difference horizontal smoother includes a smoothing processor for smoothing the input blue color difference signal to generate a smoothed blue color difference signal, and a selector for outputting the smoothed blue color difference signal as an output blue color difference signal in a second continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, and outputting the input blue color difference signal as the output blue color difference signal for phases outside the second continuous range; and
the red color difference horizontal smoother includes a smoothing processor for smoothing the input red color difference signal to generate a smoothed red color difference signal, and a selector for outputting the smoothed red color difference signal as an output red color difference signal in the second continuous range of phases, and outputting the input red color difference signal as the output red color difference signal for phases outside the second continuous range.
11. A block noise reducer comprising the block noise detector of claim 1, a luminance horizontal smoother, and a color difference horizontal smoother, wherein:
the input video signal includes an input luminance signal and an input color difference signal;
the block noise detector detects block noise according to the input luminance signal and outputs the detected block phase signal;
the luminance horizontal smoother includes a smoothing processor for smoothing the input luminance signal to generate a smoothed luminance signal, and a selector for outputting the smoothed luminance signal as an output luminance signal in a first continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, and outputting the input luminance signal as the output luminance signal for phases outside the first continuous range; and
the color difference horizontal smoother includes a smoothing processor for smoothing the input color difference signal to generate a smoothed color difference signal, and a selector for outputting the smoothed color difference signal as an output color difference signal in a second continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, and outputting the input color difference signal as the output color difference signal for phases outside the second continuous range.
12. A block noise reducer comprising a luminance block noise reducer, a blue color difference block noise reducer, and a red color difference block noise reducer, the luminance block noise reducer, the blue color difference block noise reducer, and the red color difference block noise reducer each including the block noise detector of claim 1 and a horizontal smoother, wherein:
the input video signal includes an input luminance signal, an input blue color difference signal, and an input red color difference signal;
the block noise detector in the luminance block noise reducer receives the input luminance signal and outputs a first detected block phase signal indicating a detected luminance block phase;
the horizontal smoother in the luminance block noise reducer includes a smoothing processor for smoothing the input luminance signal and outputting the smoothed luminance signal, and a selector for outputting the smoothed luminance output signal as an output luminance signal in a first continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase, and outputting the input luminance signal as the output luminance signal at phases outside the first continuous range;
the block noise detector in the blue color difference block noise reducer receives the input blue color difference signal and outputs a second detected block phase signal indicating a detected blue color difference block phase;
the horizontal smoother in the blue color difference block noise reducer includes a smoothing processor for smoothing the input blue color difference signal to generate a smoothed blue color difference signal, and a selector for outputting the smoothed blue color difference signal as a blue color difference output signal in a second continuous range of phases including the detected blue color difference block phase, at least one phase preceding the detected blue color difference block phase, and at least one phase following the detected blue color difference block phase, and outputting the input blue color difference signal as the output blue color difference signal for phases outside the second continuous range;
the block noise detector in the red color difference block noise reducer receives the input red color difference signal and outputs a third detected block phase signal indicating a detected red color difference block phase; and
the horizontal smoother in the red color difference block noise reducer includes a smoothing processor for smoothing the input red color difference signal to generate a smoothed red color difference signal, and a selector for outputting the smoothed red color difference signal as a red color difference output signal in a third continuous range of phases including the detected red color difference block phase, at least one phase preceding the detected red color difference block phase, and at least one phase following the detected red color difference block phase, and outputting the input red color difference signal as the output red color difference signal for phases outside than the third continuous range.
13. A method of detecting block noise in an input video signal including pixel values and a horizontal synchronizing signal by detecting block boundaries, the method comprising:
calculating differences between the values of adjacent pixels in the input video signal and outputting the calculated differences as spatial differences;
detecting edges by comparing the calculated spatial differences and outputting a decision signal indicating, for each calculated spatial difference, whether an edge is detected at a corresponding position;
receiving the decision signal cyclically, counting edges detected at different phases in the receiving cycle, and outputting resulting count values at a timing synchronized with the horizontal synchronizing signal;
outputting a maximum value signal having a maximum value among the count values output at said timing, and a maximum phase signal indicating a phase at which the maximum value occurs; and
outputting a detected block phase signal indicating a phase at which the block boundaries occur, based on the maximum phase signal.
14. The method of claim 13, wherein detecting edges further comprises:
comparing each spatial difference separately with a predetermined number of left-neighboring spatial differences and with a predetermined number of right-neighboring spatial differences; and
detecting an edge if a predetermined condition is satisfied with respect to either the left-neighboring spatial differences or the right-neighboring spatial differences.
15. The method of claim 14, wherein the predetermined condition is that the spatial difference be greater than all of the left-neighboring spatial differences, or greater than all of the right-neighboring spatial differences.
16. The method of claim 13, further comprising receiving and comparing the maximum phase signal output for a plurality of consecutive horizontal lines, wherein the detected block phase signal is output only if the maximum phase signal has identical values for all of the consecutive horizontal lines.
17. The method of claim 13, further comprising comparing the maximum value signal with a threshold value, wherein the maximum phase signal is output as the detected block phase signal but the detected block phase signal is output only when the maximum value signal is greater than the threshold value.
18. A method of reducing block noise, comprising:
detecting block noise by the method of claim 13;
smoothing the input video signal to generate a smoothed signal;
outputting the smoothed signal as an output video signal in a predetermined continuous range of phases including the detected block phase, at least one phase preceding the detected block phase, and at least one phase following the detected block phase; and
outputting the input video signal as the output video signal for phases outside the predetermined continuous range.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A bicycle gear changing apparatus comprising:
an upshifting input;
a downshifting input; and
a controller operatively coupled to the upshifting input and the downshifting input to receive upshift signals and downshift signals,
the controller outputting control signals to control a first gear changing device and a second gear changing device in accordance with a synchro-downshift route and a synchro-upshift route that is different from the synchro-downshift route in response to receiving the upshift signals and the downshift signals, the synchro-downshift route having a synchro-downshift point and the synchro-upshift route having synchro-upshift point that is different from the synchro-downshift point, and at least one of the synchro-upshift point and synchro-downshift point being adjustable.
2. (canceled)
3. (canceled)
4. The bicycle gear changing apparatus according to claim 1, wherein
the controller is configured to receive a synchro-downshift point signal to adjust the synchro-downshift point to be an adjusted synchro-downshift point and a synchro-upshift point signal to adjust the synchro-upshift point to be an adjusted synchro-upshift point.
5. The bicycle gear changing apparatus according to claim 4, wherein
the controller stores the adjusted synchro-downshift point and the adjusted synchro-upshift point.
6. A bicycle gear changing apparatus comprising:
an upshifting input;
a downshifting input; and
a controller operatively coupled to the upshifting input and the downshifting input to receive upshift signals and downshift signals,
the controller outputting control signals to control a first gear changing device and a second gear changing device in accordance with a synchro-downshift route and a synchro-shift route that is different from the synchro-downshift route in response to receiving the upshift signals and the downshift signals, the synchro-downshift route having a synchro-downshift point and the synchro-upshift route having a synchro-upshift point that is different from the synchro-downshift point,
the controller operating a rear gear changing device, corresponding to one of the first and second gear changing devices, before operating a front gear changing device, corresponding to the other of the first and second gear changing devices, to accomplish a synchro-upshifting operation.
7. A bicycle gear changing apparatus comprising:
an upshifting input;
a downshifting input; and
a controller operatively coupled to the upshifting input and the downshifting input to receive upshift signals and downshift signals,
the controller outputting control signals to control a first gear changing device and a second gear changing device in accordance with a synchro-downshift route and a synchro-upshift route that is different from the synchro-downshift route in response to receiving the upshift signals and the downshift signals, the synchro-downshift route having a synchro-downshift point and the synchro-upshift route having synchro-upshift point that is different from the synchro-downshift point,
the controller operating a front gear changing device, corresponding to one of the first and second gear changing devices, before operating a rear gear changing device, corresponding to the other of the first and second gear changing devices, to accomplish a synchro-upshifting operation.
8. The bicycle gear changing apparatus according to claim 1, further comprising
a first derailleur that corresponds to the rear gear changing device; and
a second derailleur that corresponds to the front gear changing device.
9. The bicycle gear changing apparatus according to claim 1, wherein
the controller outputs the control signals to control a gear ratio established by the first gear changing device and the second gear changing device such that the gear ratio changes in an ascending order during an upshift operation and in a descending order during a downshift operation.
10. The bicycle gear changing apparatus according to claim 1, wherein
the controller outputs the control signals to control a gear ratio established by the first gear changing device and the second gear changing device such that the gear ratio changes in an ascending order during an upshift operation.
11. The bicycle gear changing apparatus according to claim 1, wherein
the controller outputs the control signals to control a gear ratio established by the first gear changing device and the second gear changing device such that the gear ratio changes in a descending order during a downshift operation.