Author: claimsbot

1. A system comprising:
a network comprising a plurality of nodes wherein forwarding is controlled, at least in part, by an optimized spanning tree protocol (OSTP) comprising a selective forwarding state;
a server cluster; and
wherein, in a full-mesh portion of the network, the OSTP
is aware of the full-mesh portion,
is enabled to provide, to the nodes connected by the full-mesh portion, an explicit indication of whether or not full mesh topology is considered established, and
is further enabled to forward packets in one hop between any two of the nodes connected by the full-mesh portion;

wherein the full mesh is a first full mesh;
wherein the server cluster comprises a plurality of servers, each one of a first subset of the servers comprises one or more of the nodes of the network, and a second subset of the first subset of the servers are connected in a second full mesh; and
wherein the second full mesh is identical to the first full mesh.
2. The system of claim 1 wherein a packet sent via any two distinct ones of the nodes of the full-mesh portion from a first one of the nodes outside of the full-mesh to a second one of the nodes outside of the full-mesh portion does not pass through any of the nodes of the full-mesh portion other than the two distinct nodes.
3. The system of claim 1 wherein ports forming connections between the nodes connected by the full-mesh portion use the selective forwarding state.
4. The system of claim 1 wherein the full-mesh portion comprises more than two of the nodes.
5. The system of claim 1 wherein the server cluster is an Enterprise Server (ES) cluster, and the servers are ES-based servers.
6. The system of claim 5 wherein at least some of the second subset of the servers comprise physical partitions of a physically-partitionable symmetric multiprocessor within an ES chassis.
7. The system of claim 1 wherein the second subset of the servers is at least three of the servers.
8. The system of claim 1 wherein each of the second subset of the servers comprises one or more respective ports; and
wherein the full mesh is instantiated among particular ones of the respective ports of the second subset of the servers.
9. The system of claim 8 wherein a type of each of the respective ports is selected from the group consisting of external, internal, regular, and STP edge.
10. The system of claim 8 wherein the particular ports are of the internal type.
11. The system of claim 8 wherein the particular ports exchange messages to, at least in part, establish presence of the full mesh.
12. The system of claim 11 wherein the messages comprise a set of neighbor IDs, each of the neighbor IDs identifying one of the servers.
13. The system of claim 12 wherein the neighbor IDs are MAC addresses.
14. The system of claim 11 wherein the messages are OSTP hello messages.
15. The system of claim 11 wherein the presence of the full mesh is, at least in part, established by a particular one of the second subset of the servers when a plurality of the messages received by the particular server indicate a set of neighbors of the particular server all have each one of the set of neighbors as a neighbor.
16. The system of claim 15 wherein the set of neighbors comprises at least three of the servers.
17. The system of claim 15 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to use the optimized spanning tree protocol.
18. The system of claim 15 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to be in the selective forwarding state.
19. The system of claim 18 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to be in a delay state prior to being enabled to be in the selective forwarding state.
20. The system of claim 15 wherein the messages further comprise a state indicating the establishment of the presence of the full mesh, the state being in accordance with the explicit indication of whether or not full mesh topology is considered established, and subsequent to establishing the presence of the full mesh, a plurality of the messages sent by the particular server have the state indicating the establishment of the presence of the full mesh.
21. The system of claim 20 wherein the full mesh is determined to be valid by the particular server when, subsequent to establishing the presence of the full mesh, a plurality of the messages received by the particular server indicate that each one of the set of neighbors all have the state indicating the establishment of the presence of the full mesh.
22. The system of claim 21 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to use the optimized spanning tree protocol.
23. The system of claim 21 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to be in the selective forwarding state.
24. The system of claim 23 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to be in a delay state prior to being enabled to be in the selective forwarding state.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of operating a flash memory array comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a selected one of said memory blocks;
responsive to said erasing:
setting the counter associated with said selected one of said memory blocks to a first predetermined value; and
incrementing each counter not associated with said selected one of said memory blocks; and

when a counter equals or exceeds a predetermined threshold value, always refreshing the data in the memory block associated with said counter by:
storing data from the memory block associated with said counter in another one of said memory blocks.
2. A method as in claim 1, wherein said first predetermined value is zero.
3. A method as in claim 1, wherein said refreshing further comprises leaving said data in said different memory block when said refreshing is complete.
4. A method as in claim 1, wherein said refreshing further comprises returning data from said another one of said memory blocks back to the memory block associated with the counter.
5. A method as in claim 4, wherein said data is restored in the same locations in a memory block as it is read from.
6. A method as in claim 1, wherein refreshing comprises dividing said data into pieces, each of said pieces being refreshed after a distinct, unrelated operation is completed by said flash memory array.
7. A method as in claim 6, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
8. A method as in claim 1, wherein the values of said counters are stored in a table.
9. A method as in claim 8, wherein said table is stored in said flash memory array.
10. A method as in claim 8, wherein said table is stored in a table in a separate memory storage device.
11. A method as in claim 8, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
12. A method as in claim 11, wherein said predetermined binary values are 11111111 and 11110110.
13. A method as in claim 8, wherein entries in said table contain eight data bytes.
14. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a memory block;
responsive to said erasing:
setting a counter associated with said memory block to a first predetermined value; and
incrementing counters respectively associated with all other memory blocks in the same main block;

for each counter which equal or exceed a second predetermined value, always refreshing a memory block associated with said counter by storing data contained in said memory block in a different memory block of said flash memory array.
15. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a memory block;
responsive to said erasing:
setting the counter associated with said memory block to a first predetermined value; and
decrementing the counters associated with all other memory blocks within the same main block;

for each counter which is less than or equal to a second predetermined value, always refreshing a memory block associated with said counter by storing data from said memory block in a different memory block of said flash memory array.
16. A method as in claim 14 or 15, wherein said first predetermined value is zero.
17. A method as in claim 14 or 15, wherein in said step of refreshing, data from blocks being refreshed is restored in the same locations it is read from.
18. A method as in claim 14 or 15, wherein said step of refreshing comprises dividing data in blocks being refreshed into pieces, each of said pieces being refreshed after a distinct, unrelated operation is completed by said flash memory array.
19. A method as in claim 18, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
20. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors each sector respectively associated with a counter, the method comprising the steps of:
programming a sector of one of said memory blocks;
responsive to said programming:
setting a counter associated with the programmed sector to a first predetermined value; and
incrementing each counter associated with each adjacent sector of said one memory block; and

always refreshing the data in a sector of the one memory block of said flash memory array when an associated counter equals or exceeds a predetermined threshold value by storing data contained in that sector to different sector.
21. A method as in claim 20, wherein said first predetermined value is zero.
22. A method as in claim 20, wherein said refreshing further comprises leaving said data in said different sector when said refreshing is complete.
23. A method as in claim 20, wherein said refreshing comprises returning said data from said different sector to said sector.
24. A method as in claim 23, wherein said data is restored in the same locations in a sector as it is read from.
25. A method as in claim 20, wherein when the counters associated with multiple sectors equal or exceed said predetermined threshold simultaneously, said refreshing comprises refreshing some sectors before a distinct, unrelated operation is completed by said flash memory array and refreshing some other sectors after said distinct, unrelated operation is completed by said flash memory array.
26. A method as in claim 25, wherein each of said sectors is refreshed after a next write command is executed by said flash memory array.
27. A method as in claim 20, wherein the values of said counters are stored in a table.
28. A method as in claim 27, wherein said table is stored in said flash memory array.
29. A method as in claim 27, wherein said table is stored in a table in a separate memory storage device.
30. A method as in claim 27, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
31. A method as in claim 30, wherein said predetermined binary values are 11111111 and 11110110.
32. A method as in claim 27, wherein entries in said table contain eight data bytes.
33. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector in a memory block;
responsive to said programming:
setting a counter associated with said sector to a first predetermined value; and
incrementing counters respectively associated with all other sectors adjacent to said programmed sector;

always refreshing all sectors that have associated counters which equal or exceed a second predetermined value by storing data from a sector in a different sector in said flash memory array.
34. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector in a memory block;
responsive to said programming:
setting a counter associated with said sector to a first predetermined value;
decrementing counters respectively associated with all other sectors adjacent to said programmed sector; and

always refreshing all sectors that have associated counters which are less than or equal to a second predetermined value by storing data from a sector in a different sector in said flash memory array.
35. A method as in claim 33 or 34, wherein said first predetermined value is zero.
36. A method as in claim 33 or 34, wherein said data is restored in the same locations it is read from.
37. A method as in claim 33 or 34, wherein when the counter associated with multiple sectors equal or exceed said second predetermined value simultaneously, said refreshing comprises refreshing some of said sectors before a distinct, unrelated operation is completed by said flash memory array, and refreshing some other sectors after said distinct, unrelated operation is completed by said flash memory array.
38. A method as in claim 37, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
39. A flash memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks for storing data and a table for storing a plurality of counters values, each one of said counter values being respectively associated with one of said plurality of memory blocks;
wherein when said control circuit erases data stored in one of said memory blocks, said control circuit sets the counter value associated with said erased memory block to a first predetermined value and increments counter values respectively associated with other memory blocks; and
wherein when one of said plurality of counter values equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the memory block associated with said counter by storing the data stored in said memory block in a different memory block.
40. A flash memory storage device as in claim 39, wherein said control circuit optimizes said data prior to restoring said data.
41. A flash memory storage device as in claim 39, wherein when a counter value associated with a memory block equals or exceeds said predetermined threshold value, said control circuit divides said data into pieces, said control circuit refreshing some of said pieces before performing a distinct, unrelated operation and some other of said pieces after performing said distinct, unrelated operation.
42. A flash memory storage device as in claim 41, wherein said control circuit refreshes each of said pieces after performing a next write command.
43. A flash memory storage device as in claim 39, wherein the values of said counters are stored in a table.
44. A flash memory storage device as in claim 43, wherein said table is stored in said flash memory storage device.
45. A flash memory storage device as in claim 43, wherein said table is stored in a separate memory storage device.
46. A flash memory storage device as in claim 43, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
47. A flash memory storage device as in claim 46, wherein said predetermined binary values are 11111111 and 11110110 respectively.
48. A flash memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks, said memory blocks further divided into a plurality of sectors, for storing data and a table for storing a plurality of counter values, each counter value respectively associated with one of said plurality of sectors;
wherein when said control circuit programs one of said sectors, said control circuit sets the counter value associated with said programmed sector to a first predetermined value and increments counter values respectively associated with all sectors adjacent to said programmed sector; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the sector associated with said counter by storing the data stored in said sector in a different sector.
49. A flash memory storage device as in claim 48, wherein said control circuit optimizes said data prior to restoring said data.
50. A flash memory storage device as in claim 48, wherein when counters associated with multiple sectors equals or exceed said predetermined threshold value simultaneously, said control circuit refreshes some of said sectors before performing a distinct, unrelated operation and some other of said sectors after performing said distinct, unrelated operation.
51. A flash memory storage device as in claim 50, wherein said control circuit refreshes each of said sectors after performing a next write command.
52. A flash memory storage device as in claim 48, wherein said table is stored in said flash memory storage device.
53. A flash memory storage device as in claim 48, wherein said table is stored in a separate memory storage device.
54. A flash memory storage device as in claim 48, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
55. A flash memory storage device as in claim 54, wherein said predetermined binary values are 11111111 and 11110110 respectively.
56. A processor circuit comprising:
a processor; and
a flash memory storage device coupled to said processor, said flash memory storage device comprising a plurality of memory storage regions and a plurality of counters, each of said plurality of counters associated with one of said plurality of memory storage regions;
wherein when data stored in one of said memory storage regions is erased, the counter associated with said memory storage region is set to a first predetermined value and the remaining counters are incremented; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, the data in the memory storage region associated with said counter is always refreshed by storing data of said memory storage region in a different memory storage region.
57. A processor circuit as in claim 56, wherein said first predetermined value is zero.
58. A processor circuit as in claim 56, wherein said flash memory storage device restores said data to the same locations.
59. A processor circuit as in claim 56, wherein when a memory storage region requires refreshing, said flash memory storage device divides said memory storage region into pieces, said flash memory storage device refreshing some of said pieces before a distinct, unrelated operation is completed by said flash memory storage device and refreshing some other of said pieces after said distinct, unrelated operation is completed by said flash memory storage device.
60. A processor circuit as in claim 59, wherein said flash memory storage device refreshes each of said pieces after new write commands are executed by said flash memory storage device.
61. A processor circuit as in claim 56, wherein the values of said counters are stored in a table.
62. A processor circuit as in claim 61, wherein said table is stored in said flash memory storage device.
63. A processor circuit as in claim 61, wherein said table is stored in a separate memory storage device.
64. A processor circuit as in claim 61, wherein the most significant byte and the second most significant byte of each table entry are set to a predetermined binary values.
65. A processor circuit as in claim 64, wherein said predetermined binary values are 11111111 and 11110110 respectively.
66. A processor circuit comprising:
a processor; and
a flash memory storage device coupled to said processor, said flash memory storage device comprising a plurality of memory storage regions, said memory storage regions being divided into a plurality of sectors, and a plurality of counters, each of said plurality of counters respectively associated with one of said sectors;
wherein when one of said sectors is programmed, the counter associated with said sector is set to a first predetermined value and all of the sectors adjacent to said programmed sector incremented; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, the data in the sector associated with said counter is always refreshed by storing the data stored in said sector to a different sector.
67. A processor circuit as in claim 66, wherein said first predetermined value is zero.
68. A processor circuit as in claim 66, wherein said flash memory storage device returns said data to said sector.
69. A processor circuit as in claim 66, wherein when the counters associated with multiple sectors equal or exceed said predetermined value simultaneously, said flash memory storage device refreshes some of said sectors before a distinct, unrelated operation is completed by said flash memory storage device, and some other of said sectors after said distinct, unrelated operation is completed by said flash memory storage device.
70. A processor circuit as in claim 69, wherein said flash memory storage device refreshes each of said sectors after a write commands are executed by said flash memory storage device.
71. A processor circuit as in claim 66, wherein the values of said counters are stored in a table.
72. A processor circuit as in claim 71, wherein said table is stored in said flash memory storage device.
73. A processor circuit as in claim 71, wherein said table is stored in a separate memory storage device.
74. A processor circuit as in claim 71, wherein the entries in said table comprise N bytes each, each bit of each entry corresponding to one memory block of N based on said bit’s position within said byte.
75. A processor circuit as in claim 71, wherein the most significant byte and the second most significant byte of each table entry are set to a predetermined binary values, wherein said predetermined binary values are 11111111 and 11110110 respectively.
76. A method of operating a memory array comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a selected one of said memory blocks;
responsive to said erasing:
setting the counter associated with said selected one of said memory blocks to a first predetermined value; and
incrementing each counter not associated with said selected one of said memory blocks; and

which counter equals or exceeds a predetermined threshold value, always refreshing the data in the memory block associated with said counter by:
storing data from the memory block associated with said counter in another one of said memory blocks.
77. A method of operating a memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector of one of said memory blocks;
responsive to said programming:
setting a counter associated with the programmed sector to a first predetermined value; and
incrementing each counter associated with each adjacent sector of said one memory block; and

always refreshing the data in a sector of the one memory block of said memory array when an associated counter equals or exceeds a predetermined threshold value by storing data contained in that sector to different sector.
78. A memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks for storing data and a table for storing a plurality of counters values, each one of said counter values being respectively associated with one of said plurality of memory blocks;
wherein when said control circuit erases data stored in one of said memory blocks, said control circuit sets the counter value associated with said erased memory block to a first predetermined value and increments counter values respectively associated with other memory blocks; and
wherein when one of said plurality of counter values equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the memory block associated with said counter by storing the data stored in said memory block in a different memory block.
79. A memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks, said memory blocks further divided into a plurality of sectors, for storing data and a table for storing a plurality of counter values, each counter value respectively associated with one of said plurality of sectors;
wherein when said control circuit programs one of said sectors, said control circuit sets the counter value associated with said programmed sector to a first predetermined value and increments counter values respectively associated with all sectors adjacent to said programmed sector; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the sector associated with said counter by storing the data stored in said sector in a different sector.

1. A worm wheel comprising:
a plurality of teeth configured to mesh with teeth of a worm gear, each of the plurality of teeth having a first tooth flank on a first side in a rotational direction and a second tooth flank on a second side in the rotational direction, each of the first tooth flank and the second tooth flank having a helical surface portion and a concavely curved surface portion, the concavely curved surface portion having a shape configured to follow a convexly curved tooth flank of a worm gear, wherein:
the helical surface portion of the first tooth flank is arranged on a first side in a rotational axis direction of the worm wheel, and the concavely curved surface portion of the first tooth flank is arranged on a second side in the rotational axis direction of the worm wheel,
the concavely curved surface portion of the second tooth flank is arranged on the first side in the rotational axis direction of the worm wheel, and the helical surface portion of the second tooth flank is arranged on the second side in the rotational axis direction of the worm wheel,
a tooth height in the concavely curved surface portion of each of the first tooth flank and the second tooth flank increases toward a boundary with the helical surface portion of each of the first tooth flank and the second tooth flank;
a length of the helical surface portion of each of the first tooth flank and the second tooth flank in a tooth trace direction and a length of the concavely curved surface portion of the first tooth flank and the second tooth flank in a tooth trace direction are equal to each other; and
the first tooth flank of a first one of the plurality of teeth faces the second tooth flank of a second one of the plurality of teeth, and the second tooth flank of the first one of the plurality of teeth faces the first tooth flank of a third one of the plurality of teeth.
2. The worm wheel according to claim 1, wherein the helical surface portion of each of the first and second tooth flanks includes a groove portion that extends in the tooth trace direction.
3. A method of forming the worm wheel according to claim 1, comprising:
injecting synthetic resin between a first molding die that has a face corresponding to the first tooth flank and a second molding die that has a face corresponding to the second tooth flank; and
removing the first molding die from the worm wheel from one end toward the other end of the worm wheel in a rotational axis direction on a pitch cylinder of the cylindrical worm wheel and removing the second molding die from the worm wheel from the other end toward the one end of the worm wheel in the rotational axis direction on the pitch cylinder of the cylindrical worm wheel, after the synthetic resin is cured.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computer system comprising:
multiple processor cores;
a main memory;
at least one local cache memory associated with and operatively coupled to each core for storing cache lines accessible only by the associated core, each of the cache lines being classified as either a shared cache line or a private cache line; and
a global cache memory, the global cache memory being operatively coupled to the local cache memories and main memory and accessible by the cores, the global cache memory being capable of storing a plurality of cache lines, and wherein when a core writes a cache line, the core performs a write-back to the associated local cache memory if the cache line is a private cache line and a write-through to the global cache memory if the cache line is a shared cache line,
wherein at least one of the shared cache lines are in a valid state, an invalid state, or a transient dirty state, and wherein a shared cache line in a local cache memory transitions to the transient dirty state from the valid state or the invalid state when the cache line is written by the associated core, and wherein a shared cache line in the transient dirty state transitions to the valid state with a self-initiated write-through to the global cache memory.
2. The computer system of claim 1, wherein the self-initiated write-through to the global cache memory is arranged to occur at a period of time after the shared cache line transitions to the transient dirty state.
3. The computer system of claim 1, wherein a shared cache line which is in the valid state in a local cache memory associated with a first core transitions to the invalid state when a second core writes the shared cache line.
4. The computer system of claim 1, wherein each core transitions a subset of the shared cache lines in the associated local cache memories which are in the valid state to the invalid state before the core encounters a processing event.
5. The computer system of claim 4, wherein every shared cache line in the local cache memory which is in the transient dirty state is transitioned to either the invalid state or the valid state before the associated core encounters a processing event.
6. The computer system of claim 5, wherein the self-initiated write-through of a shared cache line in a local cache memory which is in the transient dirty state updates the global cache memory with only the data in the shared cache line that has been written by the associated core while the shared cache line is in the transient dirty state.
7. The computer system of claim 6, wherein the shared cache lines in the local cache memories are further classified into read-only cache lines and read-write cache lines, and wherein the shared read-only cache lines in a local cache memory which are in the valid state remain in the valid state when the associated core encounters a processing event.
8. The computer system of claim 7, wherein the processing event is a synchronization event.
9. The computer system of claim 5, wherein the shared cache lines in the local cache memories are further classified as read-only cache lines and read-write cache lines, and wherein the shared read-only cache lines in a local cache memory which are in the valid state remain in the valid state when the associated core encounters a processing event.
10. The computer system of claim 9, wherein the processing event is a synchronization event.
11. The computer system according to claim 1, wherein for a subset of core accesses to a shared cache line, the core bypasses the local cache memory and reads the shared cache line directly from the global cache memory.
12. The computer system of claim 11, wherein the shared cache line is blocked in the global cache memory while the core reads the shared cache line, and no request from another core can be processed by the global cache memory for the shared cache line until the shared cache line is unblocked by a write-through from the core.
13. The computer system according to claim 12, wherein the subset of the accesses of a core to a shared cache line are atomic instructions.
14. A method of implementing cache coherency in a computer system having multiple processor cores, the method comprising:
associating at least one local cache memory with each core for storing data accessible only by the associated core, the data being allocated to one or more cache lines acted upon by the associated core;
providing a global cache memory, the global cache memory being associated with each of the local cache memories for storing cache lines accessible by all of the cores;
classifying each of the cache lines in each local cache memory as a private cache line or a shared cache line;
performing a write-back operation to the associated local cache memory when a core writes a private cache line;
performing a write-through operation to the global cache memory when a core writes a shared cache line;
classifying at least one shared cache line to either an invalid state or a valid state;
changing the state of a shared cache line in a local cache memory to a transient dirty state, from either the valid or invalid state, when the shared cache line is written by the associated core; and
performing a self-initiated write-through of the shared cache line from the local cache memory to the global cache memory at a period of time after the shared cache line changes to the transient dirty state.
15. The method of claim 14, further comprising the steps of:
changing the state of any shared cache line in a local cache memory associated with a first core from the valid state to the invalid state when a second core writes the shared cache line to a local cache memory associated with the second core.
16. The method of claim 14, further comprising the steps of selecting one or more of the shared cache lines in a local cache memory which are in the valid state, and transitioning the selected shared cache lines to an invalid state before the core associated with the local cache memory encounters a processing event.
17. The method of claim 16, wherein the transitioning step further comprises selecting every shared cache line in the local cache memory in the transient dirty state and transitioning the selected shared cache lines from the transient dirty state to either the invalid state or the valid state before the core associated with the local cache memory encounters a processing event.
18. The method of claim 16, further comprising the steps of classifying the shared cache lines in each local cache memory as read-only cache lines or read-write cache lines, identifying a set of the shared read-only cache lines in each local cache memory which are in the valid state, and retaining the set of valid shared read-only cache lines in the valid state when the associated core encounters a processing event.
19. The method of claim 14, wherein the step of performing a self-initiated write-through of the shared cache line from the local cache memory to the global cache memory further comprises determining the data in the shared cache line modified by the associated core while the shared cache line is in the transient dirty state, and writing only the modified data in the shared cache line to the global cache memory.
20. The method of claim 19, further comprising the steps of classifying the shared cache lines in each local cache memory as read-only cache lines or read-write cache lines, identifying a set of the shared read-only cache lines in each local cache memory which are in the valid state, and retaining the set of valid shared read-only cache lines in the valid state when the associated core encounters a processing event.
21. The method of claim 14, wherein for a subset of core accesses to a shared cache line the core bypasses the local cache memory and reads the shared cache line directly from the global cache memory.
22. The computer system of claim 21, wherein the shared cache line is blocked in the global cache memory while the core reads the shared cache line, and no request from another core can be processed by the global cache memory for the shared cache line until the shared cache line is unblocked by a write-through.
23. The computer system according to claim 22, wherein the subset of core accesses to a shared cache line are atomic instructions.
24. A method of implementing cache coherency in a computer system having multiple processor cores, the method comprising:
associating at least one local cache memory with each core for storing data accessible by the associated core, the data being allocated to one or more cache lines acted upon by the associated core, each cache line having either a valid state or an invalid state;
providing a global cache memory, the global cache memory being associated with each of the local cache memories, the global cache memory storing data accessible by all of the cores, the data being allocated to one or more cache lines;
classifying each of the cache lines as a private cache line or a shared cache line; and
selecting between different write operations when a core writes a cache line, the selection including performing a write-back to the associated local cache memory when a core writes a private cache line and performing a write-through to the shared cache memory when a processor writes a shared cache line, and wherein the write-through operation can be delayed up to a synchronization event,
wherein the shared cache line is blocked at the global cache memory during the write-through delay, allowing the core to repetitively write to the shared cache line during the delay, and wherein the shared cache line including all core writes is written through to the global cache memory at the end of the delay.
25. The method of claim 24, further comprising the steps of determining the data modified in the shared cache line by the core during the write-through delay, and writing-through to the global cache memory only the modified data in the shared cache line.
26. The method of claim 24, where the step of classifying the individual cache lines is performed by an operating system and includes designating the individual cache lines as private or shared at a page level using observed data accesses.
27. The method of claim 24, wherein the write-through of the shared cache line to the global cache memory occurs after a period of time starting after the first write by the core to the shared cache line.