Author: claimsbot

1. A data coordination support apparatus that supports data coordination of a database including a plurality of tables, the data coordination support apparatus comprising:
an information storage unit to store primary key information indicating whether or not each of a plurality of columns included in each of the plurality of tables is designated as a primary key, and attribute information indicating an attribute of data contained in each of the plurality of columns included in each of the plurality of tables;
a table selection unit to select a table being a coordination destination of the data coordination, from among the plurality of tables;
a column identification unit to identify, with respect to each table among the plurality of tables other than the table selected by the table selection unit, a first column designated as the primary key and a second column not designated as the primary key, from a plurality of columns included in a table, based on the primary key information stored in the information storage unit;
a table extraction unit to extract such a table that a third column similar to the first column identified by the column identification unit is included in the table selected by the table selection unit, and a fourth column similar to the second column identified by the column identification unit is included in the table selected by the table selection unit, from tables among the plurality of tables other than the table selected by the table selection unit, based on the attribute information stored in the information storage unit; and
an information output unit to output recommendation information that recommends using a combination of the table selected by the table selection unit and the table extracted by the table extraction unit, in the data coordination, wherein
the table extraction unit, with respect to a table in which two or more second columns are identified by the column identification unit, extracts such a table that the fourth column exists, in the table selected by the table selection unit, individually for a largest number of the second columns.
2. The data coordination support apparatus according to claim 1, wherein
the table extraction unit, with respect to a table in which two or more first columns are identified by the column identification unit, extracts such a table that the third column exists, in the table selected by the table selection unit, individually for all of the first columns.
3. (canceled)
4. The data coordination support apparatus according to claim 1, wherein
the table extraction unit extracts at least two types of tables out of three types of tables, the three types of tables being a table that belongs to a same schema as the table selected by the table selection unit, a table that belongs to a different schema of a same instance as the table selected by the table selection unit, and a table that belongs to a schema of a different instance than the table selected by the table selection unit, and
the information output unit outputs, as the recommendation information, information that recommends using the combination of the table selected by the table selection unit and the table extracted by the table extraction unit, in the data coordination, for each type of the table extracted by the table extraction unit.
5. A data coordination support method that supports data coordination of a database including a plurality of tables, the data coordination support method comprising:
by use of a computer which includes an information storage unit that stores primary key information indicating whether or not each of a plurality of columns included in each of the plurality of tables is designated as a primary key, and attribute information indicating an attribute of data contained in each of the plurality of columns included in each of the plurality of tables, selecting a table being a coordination destination of the data coordination, from among the plurality of tables;
by use of the computer, identifying, with respect to each table among the plurality of tables other than the table selected by the selecting, a first column designated as the primary key and a second column not designated as the primary key, from a plurality of columns included in a table, based on the primary key information stored in the information storage unit;
by use of the computer, extracting such a table that a third column similar to the first column identified by the identifying is included in the table selected by the selecting, and a fourth column similar to the second column identified by the identifying is included in the table selected by the selecting, from tables among the plurality of tables other than the table selected by the selecting, based on the attribute information stored in the information storage unit; and
by use of the computer, outputting recommendation information that recommends using a combination of the table selected by the selecting and the table extracted by the extracting, in the data coordination, wherein
the extracting, with respect to a table in which two or more second columns are identified by the identifying, extracts such a table that the fourth column exists, in the table selected by the selecting, individually for a largest number of the second columns.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

I claim:

1. A phase-locked loop frequency synthesizer comprising;
a reference signal generator for generating a reference signal with a reference frequency;
a voltage controlled oscillator for generating an output signal having an output frequency in response to a control voltage signal received thereby;
a first variable frequency divider connected to said reference signal generator for frequency dividing the reference signal on the basis of a first divisor so as to generate a divided reference signal;
a second variable frequency divider connected to said voltage controlled oscillator for frequency dividing the output signal on the basis of a second divisor so as to generate a divided output signal;
a first controllable synchronous frequency divider connected to said first variable frequency divider for frequency dividing the divided reference signal on the basis of a third divisor upon receiving a frequency dividing control signal so as to generate a first low frequency signal;
a second controllable synchronous frequency divider connected to said second variable frequency divider for frequency dividing the divided output signal on the basis of the third divisor upon receiving the frequency dividing control signal so as to generate a second low frequency signal;
a phase-frequency comparator connected to said first and second controllable synchronous frequency dividers for receiving the first and second low frequency signals therefrom, said phase-frequency comparator comparing the first and second low frequency signals and outputting an adjust signal according to a detected difference therebetween;
a control voltage generating circuit connected to said voltage controlled oscillator and said phase-frequency comparator, said control voltage generating circuit supplying the control voltage signal to said voltage controlled oscillator in response to the adjust signal;
a phase-locked detector connected to said phase-frequency comparator for outputting a phase-locked signal in response to the adjust signal; and
a switching control logic connected to said phase-locked detector, said control voltage generating circuit, said first variable frequency divider, and said first and second controllable synchronous frequency dividers, said switching control logic being operable so as to supply the frequency dividing control signal to said first and second controllable synchronous frequency dividers with reference to the divided reference signal from said first variable frequency divider upon receiving the phase-locked signal from said phase-locked detector.
2. The phase-locked loop frequency synthesizer as claimed in claim 1, wherein each of said first and second controllable synchronous frequency dividers includes:
a first inverter having an input connected to a respective one of said first and second variable frequency dividers, and an output connected to a first node;
a first flip-flop having a first input connected to said switching control logic, a clock input connected to said first node, and an output connected to a second node;
a controllable frequency divider having a first input connected to said first node, a reset signal input connected to said second node, a divider input to receive the third divisor, and an output connected to a third node;
a NAND gate having a first input connected to said second node, a second input connected to said switching control logic, and an output;
a second inverter having an input connected to said third node, and an output;
a second flip-flop having a first input connected to said output of said NAND gate, a clock input connected to said output of said second inverter, and an output;
an OR gate having a first input connected to said third node, a second input connected to said output of said second flip-flop, and an output; and
an AND gate having a first input connected to the respective one of said first and second variable frequency dividers, a second input connected to said output of said OR gate, and an output connected to said phase-frequency comparator.
3. The phase-locked loop frequency synthesizer as claimed in claim 1, wherein R denotes the first divisor, N denotes the second divisor, Fref denotes the reference frequency, Fvco denotes the output frequency, and Fpfd denotes an operating frequency of said phase-frequency comparator, R, N, Fref, Fvco, Fpfd having a relation in which Fpfd{fraction (FrefR)}{fraction (FvcoN)}.
4. The phase-locked loop frequency synthesizer as claimed in claim 3, wherein, when the second divisor (N) is a fraction, the third divisor (M) is an integer and is a multiple of a denominator of the second divisor (N).

1. A method for improving resistance to bearing spin in a pulley assembly, said pulley assembly comprising a polymeric pulley having an integral bearing concentrically positioned therein, said method comprising:
providing a polymeric pulley having a central axial hub exhibiting a concentric axial bore therethrough, said concentric axial bore having an axial bore surface;
providing a metal tubular insert adjacent said axial bore surface, said metal tubular insert having an outer surface and an inner surface, wherein said outer surface of said metal tubular insert is coated with a brass or zinc coating to enhance adhesion of said outer surface of said metal tubular insert to said axial bore surface of said polymeric pulley;
providing an integral bearing having an outer axial race and an inner axial race, wherein said outer axial race of said integral bearing is coated with a phenolic primer;
applying at least one drop or bead of a fastening element onto said outer axial race having said phenolic primer coated thereon; and
forming said pulley assembly wherein said metal tubular insert is fixedly mounted in said axial bore of said polymeric pulley, and said outer axial race of said integral bearing is fixedly mounted to said inner surface of said metal tubular insert, wherein said pulley assembly retains constant position of said integral bearing relative to said polymeric pulley.
2. The method of claim 1, wherein said fastening element is a polymeric cement selected from the group consisting of epoxies, urethanes, acrylics, acrylates, methacrylates, cyanoacrylates, silicone, phenolic, and blends thereof.
3. The method of claim 2 wherein said polymeric cement is a methacrylate.
4. The method of claim 1 wherein said fastening element is a rigid material adhered to the outer surface of said outer axial race by a polymeric cement.
5. The method of claim 4 wherein said rigid material is a metal, ceramic or plastic material selected from the group consisting of ferrous or non-ferrous metals, ceramics, rigid plastics, and synthetic fibers.
6. The method of claim 5, wherein said metal is a ferrous or non-ferrous metal.
7. The method of claim 6 wherein said ferrous or non-ferrous metal is applied by welding.
8. The method of claim 1 wherein said pulley is formed from a polymeric material selected from the group consisting of polyamides, polyphthalamides, polyesters, epoxy resins, phenolic resins, polyurethanes, high density polyolefins, and ultra high density polyolefins.
9. The method of claim 1, wherein forming said pulley assembly includes over-molding said pulley on said metal tubular insert and said bearing.
10. An over molded pulley assembly having improved resistance to bearing spin, said over-molded pulley assembly comprising:
a polymeric pulley having a central axial hub exhibiting a concentric axial bore therethrough, said concentric axial bore having an axial bore surface;
a metal tubular insert adjacent said axial bore surface, said metal tubular insert having an outer surface and an inner surface, wherein said outer surface of said metal tubular insert is coated with a brass or zinc coating to enhance adhesion of said outer surface of said metal tubular insert to said axial bore surface of said polymeric pulley,
an integral bearing having an outer axial race and an inner axial race, wherein said outer axial race of said integral bearing is coated with a phenolic primer; and
at least one drop or bead of a fastening element positioned on an outer surface of said outer axial race having said phenolic primer coated thereon, wherein said pulley assembly retains constant position of said integral bearing relative to said polymeric pulley.
11. The pulley of claim 10, wherein said fastening element is a polymeric cement selected from the group consisting of epoxies, urethanes, acrylics, acrylates, methacrylates, cyanoacrylates, silicone, phenolic, and blends thereof.
12. The pulley of claim 11 wherein said polymeric cement is a methacrylate.
13. The pulley of claim 10 wherein said fastening element is a rigid material adhered to the outer surface of said outer axial race by a polymeric cement.
14. The pulley of claim 13 wherein said rigid material is selected from the group consisting of ferrous or non-ferrous metals, ceramics, rigid plastics, and synthetic fibers.
15. The pulley of claim 14, wherein said metal is a ferrous or non-ferrous metal.
16. The pulley of claim 10 wherein said pulley is formed from a polymeric material selected from the group consisting of polyamides, polyphthalamides, polyesters, epoxy resins, phenolic resins, polyurethanes, and high density polyolefins, and ultra high density polyolefins.
17. In a pulley assembly adapted for use with an endless drive belt in a vehicle, wherein said pulley assembly comprises a polymeric pulley, said polymeric pulley having a central axial hub exhibiting a concentric axial bore therethrough, said concentric axial bore having an axial bore surface; and an integral bearing having an outer axial race and an inner axial race, the improvement wherein said pulley assembly further comprises a metal tubular insert between said polymeric pulley and said integral bearing, said metal tubular insert having an outer surface and an inner surface wherein said outer surface of said metal tubular insert is adjacent said axial bore surface of said polymeric pulley and said inner surface of said metal tubular insert is adjacent said outer axial race of said integral bearing, wherein said outer surface of said metal tubular insert is coated with a brass or zinc coating to enhance adhesion of said outer surface of said metal tubular insert to said axial bore surface of said polymeric pulley; and wherein said integral bearing has at least one drop or bead of a fastening element on said outer axial race, wherein said fastening element is a polymeric cement selected from the group consisting of epoxies, urethanes, acrylics, acrylates, methacrylates, cyanoacrylates, silicone, phenolic, and blends thereof; wherein said outer race of said integral bearing further includes a primer between said outer race of said integral bearing and said at least one drop or bead of fastening element, said pulley assembly exhibiting improved resistance to bearing spin by retaining constant position of said integral bearing relative to said polymeric pulley.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A display device comprising:
a plurality of pixels; and
a driving circuit for driving the plurality of pixels;
wherein:
the driving circuit includes a single channel bidirectional shift register adapted for bidirectional scanning in a first direction and a second direction;
the single channel bidirectional shift register includes an \u201cn\u201d number of basic circuits tandem-connected in multiple stages (wherein \u201cn\u201d is equal to or greater than 2);
the basic circuits each include a first circuit and a second circuit;
the first circuit of each basic circuit includes a first transistor having a first electrode connected to a first node, a second electrode connected to a second scanning control line to which a second scanning direction control signal is supplied, and a control electrode connected to a first output terminal of a first basic circuit on a side of a preceding stage in the first scanning direction, and a second transistor having a first electrode connected to the first node, a second electrode connected to a first scanning control line to which a first scanning direction control signal is supplied, and a control electrode connected to a second output terminal of a second basic circuit on a side of a following stage in the first scanning direction;
the second circuit of each basic circuit includes a third transistor having a first electrode connected to a second node, a second electrode connected to the second scanning control line, and a control electrode connected to a third output terminal of a third basic circuit on the side of the following stage in the first scanning direction, and a fourth transistor having a first electrode connected to the second node, a second electrode connected to the first scanning control line, and a control electrode connected to a fourth output terminal of a fourth basic circuit on the side of the preceding stage in the first scanning direction; and
wherein each of the basic circuits further includes:
a fifth transistor having a control electrode connected to the first node, a second electrode connected to the second node, and a first electrode connected to a reference potential line to which a reference potential is supplied;
a sixth transistor having a control electrode connected to the second electrode of the fifth transistor, a first electrode connected to a clock terminal, and a second electrode connected to an output terminal of the basic circuit; and
a first capacitive element connected between the second node and the output terminal of the basic circuit.
2. The display device according to claim 1, wherein each of the basic circuits includes a seventh transistor having a first electrode connected to the reference potential line, a second electrode connected to the control electrode of the fifth transistor, and a control electrode connected to the control electrode of the sixth transistor.
3. The display device according to claim 1, wherein each of the basic circuits includes an eighth transistor having a control electrode and a second electrode each connected to a frame signal line to which a starting signal of a frame is supplied, and having a first electrode connected to the control electrode of the fifth transistor.
4. The display device according to claim 1, wherein each of the basic circuits includes a second capacitive element connected between the reference potential line and the control electrode of the fifth transistor.
5. The display device according to claim 1, wherein each of the basic circuits includes:
a ninth transistor connected between the control electrode of the sixth transistor and the second electrode of the fifth transistor, the ninth transistor having a control electrode connected to the first scanning control line; and
a tenth transistor connected between the control electrode of the sixth transistor and the second electrode of the fifth transistor, the tenth transistor having a control electrode connected to the second scanning control line.
6. The display device according to claim 1, wherein each of the basic circuits includes an eleventh transistor having a control electrode connected to the control electrode of the sixth transistor, a first electrode connected to a clock terminal, and a second electrode connected to an external output terminal.
7. The display device according to claim 6, wherein each of the basic circuits includes:
a twelfth transistor having a first electrode to which the reference potential is applied, and a second electrode connected to the second electrode of the eleventh transistor;
a thirteenth transistor having a first electrode connected to the control electrode of the twelfth transistor, a second electrode connected to the second scanning control line, and a control electrode connected to an external output terminal of an immediately preceding basic circuit in the first scanning direction; and
a fourteenth transistor having a first electrode connected to the control electrode of the twelfth transistor, a second electrode connected to the first scanning control line, and a control electrode connected to an external output terminal of an immediately following basic circuit in the first scanning direction.
8. The display device according to claim 7, wherein each of the basic circuits includes a fifteenth transistor having a control terminal and a second electrode each connected to the frame signal line, and a first electrode connected to the control electrode of the twelfth transistor.
9. The display device according to claim 7, wherein each of the basic circuits includes a third capacitive element connected between the reference potential line and the control electrode of the twelfth transistor.
10. The display device according to claim 1, wherein each of the basic circuits includes:
a sixteenth transistor having a control electrode connected to the control electrode of the sixth transistor, a first electrode connected to a clock terminal, and a second electrode connected to a first external output terminal; and
a seventeenth transistor having a control electrode connected to the control electrode of the sixth transistor, a first electrode connected to a clock terminal, and a second electrode connected to a second external output terminal.
11. The display device according to claim 10, wherein each of the basic circuits includes:
an eighteenth transistor having a first electrode connected to the reference potential line and a second electrode connected to the second electrode of the sixteenth transistor;
a nineteenth transistor having a first electrode connected to the reference potential line and a second electrode connected to the second electrode of the seventeenth transistor;
a twentieth transistor having a first electrode connected to the control electrodes of the eighteenth and nineteenth transistors, a second electrode connected to the second scanning control line, and a control electrode connected to a second external output terminal of an immediately preceding basic circuit in the first scanning direction; and
a twenty-first transistor having a first electrode connected to the control electrodes of the eighteenth and nineteenth transistors, a second electrode connected to the first scanning control line, and a control electrode connected to a second external output terminal of an immediately following basic circuit in the first scanning direction.
12. The display device according to claim 11, wherein each of the basic circuits includes a twenty-second transistor having a control terminal and a second electrode each connected to the frame signal line, and a first electrode connected to the control electrodes of the eighteenth and nineteenth transistors.
13. The display device according to claim 11, wherein each of the basic circuits includes a fourth capacitive element connected between the reference potential line and the control electrodes of the eighteenth and nineteenth transistors.
14. The display device according to claim 1, wherein:
a clock terminal of a basic circuit at an odd-numbered stage in the first scanning direction is connected to a first clock signal line to which a first clock signal is supplied;
a clock terminal of a basic circuit at an even-numbered stage in the first scanning direction is connected to a second clock signal line to which a second clock signal is supplied; and
the first clock signal and the second clock signal are of the same period and differ in phase.
15. The display device according to claim 1, wherein the basic circuit located at the (n\u22122)th stage based on the third stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to an output terminal of the basic circuit located at the second preceding stage;
the control electrode of the second transistor is connected to an output terminal of the basic circuit located at the second following stage;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the first following stage; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the first preceding stage.
16. The display device according to claim 15, further comprising a twenty-third transistor having a control electrode connected to the frame signal line and a first electrode connected to the second clock signal line, wherein the basic circuit at the first stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to the frame signal line;
the control electrode of the second transistor is connected to an output terminal of the basic circuit located at the third stage;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the second stage; and
the control electrode of the fourth transistor is connected to a second electrode of the twenty-third transistor.
17. The display device according to claim 16, wherein the basic circuit at the second stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to the second electrode of the twenty-third transistor;
the control electrode of the second transistor is connected to an output terminal of the basic circuit located at the fourth stage;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the third stage; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the first stage.
18. The display device according to claim 16, wherein the basic circuit at the second stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to the frame signal line;
the control electrode of the second transistor is connected to an output terminal of the basic circuit located at the fourth stage;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the third stage; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the first stage.
19. The display device according to claim 16, further comprising a fifth capacitive element connected between the control electrode of the twenty-third transistor and the reference potential line.
20. The display device according to claim 16, further comprising a twenty-fourth transistor having a control electrode connected to the second scanning control line, and a first electrode and a second electrode each connected to the second electrode of the twenty-third transistor.
21. The display device according to claim 15, further comprising a twenty-fifth transistor having a control electrode connected to the frame signal line and a first electrode connected to the first clock signal line, wherein if \u201cn\u201d is an even number, the basic circuit located at the nth stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to an output terminal of the basic circuit located at the (n\u22122)th stage;
the control electrode of the second transistor is connected to the frame signal line;
the control electrode of the third transistor is connected to a second electrode of the twenty-fifth transistor; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the (n\u22121)th stage.
22. The display device according to claim 21, wherein:
in the first scanning direction, after the starting signal of the frame has become valid, a voltage level of the first clock signal changes first and then a voltage level of the second clock signal changes; and
in the second scanning direction, after the starting signal of the frame has become valid, the voltage level of the second clock signal changes first and then the voltage level of the first clock signal changes.
23. The display device according to claim 15, further comprising a twenty-fifth transistor having a control electrode connected to the frame signal line and a first electrode connected to the second clock signal line, wherein if \u201cn\u201d is an odd number, the basic circuit located at the nth stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to an output terminal of the basic circuit located at the (n\u22122)th stage;
the control electrode of the second transistor is connected to the frame signal line;
the control electrode of the third transistor is connected to a second electrode of the twenty-fifth transistor; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the (n\u22121)th stage.
24. The display device according to claim 23, wherein:
in the first scanning direction or in the second scanning direction, after the starting signal of the frame has become valid, a voltage level of the second clock signal changes first and then a voltage level of the first clock signal changes.
25. The display device according to claim 21, wherein the basic circuit located at the (n\u22121)th stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to an output terminal of the basic circuit located at the (n\u22123)th stage;
the control electrode of the second transistor is connected to a second electrode of the twenty-fifth transistor;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the nth stage; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the (n\u22122)th stage.
26. The display device according to claim 21, wherein the basic circuit located at the (n\u22121)th stage in the first scanning direction is configured such that:
the control electrode of the first transistor is connected to an output terminal of the basic circuit located at the (n\u22123)th stage;
the control electrode of the second transistor is connected to the frame signal line;
the control electrode of the third transistor is connected to an output terminal of the basic circuit located at the nth stage; and
the control electrode of the fourth transistor is connected to an output terminal of the basic circuit located at the (n\u22122)th stage.
27. The display device according to claim 21, further comprising a sixth capacitive element connected between the second electrode of the twenty-fifth transistor and the reference potential line.
28. The display device according to claim 21, further comprising a twenty-sixth transistor having a control electrode connected to the second scanning control line, and a first electrode and a second electrode each connected to the second electrode of the twenty-fifth transistor.
29. A display device comprising:
a plurality of pixels; and
a driving circuit for driving the plurality of pixels;
wherein:
the driving circuit includes a single channel bidirectional shift register adapted for bidirectional scanning in a first direction and a second direction;
the single channel bidirectional shift register includes a flip-flop circuit;
the flip-flop circuit includes a first transistor having a first electrode connected to a first node and a second electrode to which a second scanning direction control signal is applied, and a second transistor having a first electrode connected to the first node and a second electrode to which a first scanning direction control signal is applied;
the first transistor includes a control electrode to which a resetting signal is applied in a first scanning direction and to which a setting signal is applied in a second scanning direction which is a reverse direction to the first scanning direction;
the second transistor includes a control electrode to which the setting signal is applied in the first scanning direction and to which the resetting signal is applied in the second scanning direction;
each of the transistors is an n-type of transistor; and
where the reference potential is defined as an L-level, and an H-level is defined as a voltage level of a potential higher than the reference potential,
in the first scanning direction, a voltage level of a first scanning direction control signal is the H-level and a voltage level of a second scanning direction control signal is the L-level, and
in the second scanning direction, a voltage level of a first scanning direction control signal is the L-level and a voltage level of a second scanning direction control signal is the H-level.
30. A display device comprising:
a plurality of pixels; and
a driving circuit for driving the plurality of pixels;
wherein:
the driving circuit includes a single channel bidirectional shift register adapted for bidirectional scanning in a first direction and a second direction;
the single channel bidirectional shift register includes a flip-flop circuit;
the flip-flop circuit includes a first transistor having a first electrode connected to a first node and a second electrode to which a second scanning direction control signal is applied, and a second transistor having a first electrode connected to the first node and a second electrode to which a first scanning direction control signal is applied;
the first transistor includes a control electrode to which a resetting signal is applied in a first scanning direction and to which a setting signal is applied in a second scanning direction which is a reverse direction to the first scanning direction;
the second transistor includes a control electrode to which the setting signal is applied in the first scanning direction and to which the resetting signal is applied in the second scanning direction;
each of the transistors is a p-type of transistor; and
where the reference potential is defined as an H-level, and an L-level is defined as a voltage level of a potential lower than the reference potential,
in the first scanning direction, a voltage level of a first scanning direction control signal is the L-level and a voltage level of a second scanning direction control signal is the H-level, and
in the second scanning direction, a voltage level of a first scanning direction control signal is the H-level and a voltage level of a second scanning direction control signal is the L-level.
31. The display device according to claim 1, wherein the driving circuit is a scan line driving circuit that scans each of the pixels for each display line.
32. The display device according to claim 1, wherein the driving circuit is an image line driving circuit that supplies an image voltage to each of the pixels.