Author: claimsbot

1. A semiconductor memory device, comprising:
a command generator suitable for generating an internal active command signal corresponding to an active command signal, wherein, when an active section of the active command signal lasts for a predetermined time or longer, the internal active command signal is additionally activated;
an address storage suitable for storing an address signal based on an activation number of the internal active command signal; and
a refresh operation driver suitable for performing a refresh operation on a word line corresponding to the stored address signal.
2. The semiconductor memory device of claim 1, wherein the command generator includes:
a normal activating unit for activating the internal active command signal based on the active command signal; and
an additional activating unit for additionally activating the internal active command signal based on the predetermined time.
3. The semiconductor memory device of claim further comprising:
an enable controller suitable for controlling whether to enable an operation of storing the address signal in a arbitrary section.
4. A semiconductor memory device, comprising:
a command generator suitable for receiving an active command signal, and modifying the received active command signal to an internal active command signal corresponding to an activity type;
an address storage suitable for storing an address signal based on an activation number of the internal active command signal;
a counter suitable for counting the internal active command signal corresponding to the activity type; and
a refresh operation driver suitable for receiving the address signal corresponding to an output signal of the counter, and performing a refresh operation on a word line corresponding to the stored address signal.
5. The semiconductor memory device of claim 4, wherein the activity type is divided into a first activity type and a second activity type, wherein the first activity type is determined based on an active section of the active command signal, and the second activity type is determined based on the number of times that the active command signal is activated in a predetermined section.
6. The semiconductor memory device of claim 5, further comprising:
first command generator suitable for generating a first internal active command signal when the active command signal of the first activity type is received; and
a second command generator suitable for generating a second internal active command signal when the active command signal of the second activity type is received.
7. The semiconductor memory device of claim 6, wherein the first activity type includes an active command signal having an active section where the active command signal is activated for a predetermined time or longer, and
the number of times that the first internal active command signal is activated exceeds the number of times that the active command signal of the first activity type is activated.
8. The semiconductor memory device of claim 6, wherein the second activity type includes an active command signal that is activated a predetermined times within a predetermined time, and
the number of times that the second internal active command signal is activated corresponds to the number of times that the active command signal of the second activity type is activated.
9. The semiconductor memory device of claim 6, wherein the address storage includes:
a first address storing unit for storing the address signal based on the first internal active command signal; and
a second address storing unit for storing the address signal based on the second internal active command signal.
10. The semiconductor memory device of claim 6, wherein the counter includes:
a first counting unit for counting the number of times that the first internal active command signal is activated; and
a second counting unit for counting the number of times that the second internal active command signal is activated.
11. The semiconductor memory device of claim 10, further comprising:
a comparator suitable for comparing a counting value of the first counting unit and a counting value of the second counting unit with each other.
12. The semiconductor memory device of claim 11, wherein the address storage provides the refresh operation driver with the address signal that is stored based on the internal active command signal corresponding to one of the first internal active command signal and the second internal active command signal based on an output signal of the comparator.
13. The semiconductor memory device of claim 4, further comprising:
an enable controller suitable for controlling whether to enable an operation of storing the address signal in an arbitrary section.
14. A memory system, comprising:
a controller suitable for generating access type information corresponding to data to be processed; and
a semiconductor memory device suitable for performing a readwrite operation on the data under control of the controller, modifying an internal control signal for storing a refresh target address based on the access type information, and performing a refresh operation on a word line corresponding to the refresh target address.
15. The memory system of claim 14, wherein the access type information corresponds to an access time of the data.
16. The memory system of claim 14, wherein the internal control signal is generated by modifying an active command signal provided by the controller.
17. The memory system of claim 16, wherein the semiconductor memory device includes:
a command generator suitable for receiving the active command signal and modifying the received active command signal to an internal active command signal corresponding to an activity type;
an address storage suitable for storing an address signal based on an activation number of the internal active command signal;
a counter suitable for counting the internal active command signal corresponding to the activity type; and
a refresh operation driver suitable for receiving the address signal corresponding to an output signal of the counter, and performing a refresh operation on a word line corresponding to the stored address signal.
18. The memory system of claim 17, wherein the command generator controls the number of times that the internal active command signal is activated based on the access type information.
19. The memory system of claim 17, wherein the counter controls a counting unit based on the access type information.
20. The memory system of claim 17, wherein the activity type is divided into a first activity type and a second activity type, wherein the first activity type is determined based on an active section of the active command signal, and wherein the second activity type is determined based on the number of times that the active command signal is activated in a predetermined section.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. One or more computer-readable hardware storage media comprising computer-readable instructions which are executable to cause a computing device to perform operations comprising:
adjusting a pointer received as part of a redirected call to a target virtual function;
jumping from the target virtual function to shim functionality using the adjusted pointer;
causing the shim functionality to readjust the adjusted pointer; and
jumping to a replacement function with the readjusted pointer to enable the replacement function to utilize the readjusted pointer to interact with an object instance associated with the target virtual function.
2. The one or more computer-readable hardware storage media of claim 1, wherein the adjusted pointer comprises a this pointer associated with the target virtual function.
3. The one or more computer-readable hardware storage media of claim 1, wherein the operations further comprise adjusting the pointer based on a memory offset value for the target virtual function.
4. The one or more computer-readable hardware storage media of claim 3, wherein the memory offset value is determined from a TI_GET_THISADJUST constant value associated with the object instance.
5. The one or more computer-readable hardware storage media of claim 1, wherein the replacement function is configured to use the readjusted pointer to access at least one of data or one or more functionalities of the object instance.
6. The one or more computer-readable hardware storage media of claim 1, wherein a signature for the shim functionality matches a signature for the target virtual function.
7. The one or more computer-readable hardware storage media of claim 1, wherein a calling convention for the shim functionality matches a calling convention for the target virtual function.
8. A computing device comprising:
at least one processor; and
one or more computer-readable hardware storage media comprising computer-readable instructions that are executable by the at least one processor to cause the computing device to implement operations including:
adjusting a pointer received as part of a redirected call to a target virtual function based at least in part on an offset between a memory address for an object associated with the target virtual function and a memory address for an introducing class within the object; and
readjusting the adjusted pointer to point to the object based at least in part on one or more symbols for the object.
9. The computing device of claim 8, wherein the adjusted pointer comprises a this pointer associated with the target virtual function.
10. The computing device of claim 8, the operations further comprising enabling the target virtual function to access data values or functionalities of the object using the adjusted pointer.
11. The computing device of claim 8, the operations further comprising jumping to a replacement function with the readjusted pointer to enable the replacement function to utilize the readjusted pointer to interact with the object associated with the target virtual function.
12. The computing device of claim 8, the operations further comprising executing a replacement function using the readjusted pointer.
13. A computer-implemented method comprising:
adjusting a pointer received as part of a redirected call to a target virtual function;
jumping from the target virtual function to shim functionality using the adjusted pointer;
causing, by a computing device, the shim functionality to readjust the adjusted pointer; and
jumping to a replacement function with the readjusted pointer to enable the replacement function to utilize the readjusted pointer to interact with an object instance associated with the target virtual function.
14. A computer-implemented method as described in claim 13, wherein the adjusted pointer comprises a this pointer associated with the target virtual function.
15. A computer-implemented method as described in claim 13, further comprising adjusting the pointer based on a memory offset value for the target virtual function.
16. A computer-implemented method as described in claim 15, wherein the memory offset value is determined from a TI_GET_THISADJUST constant value associated with the object instance.
17. A computer-implemented method as described in claim 13, wherein the replacement function is configured to use the readjusted pointer to access at least one of data or one or more functionalities of the object instance.
18. A computer-implemented method as described in claim 13, wherein a signature for the shim functionality matches a signature for the target virtual function.
19. A computer-implemented method as described in claim 18, wherein a calling convention for the shim functionality matches a calling convention for the target virtual function.
20. A computer-implemented method as described in claim 13, further comprising executing the replacement function using the readjusted pointer.

What is claimed is:

1. A computer system comprising:
a monitor comprising a main display area for displaying an image, the main display area having a plurality of display units arranged to be a matrix with a plurality of columns and rows, each display unit displaying a portion of the image according to a corresponding pixel data, a plurality of the display units in the main display area being arranged to form matrix-like tiles with the number of rows of the tiles being less than the number of the rows of the display units in the main display area and the number of columns of the tiles being less than the number of the columns of the display units in the main display area;
a memory comprising a plurality of first sequential memory units and a plurality of second sequential memory units, the second memory unit for storing pixel data of a display unit in the tile while the first memory unit is for storing pixel data of display units not in the tile, wherein no first memory units are utilized between any two second memory units; and
a processing unit for sequentially transmitting pixel data stored in any memory unit of the memory, wherein the processing unit does not transmit any pixel data stored in the first memory unit between transmitting two pixel data of the second memory unit when the processing unit is transmitting the two pixel data of two adjacent memory units.
2. The computer system of claim 1 wherein the monitor further comprising a controller electrically connected with the processing unit for transmitting the pixel data from the processing unit to the corresponding display unit; wherein the controller is capable of transmitting a plurality of pixel data of the second memory units to the display units of the tile to make the plurality of the display units display the corresponding image.
3. The computer system of claim 1 wherein the memory and the processing unit are incorporated into a graphics card.
4. The computer system of claim 1 wherein the processing unit is integrated into a controller chip.
5. The computer system of claim 1 wherein the memory is a system memory.
6. The computer system of claim 1 wherein the memory and the processing unit are incorporated into a motherboard.
7. The computer system of claim 1 wherein the monitor is a Liquid Crystal Display.
8. The computer system of claim 1 wherein the processing unit is capable of sequentially reading the pixel data from each memory unit of the memory for further video processing.
9. The computer system of claim 8 wherein the processing unit does not read the pixel data from the first memory unit between two pixel data from the second memory unit when the processing unit is reading the two pixel data from two adjacent second memory units.
10. The computer system of claim 8 wherein the processing unit is capable of writing pixel data into the memory unit of the memory after the video is processed.
11. The computer system of claim 10 wherein the processing unit does not write the pixel data into the first memory unit between the two pixel data from the second memory unit when the processing unit is writing the two pixel data into two adjacent second memory units.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A computer system comprising:
a computer having first and second connectors, a bus, and connection control means for enablingdisabling connection between said second connector and said bus; and
an expansion unit capable of being attacheddetached tofrom said computer,
wherein said expansion unit has
a third connector connectable to said first connector and connected to said first connector when said computer is set at a mounting position of said expansion unit,
a fourth connector connectable to said second connector and arranged to be free to move between a first position where said fourth connector is disconnected from said second connector and a second position where said fourth connector is connected to said second connector when said computer is set at the mounting position,
at least one expansion connector connected to said fourth connector and capable of being mounted with an expansion device,
a loading mechanism for moving said fourth connector between the first position and the second position, and
expansion unit control means for outputting a connection request signal for connection between said second connector and said fourth connector to said computer through said third connector when said computer is set at the mounting position, moving said fourth connector from the first position to the second position by driving said loading mechanism in accordance with a permission signal sent from said first connector, and outputting a connection completion signal upon completion of movement of said fourth connector to said second position,

said connection control means is set to disable connection between said second connector and said bus in advance, and
said computer includes
computer control means for outputting the permission signal to said expansion unit through said first connector in accordance with the connection request signal, and controlling said connection control means to enable connection between said second connector and said bus when said computer is in a power ON state upon reception of the connection request signal.
2. A system according to claim 1, wherein said expansion unit control means includes means for applying an operating voltage to said expansion device connected to said expansion connector when said computer is in a power ON state.
3. A system according to claim 1, wherein said expansion unit control means includes a sensor for detecting that said computer is set at the mounting position.
4. A system according to claim 1, wherein said expansion unit control means detects that said computer is set at the mounting position by monitoring a voltage of a predetermined pin of said third connector.
5. A system according to claim 1, wherein said computer includes means for reading attribute information of said expansion device from said expansion unit and setting a system environment for use of said expansion unit in accordance with the attribute information.
6. A system according to claim 1, wherein said expansion unit includes
an eject switch for designating to detach said fourth connector of said expansion unit from said second connector, and
means for sending a detachment request signal for detachment of said fourth connector to said computer through said third connector when said eject switch designates to detach said fourth connector from said second connector, moving said fourth connector from the second position to the first position by driving said loading mechanism in accordance with the detachment request signal sent from said computer, and outputting a separation completion signal upon completion of movement of said fourth connector to the first position, and
said computer includes
means for, when said computer is in a power ON state, controlling said connection control means to enable connection between said second connector and said bus in accordance with the detachment request signal and outputting a detachment permission signal through said first connector.
7. A system according to claim 6, wherein said expansion unit includes means for stopping applying an operating voltage to said expansion device connected to said expansion connector in accordance with the detachment permission signal.
8. A system according to claim 6, wherein said computer includes means for determining in accordance with the detachment request signal whether said expansion device connected to said expansion connector is being used, outputting the detachment permission signal when said expansion device is not being used, and stopping outputting the detachment permission signal when said expansion device is being used.
9. A system according to claim 8, wherein said computer includes means for informing an operator that said expansion device connected to said expansion connector is being used when it is determined that said expansion device is being used.
10. A system according to claim 6, wherein said computer includes means for outputting the detachment permission signal in accordance with the detachment request signal when said computer is in a power OFF state.
11. A computer system comprising:
a computer having a first connector, a bus, a second connector connected to said bus, and a nonvolatile memory; and
an expansion unit capable of being attacheddetached tofrom said computer,
wherein said expansion unit has
a third connector connectable to said first connector and connected to said first connector when said computer is set at a mounting position of said expansion unit,
a fourth connector connectable to said second connector and arranged to be free to move between a first position where said fourth connector is disconnected from said second connector and a second position where said fourth connector is connected to said second connector when said computer is set at the mounting position,
at least one expansion connector connected to said fourth connector and capable of being mounted with an expansion device,
a loading mechanism for moving said fourth connector between the first position and the second position, and
expansion unit control means for, when said computer is set at the mounting position, outputting a connection request signal for connection between said second connector and said fourth connector to said computer through said third connector and moving said fourth connector from the first position to the second position by driving said loading mechanism in accordance with a permission signal sent from said first connector, and

said computer includes
computer control means for, when said computer is in a power ON state, executing suspend processing in which information necessary for resuming processing which is being executed is stored in said nonvolatile memory to interrupt the processing and set a power OFF state in accordance with the connection request signal and thereafter outputting the permission signal to said expansion unit through said first connector.
12. A system according to claim 11, wherein said expansion unit control means includes means for outputting a connection completion signal upon completion of movement of said fourth connector to the second position, and said computer control means includes means for executing resume processing in which the information stored in said nonvolatile memory is used to resume the interrupted processing when the suspend processing is being executed upon reception of the connection completion signal.
13. A system according to claim 12, wherein said expansion unit includes means for starting applying an operating voltage to said expansion device connected to said expansion connector when said computer in a power OFF state is set in a power ON state.
14. A system according to claim 11, wherein said expansion unit control means includes a sensor for detecting that said computer is set at the mounting position.
15. A system according to claim 11, wherein said expansion unit control means detects that said computer is set at the mounting position by monitoring a voltage of a predetermined pin of said third connector.
16. A system according to claim 11, wherein said computer includes means for reading attribute information of said expansion device from said expansion unit and setting a system environment for use of said expansion unit in accordance with the attribute information.
17. A system according to claim 12, wherein said expansion unit includes
an eject switch for designating to detach said fourth connector of said expansion unit from said second connector, and
means for sending a detachment request signal for detachment of said fourth connector to said computer through said third connector when said eject switch designates to detach said fourth connector from said second connector, and moving said fourth connector from the second position to the first position by driving said loading mechanism in accordance with the detachment request signal sent from said computer, and
said computer includes
means for, when said computer is in a power ON state, executing the suspend processing in accordance with the detachment request signal and outputting a detachment permission signal through said first connector.
18. A system according to claim 17, wherein said expansion unit includes means for stopping applying an operating voltage to said expansion device connected to said expansion connector in accordance with the detachment permission signal.
19. A system according to claim 17, wherein said expansion unit includes means for outputting a separation completion signal upon completion of movement of said fourth connector to the first position, and said computer includes means for executing resume processing in which the information stored in said nonvolatile memory to resume the interrupted processing in accordance with the separation completion signal when the suspend processing is being executed.
20. A system according to claim 17, wherein said computer includes means for determining in accordance with the detachment request signal whether said expansion device connected to said expansion connector is being used, outputting the detachment permission signal when said expansion device is not being used, and stopping outputting the detachment permission signal when said expansion device is being used.
21. A system according to claim 20, wherein said computer includes means for informing an operator that said expansion device connected to said expansion connector is being used when it is determined that said expansion device is being used.
22. A system according to claim 21, wherein said computer includes means for outputting the detachment permission signal in accordance with the detachment request signal when said computer is in a power OFF state.
23. A computer system comprising:
a computer; and
an expansion unit capable of being attacheddetached tofrom said computer and constituted by an expansion unit main body and a power supply unit,
wherein said power supply unit is connected to said expansion unit main body through a cable and supplies a first power to said expansion unit through said cable, and
said expansion unit main body includes
at least one expansion connector connectable to an expansion device for expanding a function of said computer,
a mounting portion for mounting said computer, and
a power supply circuit for supplying an operating power to said expansion device on the basis of the first power supplied from said power supply unit when said computer is mounted at said mounting portion.
24. A system according to claim 23, wherein said expansion unit main body includes means for designating to startstop supplying the first power through said cable.
25. A system according to claim 23, wherein said expansion unit main body includes means for designating to start supplying the first power through said cable when said computer is mounted at said mounting portion.
26. A system according to claim 23, wherein said power supply unit has a plurality of power supply outlets, and said expansion unit main body includes means for enabling said plurality of power supply outlets in a predetermined order with predetermined time lags.
27. A system according to claim 23, wherein said computer includes means for designating to startstop supplying the first power through said expansion unit main body and said cable when said computer is mounted at said mounting portion.
28. A system according to claim 27, wherein said expansion unit has a plurality of power supply outlets, and said computer includes means for enabling said plurality of power supply outlets in a predetermined order with predetermined time lags.
29. A computer system comprising:
a computer; and
an expansion unit capable of being attacheddetached tofrom said computer,
wherein said expansion unit includes
at least one expansion connector connectable to an expansion device for expanding a function of said computer,
a mounting portion for mounting said computer, and
a lock mechanism for fixing said computer at a predetermined position of said mounting portion when said computer is mounted at said mounting portion.
30. A system according to claim 29, wherein said expansion unit has a detachable input device and includes means for operating said lock mechanism when specific information is supplied from said input device.
31. A system according to claim 29, wherein said expansion unit has a detachable input device and includes means for releasing said lock mechanism when specific information is supplied from said input device.
32. A system according to claim 29, wherein said expansion unit includes means for operating said lock mechanism when said computer is mounted.
33. A system according to claim 29, wherein said expansion unit has an eject switch for detaching said mounted computer and includes means for releasing said lock mechanism in accordance with an operation of said is eject switch.
34. A computer system comprising:
a computer having a first connector connected to a bus and at least one second connector connectable to an external device;
a relay unit connected to said computer and having a third connector connected to said bus which relays said first connector, and at least one fourth connector connectable to said external device which relays said second connector; and
at least one expansion unit connectable to said relay unit,
wherein said expansion unit has
a mounting portion capable of being mounted with an expansion device for expanding a function of said computer,
an internal bus connected to said expansion device mounted at said mounting portion,
a fifth connector connected to said internal bus, and
a sixth connector connectable to either said third connector or said fifth connector of another expansion unit.
35. A system according to claim 34, wherein said first and second connectors are arranged on a rear surface of said computer,
said relay unit is mounted on said rear surface of said computer so as to have said third connector on a lower surface and relays said first and second connectors of said computer, and
said at least one expansion unit is mounted under said computer and said relay unit to overlap another expansion unit such that said bus of said computer is connected to said expansion device of said expansion unit.
36. An electronic equipment comprising:
a processor incorporating a delay circuit element whose delay time changes depending on a temperature;
a detection circuit, connected to said delay circuit element, for detecting an internal temperature of said processor from a change in response delay of said delay circuit element; and
clock control means for controlling a clock signal supplied to said processor such that an operating speed of said processor is decreased when the internal temperature detected by said detection circuit exceeds a first temperature.
37. An electronic equipment according to claim 36, further comprising
a nonvolatile memory, and
means for causing said nonvolatile memory to store information necessary for resuming processing which is being executed, thereby powering off said electronic equipment when the internal temperature detected by said detection circuit exceeds a second temperature.
38. An electronic equipment comprising:
a processor for controlling said electronic equipment;
a detection circuit for detecting an internal temperature of said processor; and
clock control means for controlling a clock signal supplied to said processor such that an operating speed of said processor is decreased when the internal temperature detected by said detection circuit exceeds a first temperature.
39. An equipment according to claim 38, further comprising
a nonvolatile memory, and
suspend means for causing said nonvolatile memory to store information necessary for resuming processing which is being executed, thereby powering off said electronic equipment when the internal temperature detected by said detection circuit exceeds a second temperature.
40. An equipment according to claim 39, further comprising
a fan for exchanging air in the periphery of said processor,
a driving circuit for driving said fan, and
means for controlling said driving circuit to cool the air in the periphery of said processor in accordance with the internal temperature detected by said detection circuit.
41. An equipment according to claim 40, wherein said processor has an element whose characteristics change depending on a temperature, and
said detection circuit detects the internal temperature of said processor on the basis of a characteristic signal from said element.
42. An equipment according to claim 40, wherein said processor has a p-n junction circuit element for temperature detection, and
said detection circuit detects the internal temperature of said processor on the basis of a signal supplied from said p-n junction circuit element.
43. An equipment according to claim 40, wherein said processor has a transistor circuit element for temperature detection, and
said detection circuit detects the internal temperature of said processor on the basis of a signal supplied from said transistor circuit element.
44. An equipment according to claim 40, wherein
said processor has a thermistor circuit element for temperature detection, and
said detection circuit detects the internal temperature of said processor on the basis of a signal supplied from said thermistor circuit element.
45. An equipment according to claim 40, wherein
said processor has a delay circuit element for temperature detection, and
said detection circuit detects the internal temperature of said processor on the basis of a signal supplied from said delay circuit element.
46. A computer system comprising:
a computer having a processor for controlling said entire computer;
an expansion unit used to expand a function of said computer and capable of being attacheddetached tofrom said computer; and
a sensor for detecting a temperature of said processor,
wherein said expansion unit includes
a fan for exchanging air in the periphery of said processor,
a driving circuit for driving said fan, and
control means for appropriately setting the temperature of said processor by controlling said driving circuit in accordance with the temperature detected by said sensor.
47. A system according to claim 46, further comprising
communication means for performing communication between said computer and said expansion unit, and
wherein said sensor is arranged near said processor in said computer and outputs a signal representing the temperature of said processor to said expansion unit through said communication means.
48. A system according to claim 46, wherein said sensor is arranged near a mounting portion of said expansion unit, at which said computer is mounted.
49. A system according to claim 48, further comprising
communication means for performing communication between said computer and said expansion unit, and
wherein said sensor outputs a signal representing the temperature of said processor to said expansion unit through said communication means, and
said computer includes means for controlling a clock supplied to said processor so as to decrease an operating speed of said processor when the temperature of said processor, which is sent through said communication means, exceeds a first temperature.
50. A system according to claim 48, further comprising
communication means for performing communication between said computer and said expansion unit, and
a nonvolatile memory, and
wherein said sensor outputs a signal representing the temperature of said processor to said computer through said communication means, and
said computer includes means for causing said nonvolatile memory to store information necessary for resuming processing which is being executed, thereby powering off said computer when the temperature of said processor, which is sent through said communication means exceeds a second temperature.