Author: claimsbot

1. A semiconductor device comprising:
a semiconductor substrate having a front surface which comprises a first region and a second region that is separated from the first region;
a light receiving portion disposed on the front surface in the first region;
a light emitting portion disposed on the front surface in the second region;
an insulation film covering the front surface of the semiconductor substrate;
an electrode disposed on the insulation film;
a supporting body attached to the front surface of the semiconductor substrate;
an adhesive layer attaching the supporting body to the front surface so as to cover the insulation film and the electrode; and
a bump electrode disposed on a back surface of the semiconductor substrate and electrically connected to the electrode,
wherein a first opening is formed to penetrate the supporting body and the adhesive layer so as to expose the light receiving portion,
a second opening is formed to penetrate the supporting body and the adhesive layer so as to expose the light emitting portion, and
the first opening is different from the second opening.
2. The semiconductor device of claim 1, wherein the supporting body comprises a semiconductor substrate.
3. The semiconductor device of claim 1, further comprising light-transmitting fillers filling the first and second openings.
4. The semiconductor device of claim 3, wherein the fillers fill the first and second openings so as to form a curved top portion in each of the first and second openings.
5. The semiconductor device of claims 1, wherein the light receiving portion comprises a photodiode.
6. The semiconductor device of claims 1, wherein the light emitting portion comprises an LED.
7. The semiconductor device of claims 1, further comprising a protection film covering ends of the insulation film, the adhesive layer and the supporting body.
8. The semiconductor device of claims 1, further comprising a control circuit formed on the front surface of the semiconductor substrate and controlling at least one of the light receiving portion and the light emitting portion.
9. A method of manufacturing a semiconductor device, comprising:
forming a light receiving portion on a front surface of a semiconductor substrate;
forming an insulation film covering the semiconductor substrate;
forming an electrode on the insulation film;
applying an adhesive layer on the front surface of the semiconductor substrate;
attaching a supporting body to the front surface of the semiconductor substrate with the adhesive layer so as to cover the insulation film and the electrode;
forming a first opening in the supporting body and the adhesive layer so as to expose the light receiving portion;
forming a second opening in the supporting body and the adhesive layer away from the first opening;
placing a light emitting portion on the semiconductor substrate in the second opening;
forming a bump electrode on a back surface of the semiconductor substrate so as to be electrically connected to the electrode; and
dicing the semiconductor substrate and the supporting body so as to produce a semiconductor die having the first and second openings.
10. The method of claim 9, wherein the supporting body comprises a semiconductor substrate.
11. The method of claim 9, further comprising filling the first and second openings with light-transmitting fillers.
12. The method of claim 11, wherein the first and second openings are filled with the fillers so as to have a curved top portion in each of the first and second openings.
13. The method of claims 9, wherein the light receiving portion comprises a photodiode.
14. The method of claims 9, wherein the light emitting portion comprises an LED.
15. The method of claims 9, further comprising, before the dicing, removing a region of the semiconductor substrate so as to form a groove penetrating through the insulation film and the adhesive layer to cut into the supporting body along a dicing line of the dicing, and forming a protection film so as to cover the groove, wherein only the protection film and the supporting body is cut during the dicing.
16. The method of claims 9, further comprising forming a control circuit controlling at least one of the light receiving portion and the light emitting portion on the front surface of the semiconductor substrate.
17. A semiconductor device comprising:
a first substrate having a first opening and a second opening different from the first opening;
a second substrate made of a semiconductor and attached to the first substrate so as to cover the first and second opening;
a light emitting portion formed on the semiconductor substrate and configured to receive light through the first opening; and
a light emitting portion accommodated in the second opening and configured to emit light through the second opening.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method, comprising:
a processor of a computer determining one or more paths of a circuit to be tested, each path of said one or more paths independently comprising one or more nets;
selecting a set of quantitative, geometric or parametric features of said nets, said circuit having one or more pattern input points and one or more pattern observation points connected by said nets, each of said nets defined by an input point and all fan out paths to (i) input points of other nets of said nets or (ii) to said pattern observation points, each net of said nets comprising one or more connected segments;
selecting a unit of measure for each feature of said set of features;
assigning a weight to each said segment of said nets based on a number of said unit of measure of said feature in each segment of each fan out path of each of said nets; and
said processor generating a set of test patterns based on said weights assigned to each segment of each fan out path of each of said nets of said circuit.
2. The method of claim 1, further including:
applying said set of test patterns to said pattern input points and observing a resultant test pattern at said pattern observation points.
3. The method of claim 1, wherein said generating said set of test patterns includes selecting a subset of initial test patterns generated from a test netlist, said test netlist describing said nets of said integrated circuit and faults for testing said nets, said test netlist not including information relating to said weights assigned to each segment of said nets of said integrated circuit.
4. The method of claim 3, wherein said selecting said subset of said initial test patterns is based on said weights assigned to each segment of each fan out path of each of said nets of said circuit.
5. The method of claim 4, further including:
(a) calculating a physical test coverage, said physical test coverage defined as a ratio of a weighted sum of weights of segments associated with faults testable by said set of test patterns to a sum of all weights of all segments of said nets;
(b) changing said set of test patterns based on said physical test coverage ratio if said physical test coverage ratio is less than a target value; and
(c) repeating steps (a) and (b) until said ratio is equal to or greater than said target value or until a steps (a) and (b) have been repeated a predetermined number of times.
6. The method of claim 1, wherein said generating said set of test patterns includes creating test patterns from a weighted test netlist, said weighted test netlist including weights assigned to each segment of each of said nets of said circuit.
7. The method of claim 6, wherein said creating said test patterns includes:
(a) calculating one or more cost functions for each pattern observation point, each cost function consisting of a different combination of faults and each cost function including only and all faults between one pattern observation point and one pattern input point.
8. The method of claim 7, wherein a numerical value of a particular cost function is based on said weights associated to each fault included in said particular cost function.
9. The method of claim 8, further including:
(b) calculating a physical test coverage, said physical test coverage defined as a ratio of a sum of weights associated with all segments associated with faults testable by said set of test patterns to a sum of all weights of all segments of said nets;
(c) changing said set of test patterns based on said physical test coverage ratio if said physical test coverage ratio is less than a target value; and
(d) repeating steps (b) and (c) until said ratio is equal to or greater than said target value or until a steps (b) and (c) have been repeated a predetermined number of times.
10. The method of claim 1, wherein said features are selected from the group consisting of wire length, number of vias, number of particular circuit element type, number of occurrences of a wire crossing another wire, number of wires spaced apart a certain distance, number of wires having a certain number of direction changes, number of wires spaced apart a specified distance from other wires, total area of a net, critical area of a net, device deign parameter, transistor threshold voltage, operating voltage level and clock domain.

1. Folding box, comprising:
a base,
first and second side walls which, together with the base, form a box open at the top in the folded open state,
at least one retaining element disposed on a first side wall,
at least one pin mounted so as to be rotatable on a second side wall,
wherein the at least one pin has a cross-section that is not circular on at least one pin end and the at least one pin end locks the first to the second side wall via the retaining element in a first rotational position and unlocks said side walls in a second rotational position, and
wherein the at least one pin can be automatically rotated into the second rotational position as the second side wall is folded open.
2. Folding box according to claim 1, wherein the at least one pin end has a cross-section selected from the group comprising rectangular with rounded corners, S-shaped, oval, ellipsoid, hook-shaped or a flattened circular cross-section.
3. Folding box according to claim 1, wherein the at least one pin can be automatically rotated into the first rotational position with the aid of a spring.
4. Folding box according to claim 3, wherein the at least one pin can be automatically rotated into the first rotational position with the aid of the spring once the second side wall has assumed an end position.
5. Folding box according to claim 1, wherein the at least one pin can be rotated into the first andor second rotational position via a handle.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A compound of formula (I)
wherein
A1, A2, A3 and A4 are independently of one another C\u2014H, C\u2014R5, or nitrogen;
R1 is -(D)m-(E)n-(D)p-R6;
each D is independently C1-C6alkylene;
E is \u2014O\u2014, \u2014(CO)\u2014 or \u2014(CO)NH\u2014;
m, n and p are independently 0 or 1, provided that where n is 0, p is not 1 and than where n is 1, m is not 0;
R2 is hydrogen, C1-C8alkyl, C1-C8alkylcarbonyl-, or C1-C8alkoxycarbonyl-;
R3 is C1-C8haloalkyl;
R4 is aryl or aryl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-, or heterocyclyl or heterocyclyl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-;
each R5 is independently halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-; and
R6 is hydrogen, or
R6 is C1-C8alkyl or C1-C8alkyl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-, or
R6 is C2-C8alkenyl or C2-C8alkenyl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-, or
R6 is C2-C8alkynyl or C2-C8alkynyl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-, or
R6 is C3-C8cycloalkyl, or C3-C8halocycloalkyl, or
R6 is aryl or aryl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-, or
R6 is heterocyclyl or heterocyclyl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-; or a salt or N-oxide thereof.
2. A compound according to claim 1 wherein A1 is C\u2014H or C\u2014R5.
3. A compound according to claim 1 wherein A2 is C\u2014H or C\u2014R5.
4. A compound according to claim 1 wherein A3 is C\u2014H or C\u2014R5.
5. A compound according to any claim 1 wherein A4 is C\u2014H or C\u2014R5.
6. A compound according to claim 1 wherein R1 is R6\u2014, R6\u2014C1-C6alkyl-, R6-oxy-C1-C6alkyl-, R6-carbonyl-C1-C6alkyl-, R6-amino-carbonyl-C1-C6alkyl-, or R6\u2014C1-C6alkoxy-C1-C6alkyl-.
7. A compound according to claim 1 wherein each D is independently \u2014CH2\u2014, \u2014CH2\u2014CH2\u2014, \u2014CH(Me)\u2014, or \u2014CH2\u2014CH2\u2014CH2\u2014.
8. A compound according to claim 1 wherein E is \u2014O\u2014 or \u2014(CO)\u2014.
9. A compound according to claim 1 wherein R2 is hydrogen, methyl, ethyl, methylcarbonyl-, or methoxycarbonyl-.
10. A compound according to claim 1 wherein R3 is chlorodifluoromethyl or trifluoromethyl.
11. A compound according to claim 1 wherein R4 is aryl or aryl substituted by one to three substituents independently selected from halogen, cyano, nitro, C1-C8alkyl, C1-C8haloalkyl, C1-C8alkoxy, C1-C8haloalkoxy, or C1-C8alkoxycarbonyl-.
12. A compound according to claim 1 wherein each R5 is independently bromo, chloro, fluoro, cyano, nitro, methyl, ethyl, trifluoromethyl, methoxy, difluoromethoxy, trifluoromethoxy, or methoxycarbonyl-.
13. A method of combating and controlling insects, acarines, nematodes or molluscs which comprises applying to a pest, to a locus of a pest, or to a plant susceptible to attack by a pest an insecticidally, acaricidally, nematicidally or molluscicidally effective amount of a compound of formula (I) as defined in claim 1.
14. An insecticidal, acaricidal, nematicidal or molluscicidal composition comprising an insecticidally, acaricidally, nematicidally or molluscicidally effective amount of a compound of formula (I) as defined in claim 1.