Author: claimsbot

1. An exposure apparatus, comprising:
a light source adapted to emit light;
a photomask in a path of the light between the light source and a semiconductor substrate, the photomask being in a mask plane (MP) and having patterns to be transcribed onto the semiconductor substrate; and
a spatial light modulator (SLM) in a first image correction region of the photomask between the light source and the photomask, the SLM being adapted to adjust a distribution of intensity of the light.
2. The exposure apparatus as claimed in claim 1, wherein the first image correction region extends to a first distance from a conjugate plane (CP) of the MP along a first direction and to a second distance from the CP of the MP along the second direction, each of the first and second distances being substantially equal to a thickness of the photomask, the first direction being opposite the second direction, the first and second directions being perpendicular to the CP.
3. The exposure apparatus as claimed in claim 1, wherein the semiconductor substrate is in a second image correction region of the photomask, the second image correction region of the photomask being different than the first image correction region of the photomask.
4. The exposure apparatus as claimed in claim 1, wherein the SLM includes a micromirror array adapted to reflect light delivered from the light source.
5. The exposure apparatus as claimed in claim 4, wherein the micromirror array includes a plurality of micromirrors, each micromirror of the plurality of micromirrors being adapted to adjust an angle thereof with respect to a surface supporting the micromirror array.
6. The exposure apparatus as claimed in claim 1, further comprising a polarization beam splitter (PBS) between the photomask and the SLM, the PBS being adapted to reflect light delivered from the light source toward the SLM.
7. The exposure apparatus as claimed in claim 6, further comprising a first quarter wavelength (\u03bb4) plate between the PBS and the SLM.
8. The exposure apparatus as claimed in claim 6, further comprising an aperture between the PBS and the SLM.
9. The exposure apparatus as claimed in claim 6, further comprising a first lens between the PBS and the SLM, the first lens being adapted to collimate from the PBS in.
10. The exposure apparatus as claimed in claim 9, further comprising a second lens between the first lens and the SLM, the second lens being adapted to focus light from the first lens.
11. The exposure apparatus as claimed in claim 10, further comprising a third lens between the second lens and the SLM, the third lens being adapted to collimate light from the second lens.
12. The exposure apparatus as claimed in claim 6, further comprising a micro-fly’s eye lens in the path of the light between the light source and the PBS.
13. The exposure apparatus as claimed in claim 12, further comprising a beam delivery module between the light source and the PBS.
14. The exposure apparatus as claimed in claim 6, further comprising a second quarter wavelength (\u03bb4) plate between the PBS and the photomask.
15. The exposure apparatus as claimed in claim 6, further comprising a fourth lens between the PBS and the photomask, the fourth lens being adapted to collimate light from the PBS.
16. An exposure apparatus, comprising:
a light source adapted to emit light;
a photomask in a path of the light between the light source and a
semiconductor substrate, the photomask having patterns to be transcribed onto the semiconductor substrate; and
a uniformity adjustment module between the light source and the photomask, the uniformity adjustment module including a polarization beam splitter (PBS) and a spatial light modulator (SLM), the PBS being adapted to reflect light delivered from the light source toward the SLM, and the SLM being adapted to adjust a distribution of intensity of the light.
17. The exposure apparatus as claimed in claim 16, wherein the SLM is in a first image correction region of the photomask between the light source and the photomask.
18. The exposure apparatus as claimed in claim 17, wherein the semiconductor substrate is disposed in a second image correction region of the photomask, the second image correction region of the photomask being different than the first image correction region of the photomask.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for fast forward error correction coding and decoding, the system comprising:
a transmitting device, wherein the transmitting device comprises:
a data source;
at least one forward error correction (FEC) encoder couple to the data source, wherein the at least one FEC encoder is adapted to encode data from the data source;
a channelizer coupled to the at least one FEC encoder, wherein the channelizer is adapted to interleave the encoded data among a plurality of communication channels;
wherein the data source is adapted to place control information prior to other information so that the control information is encoded and interleaved prior to the other information;
at least one receiving device, the at least one receiving device adapted to receive the plurality of communication channels, wherein the receiving device comprises:
a dechannelizer, wherein the dechannelizer is adapted to de-interleave the plurality of communication channels; and
a decoder coupled to the dechannelizer.
2. A system as in claim 1 wherein the at least one FEC encoder comprises a convolutional FEC encoder.
3. A system as in claim 2 wherein the convolutional FEC encode comprises a punctured convolutional FEC encoder.
4. A system as in claim 1 wherein the at least one FEC encoder comprises a block FEC encoder.
5. A system as in claim 1 wherein the decoder comprises a Viterbi decoder.
6. A system as in claim 5 wherein the Viterbi decoder comprises a hard decision Viterbi decoder.
7. A system as in claim 5 wherein the Viterbi decoder comprises a soft decision Viterbi decoder.
8. A communications system for fast forward error correction coding and decoding, the communications system comprising:
a transmission device, the transmission device comprising:
a data source;
a controller coder, wherein the controller coder is adapted to encode data from the data source;
a plurality of pseudo-noise (PN) code generators;
a plurality of mixers, the plurality of mixers adapted to spread encoded data from the controller coder, wherein the controller coder is further adapted to interleave the encoded data amongst the plurality of mixers according to a predetermined arrangement;
a plurality of modulators, the plurality of modulators adapted to modulate the interleaved PN code spread encoded data from the plurality of mixers onto at least one carrier frequency;
wherein the data source is adapted to place control information prior to other information so that the control information is encoded and interleaved prior to the other information;

a receiving device adapted to receive the at least one carrier frequency, wherein the receiving device comprises:
at least one decoder, wherein the at least one decoder comprises:
a plurality of PN code despreaders;
a de-interleaver coupled to the plurality of PN code despreaders, wherein the de-interleaver is adapted to reconstitute the encoded data from the data source; and
a FEC decoder.
9. A communications system as in claim 8 wherein the controller coder comprises a block FEC encoder.
10. A communications system as in claim 8 wherein the controller coder comprises a convolutional FEC encoder.
11. A communications system as in claim 8 wherein each of the plurality of PN code generators comprise a PN code substantially mutually orthogonal with each of the other PN codes.
12. A communications system as in claim 8 wherein the transmission device comprises a direct sequence code division multiple access (DS-CDMA) communications system.
13. A communications system as in claim 8 wherein the transmission device comprises a frequency hop code division multiple access (FH-CDMA) communications system.
14. A communications system as in claim 8 wherein the at least one decoder is a Viterbi decoder.
15. A method for fast forward error correction (FFEC) coding and decoding, the method comprising the steps of:
placing, in user data, control information prior to other information;
retrieving the user data;
encoding the user data according to a FEC scheme;
interleaving the FEC encoded data amongst a plurality of transmission channels;
transmitting the FEC encoded data, whereby the encoded and interleaved control information is transmitted prior to the encoded and interleaved other information;
receiving the plurality of transmission channels;
de-interleaving the FEC encoded data; and
FEC decoding the FEC encoded data to produce the user data.
16. A method as in claim 15 wherein the step of encoding the user data according to the FEC scheme further comprises the step of block FEC encoding the user data.
17. A method as in claim 15 wherein the step of encoding the user data according to the FEC scheme further comprises the step of convolutional FEC encoding the user data.
18. A method as in claim 15 wherein the step of transmitting the FEC encoded data further comprises the step of transmitting the FEC encoded data within a predetermined time frame.
19. A method as in claim 15 wherein the step of FEC decoding the FEC encoded data to produce the user data further comprises the step of Viterbi FEC decoding the FEC encoded data.
20. A method as in claim 15 wherein the step of FEC decoding further comprises the step of ReedSolomon FEC decoding the FEC encoded data.
21. A method for interleaving FEC coded packet data across multiple channels, the method comprising the steps of:
providing N transmission channels, where each N transmission channel comprises a transmit frame;
inserting channel preambles on each transmit frame; and
distributing next, after the channel preambles, the FEC packet data across each transmit frame, wherein the FEC packet data has control information placed prior to other information so that the control information is distributed prior to the other information.
22. A method as in claim 21 wherein the step of distributing, after the channel preambles, the FEC coded packet data across each transmit frame further comprises the step of distributing, FEC coded ATM packet data.
23. A method as in claim 21 wherein the step of distributing after the channel preambles, the FEC coded packet data across each transmit frame further comprises the step of distributing FEC coded control data.
24. A system for fast forward error correction data coding and decoding, the system comprising:
a communications device, wherein the communications device comprises:
a recordable media, the recordable media comprising a plurality of recordable tracks around which encoded packetized data may be interleaved;
a plurality of detectors adapted to read the interleaved encoded packetized data from the plurality of recordable tracks;

at least one receiving device, the at least one receiving device adapted to receive the interleaved encoded packetized data from the plurality of detectors, wherein the receiving device comprises:
a dechannelizer, wherein the dechannelizer is adapted to de-interleave the encoded packetized data from the plurality of detectors; and
a decoder coupled to the dechannelizer.
25. A system as in claim 24 further comprising:
a data source; and
at least one forward error correction (FEC) encoder coupled to the data source, wherein the at least one FEC encoder is adapted to encode packetized data from the data source.
26. A transmitting device that operates on data, the transmitting device comprising:
means for storing data, the means for storing placing control information in the data prior to placing other information in the data;
means for encoding the data, the means for encoding coupled to the means for storing data; and
means for interleaving the encoded data among a plurality of communication channels, the means for interleaving coupled to the means for encoding,
whereby the control information is encoded and interleaved prior to the other information.
27. The transmitting device of claim 26, wherein the transmitting device further comprises means for creating a single frame and means for placing the control information near a beginning of the single frame, wherein the single frame comprises a transmit frame on each of the communication channels.
28. A receiving device comprising:
means for de-interleaving data received from a plurality of communication channels, the received data having control information placed prior to other information so that the control information is received prior to the other information; and
means, coupled to the means for de-interleaving, for decoding the control information prior to decoding the other information.
29. The receiving device of claim 28, wherein the receiving device further comprises means for receiving a single frame, the single frame having the control information placed near a beginning of the single frame, wherein the single frame comprises a transmit frame on each of the communication channels.
30. A transmitting device that operates on data, the transmitting device comprising:
means for placing asynchronous transfer mode (ATM) information in the data prior to placing other information in the data;
means, coupled to the means for placing, for encoding the data; and
means, coupled to the means for encoding, for interleaving the encoded data among a plurality of communication channels,
whereby the ATM information is encoded and interleaved prior to the other information.

1. A compression device for applying compression treatment to a part of a patient’s body, the device comprising:
a wicking layer having a first face and a second face, the first face is applied to the skin and the second face is away from the skin, the wicking layer is adapted to move moisture;
at least one bladder defining a compression region constructed of bladder material generally overlying the second face of the wicking layer;
the wicking layer being joined to the bladder material, and
wherein a portion of the wicking layer is exposed from under the bladder material, the exposed portion of the wicking layer being within the compression region.
2. A compression device as set forth in claim 1 wherein the wicking layer has an average wicking rate in terms of distance of at least about 0.01 ins (0.0254 cms)
3. A compression device as set forth in claim 2 wherein the wicking layer has an average wicking rate in terms of distance of at least about 0.0375 ins (0.09525 cms).
4. A compression device as set forth in claim 1 wherein the wicking layer has an average wicking rate in terms of weight of fluid wicked of at least about 0.002 gs.
5. A compression device as set forth in claim 4 wherein the wicking layer has an average wicking rate in terms of weight of fluid wicked of at least about 0.0048 gs.
6. A compression device as set forth in claim 1 wherein the at least one bladder has openings extending therethrough, wherein the bladder comprises openings extending through the bladder in the compression region, the exposed portion of the wicking material being in at least partial registration with at least one of the openings.
7. A compression device as set forth in claim 2 wherein the rate of wicked moisture evaporating from the wicking layer through one of the openings is between about 0.5 mgminute and about 2.0 mgminute.
8. A compression device as set forth in claim 7 wherein the combined rate of wicked moisture evaporating through the openings combined is between about 20 mgminute and about 50 mgminute.
9. A compression device as set forth in claim 6 wherein each of the openings has a generally waterdrop shape including a wider end portion and a narrower end portion, at least some of the openings having the wider end portions being arranged nearer to a longitudinal edge of the at least one bladder than the narrower end portion.
10. A compression device as set forth in claim 9 wherein the openings are arranged so that a first set of the openings have wider end portions nearer the longitudinal edge and a second set of openings have wider end portions nearer to an opposite longitudinal edge of the at least one bladder.
11. A compression device as set forth in claim 9 wherein the openings of the first set are longitudinally offset from the openings of the second set.
12. A compression device as set forth in claim 9 wherein each of the openings has an area of about 0.61 in2.
13. A compression device as set forth in claim 9 wherein the openings comprise between about 4% and about 15% of the total surface area of the at least one bladder.
14. A compression device as set forth in claim 6 wherein a portion of the wicking layer is not in registration with the openings.
15. A compression device as set forth in claim 14 wherein a portion of the bladder material not defining the bladder has a peripheral opening therethrough, wherein the portion of the wicking layer is in registration with the peripheral opening.
16. A compression device as set forth in claim 6 wherein a total open percentage of the exposed portion of the wicking layer is at least about 20% of the at least one bladder.
17. A compression device as set forth in claim 6 wherein the wicking layer is breathable to allow body heat and moisture to dissipate therethrough and out the openings in the at least one bladder.
18. A compression device as set forth in claim 17 wherein the wicking layer is constructed of a mesh material.
19. A compression device as set forth in claim 1 further comprising an outer cover disposed over the at least one bladder so that the bladder is disposed between the outer cover and the wicking layer, the outer cover being breathable to allow heat and moisture moved to the exposed portion to evaporate and exit the device.
20. A compression device as set forth in claim 19 wherein the outer cover is constructed of a mesh material.
21. A compression device as set forth in claim 20 wherein loops of a hook-and-loop fastening system are formed on a majority portion of an outer surface of the outer cover.
22. A compression device as set forth in claim 19 wherein the outer cover and the wicking layer are secured only to a periphery of the at least one bladder to allow the bladder to move independently of the wicking layer and outer cover.
23. A compression device as set forth in claim 19 wherein the bladder layers are constructed of an unlaminated, stretchable PVC material, and wherein the outer cover restricts the amount of expansion of the at least one inflatable bladder when the bladder is being filled with fluid.
24. A compression device as set forth in claim 1 further comprising a flap disposed generally immediately laterally of the bladder, the flap being divided to define at least two fingers, each finger including a fastening component.
25. A compression device for applying compression treatment to a part of a wearer’s body, the device comprising:
a wicking layer having a first face and a second face, the first face is applied to the skin and the second face is away from the skin, the wicking layer is adapted to move moisture;
a bladder defining a compression region constructed of bladder material generally overlying the second face of the wicking layer;
the wicking layer being joined to a skin facing surface of the bladder material, and
wherein a portion of the wicking layer is in communication with at least one opening and further wherein the at least one opening is within the area defined by the compression region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Cryptography processor for carrying out operations for cryptographic applications, comprising:
a central processing unit for obtaining commands for executing an operation and for outputting results of an operation;
a co-processor coupled to the central processing unit, the co-processor comprising:
a plurality of calculating subunits, each calculating subunit comprising at least one arithmetical unit, wherein each calculating subunit further comprises a plurality of registers exclusively assigned to the arithmetical unit of the respective calculating subunit, and wherein each calculating subunit comprises a word length specified by the number width of the arithmetical unit; and
a single control unit coupled to each of the plurality of calculating subunits and arranged to sub-divide an operation into sub-operations, to distribute the sub-operations among the plurality of calculating subunits and to control the execution of the operation by the plurality of calculating subunits, wherein the single control unit is arranged to interconnect at least two calculating subunits in such a manner that the interconnected calculating subunits are adapted to perform a calculation with numbers whose word length is equal to the sum of the number widths of the interconnected calculating subunits,
the calculating subunits being implemented for carrying out the suboperations independently without any intervention on the part of the control unit, after the control unit has supplied the necessary command to the calculating unit;
wherein the plurality of calculating subunits, the central processing unit, and the single control unit are integrated on a single chip; and
wherein the single chip comprises a common supply current access for supplying the plurality of calculating subunits, the central processing unit, and the single control unit with current.
2. Cryptography processor as claimed in claim 1, wherein the operations for cryptographic applications include a modular exponentiation andor a modular multiplication.
3. Cryptography processor as claimed in claim 1, wherein each calculating subunit is arranged to process binary numbers with at least 512 digits and preferably at least 1024 or 2048 digits.
4. Cryptography processor as claimed in claim 1, which further comprises a memory associated only with the central processing unit.
5. Cryptography processor as claimed in claim 1, comprising:
a clock generation device for delivering a clock to the central processing unit, to the plurality of calculating subunits and to the single control unit, the clock generation device also being integrated on the single chip.
6. Cryptography processor as claimed in claim 1,
wherein the length of the plurality of registers assigned to a calculating subunit, and the length of the plurality of registers associated with another calculating subunit differ, such that the calculating subunits are adapted to carry out arithmetical calculations with numbers of differing lengths.
7. Cryptography processor as claimed in claim 1, wherein the number of registers associated with a calculating subunit is sufficient so as to hold operands for at least two sub-operations, wherein the processor is adapted to not transfer any operands between the co-processor and the central processing unit for the at least two sub-operations.
8. Cryptography processor as claimed in claim 7, wherein the single control unit further comprises:
a device for controlling, in terms of time, the operation of the calculating subunits, such that the order of the at least two sub-operations, the operands of which are stored in the registers of a calculating subunit, is adjustable.
9. Cryptography processor as claimed in claim 1, further comprising:
a device for switching off a selected calculating subunit if it is determined by the single control unit that there do not exist any sub-operations for the selected calculating subunit, so as to reduce the current consumption of the cryptography processor.
10. Cryptography processor as claimed in claim 1, wherein the single control unit is arranged to combine at least two calculating subunits into a cluster, such that a sub-operation is assigned to the cluster, so that this sub-operation is executable jointly by the calculating subunits of the cluster.
11. Cryptography processor as claimed in claim 1, wherein the arithmetical unit of at least one calculating subunit comprises a serialparallel calculating unit implemented such that a number of calculations are executable in parallel in one cycle, the number being equal to the digits of a number used in the calculation, and the same calculation as in the one cycle being performed in a different, later cycle in a serial manner using the result of the one cycle.
12. Cryptography processor as claimed in claim 11, wherein one calculating subunit is implemented for a modular multiplication so as to add, in the one cycle, a partial product to one result of a previous cycle, and so as to add, in a further cycle, the result of the latest cycle to a next partial product.
13. Cryptography processor as claimed in claim 12, wherein the arithmetical unit comprises a three-operands adder for a modular multiplication, which three-operands adder comprises, for each digit of a processed number:
a half adder for an addition without carry with three inputs and two outputs; and
a downstream full adder with two inputs and one output.
14. Cryptography processor for carrying out operations for cryptographic applications, comprising:
a central processing unit for obtaining commands for executing an operation and for outputting results of an operation;
a co-processor coupled to the central processing unit, the co-processor comprising:
a plurality of calculating subunits, each calculating subunit comprising at least one arithmetical unit, wherein each calculating subunit further comprises a plurality of registers exclusively assigned to the arithmetical unit of the respective calculating subunit, wherein the length of the plurality of registers associated with a first calculating subunit, and the length of the plurality of registers associated with a second calculating subunit differ from each other, and wherein the first and second calculating subunits are adapted to carry out arithmetical calculations with numbers of differing lengths corresponding to the differing lengths of the plurality of registers; and
a single control unit coupled to each of the plurality of calculating subunits and arranged to sub-divide an operation into sub-operations, to distribute the sub-operations among the plurality of calculating subunits and to control the execution of the operation by the plurality of calculating subunits,
said calculating subunits being implemented for carrying out the suboperations independently without any intervention on the part of the control unit, after the control unit has supplied the necessary command to the calculating unit;
wherein the plurality of calculating subunits, the central processing unit, and the single control unit are integrated on a single chip, and
wherein the single chip comprises a common supply current access for supplying the plurality of calculating subunits, the central processing unit, and the single control unit with current.
15. Cryptography processor for carrying out operations for cryptographic applications, comprising:
a central processing unit for obtaining commands for executing an operation and for outputting results of an operation;
a co-processor coupled to the central processing unit, the co-processor comprising:
a plurality of calculating subunits, each calculating subunit comprising at least one arithmetical unit, wherein each calculating subunit further comprises a plurality of registers exclusively assigned to the arithmetical unit of the respective calculating subunit, wherein the number of registers associated with a calculating subunit is sufficient so as to hold operands for at least two sub-operations; and
a single control unit coupled to each of the plurality of calculating subunits and arranged to sub-divide an operation into sub-operations, to distribute the sub-operations among the plurality of calculating subunits and to control the execution of the operation by the plurality of calculating subunits,
wherein the cryptography processor is adapted to not transfer any operands between the co-processor and the central processing unit for the at least two sub-operations,
and wherein the single control unit includes a device for controlling, in terms of time, the operation of the calculating subunits, such that the order of the at least two sub-operations, the operands of which are stored in the registers of a calculating subunit, is adjustable;
said calculating subunits being implemented for carrying out the suboperations independently without any intervention on the part of the control unit, after the control unit has supplied the necessary command to the calculating unit;
wherein the plurality of calculating subunits, the central processing unit, and the single control unit are integrated on a single chip, and
wherein the single chip comprises a common supply current access for supplying the plurality of calculating subunits, the central processing unit, and the single control unit with current.
16. Cryptography processor for carrying out operations for cryptographic applications, comprising:
a central processing unit for obtaining commands for executing an operation and for outputting results of an operation;
a co-processor coupled to the central processing unit, the co-processor comprising:
a plurality of calculating subunits, each calculating subunit comprising at least one arithmetical unit; and
a single control unit coupled to each of the plurality of calculating subunits and arranged to sub-divide an operation into sub-operations, to distribute the sub-operations among the plurality of calculating subunits and to control the execution of the operation by the plurality of calculating subunits; and
a device for switching off a selected calculating subunit or registers of a selected calculating subunit when it is determined by the single control unit that there do not exist any operations for the selected calculating subunit, so as to reduce the current consumption of the cryptography processor;
said calculating subunits being implemented for carrying out the suboperations independently without any intervention on the part of the control unit, after the control unit has supplied the necessary command to the calculating unit;
wherein the plurality of calculating subunits, the central processing unit, and the single control unit are integrated on a single chip, and
wherein the single chip comprises a common supply current access for supplying the plurality of calculating subunits, the central processing unit, and the single control unit with current.