1. A semiconductor storage device comprising:
multiple memory strings each having a plurality of memory cells connected in series, each of the memory cells having a charge storage layer and a control gate;
select transistors each provided for and connected in series with the memory cells of one of the memory strings;
first and second blocks each configured with a plural number of the memory strings;
word lines connected to the control gates of the memory cells; and
select gate lines each connected to a gate of one of the select transistors,
wherein: when data are written in the first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line; and when data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
2. The semiconductor storage device according to claim 1, wherein the multiple memory strings are divided into at least the first block and the second block.
3. The semiconductor storage device according to claim 1, wherein, when data are written in the first block, after the data are sequentially written in the memory cells in the memory string connected to the selected select gate line, another select gate line is selected and the data are sequentially written in the memory cells in the memory string connected to said another select gate line.
4. The semiconductor storage device according to claim 1, wherein, when data are written in the second block, after the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line, another word line is selected and the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to said another word line.
5. The semiconductor storage device according to claim 1, wherein:
an erasing operation carried out for a memory cell in the second block erases all of the memory cells in the second block, and
an erasing operation carried out for a memory cell in the first block erases less than all of the memory cells in the first block.
6. The semiconductor storage device according to claim 1, further comprising first and second self boost systems that are different from each other and configured to carry out the data write operation for the first and second blocks, respectively.
7. The semiconductor storage device according to claim 1, wherein
each of the memory cells in the first block is configured to hold data containing one bit, and
each of the memory cells in the second block is configured to hold data containing two or more bits.
8. The semiconductor storage device according to claim 1, further comprising:
plural dummy transistors each provided for a memory string and connected in series between the memory cells and the select transistor of the memory string, and
dummy word lines each connected to a gate of one of the dummy transistors,
wherein when data are erased, potentials on the dummy word lines decrease sequentially from one that is nearest the select gate line to one that is nearest the word lines.
9. A controller of a semiconductor storage device including: multiple memory strings each having a plurality of memory cells connected in series and divided into at least first and second blocks, each of the memory cells having a charge storage layer and a control gate; select transistors each provided for and connected in series with the memory cells of one of the memory strings; word lines connected to the control gates of the memory cells; and select gate lines each connected to a gate of one of the select transistors, the controller comprising:
an interface that is configured to receive a write command from a host; and
a control section that is configured to respond to the write command and write data in the semiconductor storage device in a first write mode or a second write mode,
wherein the control section, in the first write mode, after a select gate line is selected, sequentially writes the data in the memory cells in the memory string connected to the selected select gate line, and, in the second write mode, after a word line connected to the control gates of memory cells of different memory strings is selected, sequentially writes the data in the memory cells of the different memory strings which have their control gates connected to the selected word line.
10. The controller according to claim 9, wherein the control section, in the first write mode, after the data are sequentially written in the memory cells in the memory string connected to the selected select gate line, selects another select gate line and sequentially writes the data in the memory cells in the memory string connected to said another select gate line.
11. The controller according to claim 9, wherein the control section, in the second write mode, after the data are sequentially written in the memory cells of the different memory strings which have their control gates connected to the selected word line, selects another word line and sequentially writes the data in the memory cells of the different memory strings which have their control gates connected to said another word line.
12. The controller according to claim 9, wherein:
an erasing operation carried out for a memory cell in the second block erases all of the memory cells in the second block, and
an erasing operation carried out for a memory cell in the first block erases less than all of the memory cells in the first block.
13. The controller according to claim 12, wherein
each of the memory cells in the first block is configured to hold data containing one bit, and
each of the memory cells in the second block is configured to hold data containing two or more bits.
14. The controller according to claim 12, wherein the controls section is configured to access a table that indicates a write mode for each of the blocks.
15. A method of performing a data operation in a semiconductor storage device that includes: multiple memory strings each having a plurality of memory cells connected in series and divided into at least first and second blocks, each of the memory cells having a charge storage layer and a control gate; select transistors each provided for and connected in series with the memory cells of one of the memory strings; word lines connected to the control gates of the memory cells; and select gate lines each connected to a gate of one of the select transistors, said method comprising:
when writing data to the first block, selecting a gate line connected to the gate of a select transistor of one of the memory strings in the first block, and then sequentially writing the data in the memory cells in the memory string connected to the selected select gate line; and
when writing data to the second block, selecting a word line connected to the control gates of memory cells of different memory strings in the second block, and then sequentially writing the data in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
16. The method according to claim 15, wherein the multiple memory strings are divided into at least the first block and the second block.
17. The method according to claim 15, wherein, when data are written in the first block, after the data are sequentially written in the memory cells in the memory string connected to the selected select gate line, another select gate line is selected and the data are sequentially written in the memory cells in the memory string connected to said another select gate line.
18. The method according to claim 15, wherein, when data are written in the second block, after the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line, another word line is selected and the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to said another word line.
19. The method according to claim 15, wherein:
an erasing operation carried out for a memory cell in the second block erases all of the memory cells in the second block, and
an erasing operation carried out for a memory cell in the first block erases less than all of the memory cells in the first block.
20. The method according to claim 19, wherein
each of the memory cells in the first block is configured to hold data containing one bit, and
each of the memory cells in the second block is configured to hold data containing two or more bits.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A sport activity impact detection and image recording system comprising:
an impact detection device comprising;
a piezoelectric transducer for producing an electrical signal in response to impact;
a monitoring circuit;
a wireless transceiver for transmitting at least one impact detection signal containing impact notification data;
at least one portable camera device comprising:
a camera to capture a video of the sports activity;
a wireless transceiver to receive impact detection signal containing impact notification data from the impact detection device;
an image display unit;
a processor that performs functions comprising:
receiving the video from the camera;
receiving the impact detection signal and processing the impact notification data from the wireless transceiver;
saving a video in slow motion or normal speed;
concatenating a plurality of the video to make one a single video for purposes of review, comment and sharing;
saving the video in local memory or on a server;
saving the impact notification data along with the video;
replaying the saved video on the image display unit;
executing an application program to allow interaction with the camera, wireless transceiver and impact detection device;
wherein upon detection of impact by the monitoring circuit, the impact detection device transmits the impact notification data wirelessly,
wherein the at least one portable camera device upon receiving impact notification from the impact detection device can record a video of sport activity around the time of impact.
2. The system of claim 1, wherein the impact detection device can be attached to a players body.
3. The system of claim 1, wherein the impact detection device can be attached to the sports equipment.
4. The system of claim 1, wherein the duration of the video of sport activity taken before the time of impact is user configurable from 0 to 3 seconds.
5. The system of claim 1, wherein the duration of the video of sport activity taken after the time of impact is user configurable from 0 to 3 seconds.
6. The system of claim 1, wherein the portable camera device records video at a user configurable video frame rate.
7. The system of claim 1, wherein the impact notification data being sent includes one or more elements selected from a group comprising:
time of impact;
notification of impact detection;
impact related information.
8. The system of claim 7, wherein the impact related information includes one or more elements selected from a group comprising:
amplitude of the impact;
signal to noise ratio of the piezeoelectric signal generated from the impact.
9. The system of claim 1, wherein the processor operates on the impact notification data and generates a performance value comprising:
force value;
speed;
acceleration.
10. The system of claim 7, wherein the impact related information is saved along with the corresponding saved video.
11. The system of claim 1, wherein the at least one portable camera device captures a still image at a plurality of user configurable pre-determined times around the time of impact.
12. The system of claim 11, wherein the impact related information is saved along with the still images.
13. The system of claim 1, wherein the monitoring circuit comprises:
an analog to digital convertor to translate the signal provided by the piezoelectric transducer into a digital signal;
a microprocessor performing one or more functions in a group comprising:
run algorithms to detect impact;
communicate the impact detection signal to the portable camera device wirelessly;
communicate user input to the portable camera device wirelessly.
14. The system of claim 13, wherein the impact detection is determined by the amplitude of the input data provided by the analog to digital convertor exceeding a specified threshold.
15. The system of claim 13, wherein the impact detection is determined by the signal to noise ratio of the input data provided by the analog to digital convertor exceeding a specified threshold.
16. The system of claim 15, wherein the signal to noise ratio is determined by method comprising the steps of:
obtaining the signal which is the output of a moving average filter of the absolute value of the incoming samples whose absolute value exceeds a pre-determined threshold;
obtaining the noise which is the output of the moving average filter of the incoming signal whose absolute value is below a pre-determined threshold;
dividing the signal by the noise.
17. The system of claim 1, wherein the sport activity impact for each sport is defined from (a) to (l):
a. a tennis racquet hitting a tennis ball;
b. a cricket bat hitting a cricket ball;
c. a baseball bat hitting a baseball ball;
d. a badminton racquet hitting a shuttle cock;
e. a squash racquet hitting a squash ball;
f. a racquetball racquet hitting a racquetball ball;
g. an ice hockey stick hitting a puck;
h. a field hockey stick hitting a ball;
i. a boxing glove hitting a boxing bag;
j. a players hand hitting a volleyball;
k. a basketball hitting the hoop;
l. a table tennis bat hitting a table tennis ball.
18. The system of claim 1, wherein the application program running on the processor provides a user interface to execute one or more functions in a group comprising:
connect and disconnect to the impact detection device;
start and stop video recording;
review the captured videos;
add comments after reviewing the video;
edit and save snippets of the captured video;
configure parts of the video to be shown in slow motion to allow detailed review of the user action;
edit and save the captured images;
review the captured images;
configuring the video frame rate;
configuring whether to take images in addition to the video;
configuring length of video capture;
configuring plurality of times when the still image is taken.
19. The system of claim 1, wherein the portable camera device is a smart phone.
20. The system of claim 1, wherein the portable camera device is selected from the group comprising of:
tablet;
digital camera;
portable computer.