Author: claimsbot

What is claimed is:

1. A hair extension system comprising:
a tube having a central tube opening therethrough, the tube formed of a malleable material capable of being flattened and opened reversibly;
a strand of extension hair inserted through the tube opening and attached to the tube by an attaching means on one side of the tube adjacent to a first end of the strand of extension hair so that the extension hair is restricted to occupying a first portion of the opening and a second portion of the opening remains open so that the second portion of the opening is capable of receiving a strand of existing hair from a person, the strand of existing hair being drawn through the second portion of the opening adjacent to the extension hair in the opening and the tube is capable of being reversibly compressed to bind the two strands of hair within the flattened tube and subsequently the tube is capable of being opened to permit the tube to be repositioned on the stand of existing hair and recompressed to bind the two strands therein.
2. The system of claim 1 wherein the attaching means comprises an adhesive attaching means for gluing the stand of extension hair onto the tube.
3. The system of claim 1 wherein the attaching means comprises a threaded attaching means for sewing the stand of extension hair onto the tube.
4. The system of claim 3 wherein the threaded attaching means comprises sewing at least one of the strands of extension hair onto the tube.
5. The system of claim 3 wherein the threaded attaching means comprises sewing an external threading means between the strand of extension hair and the tube.
6. The system of claim 1 wherein the tube has a longitudinal split in the tube running parallel to the strand of extension hair.
7. The system of claim 1 wherein the tube is capable of being folded in half into a compressed V shape after being compressed.
8. The system of claim 7 further comprising a bending tool comprising a pair of opposing pivotable faces with a V-shaped protrusion on one of the pair of faces and a mating V-shaped recess on the other of the pair of faces, the bending tool capable of forming the compressed tube into a V shape.
9. The system of claim 8 further comprising a compressing tool comprising a pair of opposing pivotable flat faces capable of compressing the tube after the existing strand of hair is drawn into the opening and further capable of compressing the tube again after the tube is formed into a V shape.
10. The system of claim 9 further comprising an opening tool comprising a pair of opposing facing pointed wedge elements capable of being inserted into the opening after the tube is compressed and prying apart the compressed tube to reopen the tube to permit sliding the tube along the strand of existing hair.
11. A hair extension method comprising:
a first step of forming a tube having a central tube opening therethrough, the tube formed of a malleable material capable of being flattened and opened reversibly;
a second step of attaching a strand of extension hair inserted through the tube opening and attached to the tube by an attaching means on one side of the tube adjacent to a first end of the strand of extension hair so that the extension hair is restricted to occupying a first portion of the opening and a second portion of the opening remains open so that the second portion of the opening is capable of receiving a strand of existing hair from a person,
a third step of drawing a strand of existing hair through the second portion of the opening adjacent to the extension hair in the opening and the tube is capable of being reversibly compressed to bind the two strands of hair within the flattened tube;
a fourth step of compressing the tube to bind the two strands of hair within the flattened tube and subsequently the tube is capable of being opened to permit the tube to be repositioned on the stand of existing hair and recompressed to bind the two strands therein.
12. The method of claim 11 wherein the attaching means comprises an adhesive attaching means for gluing the stand of extension hair onto the tube and the second step comprises attaching the extension hair by gluing it to the tube.
13. The method of claim 11 wherein the attaching means comprises a threaded attaching means for sewing the stand of extension hair onto the tube and the second step comprises attaching the extension hair by sewing it to the tube.
14. The method of claim 13 wherein the second step comprises sewing at least one of the strands of extension hair onto the tube.
15. The method of claim 14 wherein the second step comprises sewing an external threading means between the strand of extension hair and the tube.
16. The method of claim 11 wherein the tube has a longitudinal split in the tube running parallel to the strand of extension hair and the fourth step comprises crimping the tube with the slit at a central point in the tube after compressing the tube and further comprising a fifth step of bending the flattened tube into a V shape.
17. The method of claim 16 further comprising a sixth step of compressing the V shape tube into a flattened folded over tube.
18. The method of claim 16 further comprising a bending tool comprising a pair of opposing pivotable faces with a V-shaped protrusion on one of the pair of faces and a mating V-shaped recess on the other of the pair of faces, wherein the fifth step comprises using the bending tool to form the compressed tube into the V shape.
19. The method of claim 18 further comprising a compressing tool comprising a pair of opposing pivotable flat faces and the fourth step comprises using the compressing tool to compress the tube after the existing strand of hair is drawn into the opening and the sixth step comprises using the compressing tool to compress the tube again after the tube is formed into a V shape.
20. The method of claim 19 further comprising an opening tool comprising a pair of opposing facing pointed wedge elements capable of being inserted into the opening after the tube is compressed and further comprising a seventh step of prying apart the compressed tube to reopen the tube to permit sliding the tube along the strand of existing hair.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A surface emitting laser comprising:
a resonator;
a first reflector; and
a second reflector,
wherein the resonator and the first and second reflectors are provided on a substrate,
wherein the resonator includes an active region and a current confinement region,
wherein the resonator includes a first refractive index region that is located at a central portion of the resonator and a second refractive index region that is located at a peripheral portion of the resonator and that is lower than the first refractive index region in effective refractive index,
wherein a resonator length I1 of a first region of the resonator that includes the first refractive index region causes the first region of the resonator to satisfy a resonance condition, and a resonator length I2 of a second region of the resonator that includes the second refractive index region causes the second region of the resonator not to satisfy the resonance condition,
wherein the first refractive index region is equal in physical length to that of the second refractive index region, and
wherein the resonator length I1 of the region including the first refractive index region and the resonator length I2 of the region including the second refractive index region satisfy the following conditional expressions:
I1=I2,
I1=N\u03bb(2nh),
I2=(N\u22121)\u03bb2nh+\u03bb4nl, and
nh>nl,
in which N is an integer equal to or larger than two, where \u03bb indicates an oscillation wavelength, nh indicates an effective refractive index of a fundamental mode selection region, and nl indicates an effective refractive index of a high-order mode oscillation suppression region.
2. A surface emitting laser according to claim 1, wherein the second refractive index region is formed by processing a part of a layer which corresponds to the first refractive index region to reduce an effective refractive index of the layer.
3. A surface emitting laser according to claim 1, wherein the second refractive index region is formed by replacing a part of a layer which corresponds to the first refractive index region with a material lower in refractive index than the layer.
4. A surface emitting laser according to claim 1, wherein the surface emitting laser is one of multiple surface emitting lasers of a surface emitting laser array.
5. A surface emitting laser according to claim 4, wherein the surface emitting laser array is incorporated in an image forming apparatus as a light source for exposure.

1. An ink for ink-jet recording comprising:
water;
a water-soluble organic solvent;
a water-soluble N-hydroxy cyclic imide compound;
a self-dispersible pigment; and
a surfactant of sulfuric acid ester salt type.
2. The ink for ink-jet recording according to claim 1, wherein the N-hydroxy cyclic imide compound is N-hydroxysuccinimide or N-hydroxyphthalimide.
3. The ink for ink-jet recording according to claim 1, wherein the self-dispersible pigment is modified by at least one functional group selected from the group consisting of carboxyl group, phosphate group, and salt thereof.
4. The ink for ink-jet recording according to claim 1, wherein the surfactant of sulfuric acid ester salt type is a surfactant of alkyl sulfuric acid ester salt type or a surfactant of alkyl ether sulfuric acid ester salt type represented by a general formula (1);
R1O\u2014(R2O)n\u2014SO3M\u2003\u2003(1)
in the general formula (1), R1 is an alkyl group, R2 is an ethylene group or a propylene group, n is 0 to 10, M is an alkali metal, an alkali earth metal, ammonium, or alkanolamine.
5. The ink for ink-jet recording according to claim 1, wherein the surfactant of sulfuric acid ester salt type is a surfactant of alkyl ether sulfuric acid ester salt type including a polyoxyethylene structure.
6. The ink for ink-jet recording according to claim 1, wherein the N-hydroxy cyclic imide compound is contained in an amount ranging from 0.01% by mass to 2% by mass.
7. The ink for ink-jet recording according to claim 6, wherein the N-hydroxy cyclic imide compound is contained in an amount ranging from 0.05% by mass to 1.0% by mass.
8. The ink for ink-jet recording according to claim 1, wherein the N-hydroxy cyclic imide compound is contained in an amount of not less than 0.50% by mass.
9. The ink for ink-jet recording according to claim 1, wherein a mass ratio (X:Y) of the N-hydroxy cyclic imide compound (X) to the surfactant of sulfuric acid ester salt type (Y) is 1:0.1 to 1:1.
10. An ink-jet recording method which performs recording on a recording medium comprising:
preparing the ink for ink-jet recording as defined in claim 1; and
discharging the ink onto the recording medium.
11. An ink-jet recording apparatus which performs recording on a recording medium, comprising:
an ink accommodating section in which the ink for ink-jet recording as defined in claim 1 is accommodated; and
an ink discharge mechanism which discharges the ink onto the recording medium.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A branch control apparatus in a microprocessor having an instruction cache, coupled to an address bus, for providing cache lines to an instruction buffer, the apparatus comprising:
a target address of a branch instruction, said target address provided by a branch target address cache (BTAC);
a wrap signal, originating directly from said BTAC, for indicating whether said branch instruction wraps across first and second cache lines of said instruction cache; and
an address register, coupled to said BTAC, for storing said target address;
wherein if said wrap signal indicates said branch instruction wraps across said first and second cache lines, said address register provides said target address on the address bus to the instruction cache to select a third cache line, said third cache line containing a target instruction of said branch instruction.
2. The branch control apparatus of claim 1, wherein said address register provides said target address on the address bus after a fetch address for said second cache line is provided on the address bus.
3. The branch control apparatus of claim 2, wherein said BTAC is coupled to the address bus, wherein said BTAC provides said target address in response to a fetch address provided on the address bus.
4. The branch control apparatus of claim 3, wherein said BTAC provides said target address in response to a fetch address of said first cache line.
5. The branch control apparatus of claim 4, wherein said first cache line contains a first portion of said branch instruction.
6. A pipelined microprocessor, comprising:
an instruction cache, coupled to an address bus configured to receive a first fetch address for selecting a first cache line;
a branch target address cache (BTAC), coupled to said address bus, for storing and directly providing a wrap indicator for indicating whether a branch instruction wraps beyond said first cache line;
an address register, coupled to said BTAC, for storing a target address of said branch instruction, said target address provided by said BTAC; and
a multiplexer, coupled to receive said target address from said address register and coupled to receive a second fetch address that specifies a second cache line containing a portion of said branch instruction wrapping beyond said first cache line, wherein if said wrap indicator is true, said multiplexer selects said second fetch address for provision onto said address bus and subsequently
selects said target address from said address register for provision onto said address bus, after selecting said second fetch address for provision onto said address bus.
7. The pipelined microprocessor of claim 6, wherein said multiplexer selects said second fetch address after selecting said first fetch address.
8. The pipelined microprocessor of claim 6, wherein said BTAC provides said target address in response to said first fetch address received on said address bus.
9. The pipelined microprocessor of claim 6, wherein said second fetch address is a next sequential fetch address to said first fetch address.
10. The pipelined microprocessor of claim 6, wherein said multiplexer selects said target address for selecting a third cache line in said instruction cache, said third cache line containing a target instruction of said branch instruction.
11. The pipelined microprocessor of claim 10, wherein said multiplexer selects said first fetch address, said second fetch address and said target address for causing said first, second and third cache lines to be stored in order in an instruction buffer.
12. A branch control apparatus in a microprocessor, comprising:
a branch target address cache (BTAC), for caching indications of whether previously executed branch instructions wrap across two cache lines and for directly providing said indications;
a register, coupled to said BTAC, for receiving from said BTAC a target address of one of said previously executed instructions stored therein; and
control logic, coupled to said BTAC, for receiving one of said indications associated with said one of said previously executed branch instructions;
wherein if said one of said indications indicates said one of said previously executed branch instructions wraps across two cache lines, said control logic causes the microprocessor to branch to said target address, after causing said two cache lines containing said one of said previously executed branch instructions to be fetched.
13. The branch control apparatus of claim 12, wherein said control logic is configured to cause a first of said two cache lines containing a portion of said one of said previously executed branch instructions to be fetched from an instruction cache.
14. The branch control apparatus of claim 13, wherein said control logic is configured to receive a miss indicator from said instruction cache.
15. A microprocessor branch control apparatus, comprising:
an incrementer, coupled to an instruction cache address bus, for providing a first fetch address on said address bus, said first fetch address selecting a first cache line containing a first portion of a branch instruction;
a branch target address cache (BTAC), coupled to said address bus, for providing a target address of said branch instruction in response to said first fetch address, and for caching and directly providing an indication of whether said branch instruction wraps beyond said first cache line; and
an address register, coupled to said BTAC, for storing said target address if said BTAC indicates said branch instruction wraps beyond said first cache line;
wherein said incrementer provides a second fetch address on said address bus, said second fetch address selecting a second cache line containing a second portion of said branch instruction;
wherein said address register provides said target address on said address bus, said target address selecting a third cache line containing a target instruction of said branch instruction.
16. The microprocessor branch control apparatus of claim 15, further comprising:
a flag register, for storing an indication that said address register stores said target address of said branch instruction that wraps beyond said first cache line.
17. A method for performing branches in a microprocessor with an instruction cache, the method comprising:
storing in a branch target address cache an indication of whether a previously executed branch instruction wraps beyond a first cache line containing at least a portion of said branch instruction, and said branch target address cache directly providing the indication;
applying a first fetch address to the instruction cache for selecting said first cache line containing at least a portion of a branch instruction, after said storing said indication;
providing a target address of said branch instruction and said indication in response to said first fetch address;
determining whether said branch instruction wraps beyond said first cache line based on said indication;
storing said target address in a register if said branch instruction wraps beyond said first cache line;
applying a second fetch address to the instruction cache, if said branch instruction wraps beyond said first cache line, for selecting a second cache line containing a remainder of said branch instruction; and
providing said target address from said register to the instruction cache for selecting a third cache line containing a target instruction of said branch instruction.
18. The method of claim 17, further comprising:
determining whether said second fetch address misses in said instruction cache.
19. The method of claim 17, further comprising: storing said first, second and third cache lines in an instruction buffer.
20. The method of claim 19, wherein said storing said first, second and third cache lines in said instruction buffer comprises storing said first, second and third cache lines in said instruction buffer in order.