Author: claimsbot

1. A method for forming a MOS transistor, comprising:
providing a substrate;
sequentially forming a composite layer for forming a gate structure and a carbon-containing mask material layer on the substrate, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction gas;
patterning the carbon-containing mask material layer and the composite layer into a carbon-containing hard mask layer and a gate structure, respectively;
forming a spacer on sidewalls of the gate structure and the carbon-containing hard mask layer;
forming a passivation layer over the substrate;
removing a portion of the passivation layer to expose an area of the substrate; and
forming a doped epitaxial layer in the exposed area of the substrate.
2. The method of claim 1, wherein the carbon-containing precursor gas comprises bis(t-butylamino)silane, tetraethylorthosilicate (TEOS), triethoxysilane or hexamethyl-disiloxane (HMDS).
3. The method of claim 1, wherein a flow rate of the carbon-containing precursor gas is set constant during formation of the carbon-containing mask material layer.
4. The method of claim 1, wherein a flow rate of the carbon-containing precursor gas is varied with time during formation of the carbon-containing mask material layer.
5. The method of claim 2, wherein the carbon-containing precursor gas comprises bis(t-butylamino)silane and has a flow rate set within a range of about 100-235 sccm.
6. The method of claim 2, wherein the carbon-containing precursor gas comprises tetraethylorthosilicate and has a flow rate set within a range of about 100-1000 sccm.
7. The method of claim 2, wherein the carbon-containing precursor gas comprises triethoxysilane and has a flow rate set within a range of about 100-1000 sccm.
8. The method of claim 2, wherein the carbon-containing precursor gas comprises hexamethyldisiloxane and has a flow rate set within a range of about 100-500 sccm.
9. The method of claim 1, wherein the carbon-containing mask material layer comprises carbon-containing oxide, carbon-containing oxynitride or carbon-containing nitride.
10. The method of claim 9, wherein the carbon-containing mask material layer comprises carbon-containing oxide or carbon-containing oxynitride, and the reaction gas comprises O2, O3, NO or N2O.
11. The method of claim 9, wherein the carbon-containing mask material layer comprises carbon-containing nitride, and the reaction gas comprises N2 or NH3.
12. The method of claim 1, wherein the carbon-containing mask material layer is formed through APCVD, LPCVD, PECVD, HDP-CVD, RECVD, ALD or ALCVD.
13. The method of claim 1, wherein the spacer is a composite spacer comprising a first spacer on the sidewalls of the gate structure and the carbon-containing hard mask layer and a second spacer on a sidewall of the first spacer.
14. The method of claim 13, wherein the first spacer and the second spacer comprise different materials selected from a group consisting of SiO, SiN and SiON at least.
15. The method of claim 1, further comprising removing a portion of the exposed substrate to form a trench after a portion of the passivation layer is removed but before the doped epitaxial layer is formed, wherein the doped epitaxial layer fills up the trench at least.
16. The method of claim 1, further comprising forming a stress layer over the substrate after the doped epitaxial layer is formed.
17. The method of claim 16, further comprising removing a portion of the spacer after the doped epitaxial layer is formed but before the stress layer is formed.
18. The method of claim 1, further comprising removing the passivation layer after the doped epitaxial layer is formed.
19. The method of claim 1, wherein the MOS transistor is a PMOS transistor, and the doped epitaxial layer comprises P-doped SiGe.
20. The method of claim 1, wherein the MOS transistor is an NMOS transistor, and the doped epitaxial layer comprises N-doped Si\u2014C alloy.
21. A method for fabricating a MOS transistor, comprising:
providing a substrate;
sequentially forming, on the substrate, a composite layer for forming a gate structure and a composite mask material layer that comprises at least one carbon-containing layer, wherein at least one carbon-containing layer is formed with a carbon-containing precursor gas and a reaction gas;
patterning the composite mask material layer and the composite layer for forming a gate structure into a composite hard mask layer and a gate structure, respectively;
forming a spacer on sidewalls of the gate structure and the composite hard mask layer;
forming a passivation layer over the substrate;
removing a portion of the passivation layer to expose an area of the substrate; and
forming a doped epitaxial layer in the exposed area of the substrate.
22. The method of claim 21, wherein the carbon-containing precursor gas comprises bis(t-butylamino)silane, tetraethyl-orthosilicate (TEOS), triethoxysilane or hexamethyldisiloxane (HMDS).
23. The method of claim 21, wherein a flow rate of the carbon-containing precursor gas is set constant during formation of the carbon-containing layer.
24. The method of claim 21, wherein a flow rate of the carbon-containing precursor gas is varied with time during formation of the carbon-containing layer.
25. The method of claim 22, wherein the carbon-containing precursor gas comprises bis(t-butylamino)silane and has a flow rate set within a range of about 100-235 sccm.
26. The method of claim 22, wherein the carbon-containing precursor gas comprises tetraethylorthosilicate and has a flow rate set within a range of about 100-1000 sccm.
27. The method of claim 22, wherein the carbon-containing precursor gas comprises triethoxysilane and has a flow rate set within a range of about 100-1000 sccm.
28. The method of claim 22, wherein the carbon-containing precursor gas comprises hexamethyldisiloxane and has a flow rate set within a range of about 100-500 sccm.
29. The method of claim 21, wherein the carbon-containing layer comprises carbon-containing oxide, carbon-containing oxynitride or carbon-containing nitride.
30. The method of claim 29, wherein the carbon-containing layer comprises carbon-containing oxide or carbon-containing oxynitride, and a reaction gas for forming the carbon-containing layer contains O2, O3, NO or N2O.
31. The method of claim 29, wherein the carbon-containing layer comprises carbon-containing nitride, and the reaction gas comprises N2 or NH3.
32. The method of claim 21, wherein the carbon-containing layer is formed with APCVD, LPCVD, PLC VD, I-IDP-CVD, RECVD, ALD or ALCVD.
33. The method of claim 21, wherein the spacer is a composite spacer comprising a first spacer on the sidewalls of the gate structure and the composite hard mask layer and a second spacer on a sidewall of the first spacer.
34. The method of claim 33, wherein the first and the second spacers comprise different materials selected from a group consisting of SiO, SiN and SiON at least.
35. The method of claim 21, further comprising removing a portion of the exposed substrate to form a trench after a portion of the passivation layer is removed but before the doped epitaxial layer is formed, wherein the doped epitaxial layer fills up the trench at least.
36. The method of claim 21, further comprising forming a stress layer over the substrate after the doped epitaxial layer is formed.
37. The method of claim 36, further comprising removing a portion of the spacer after the doped epitaxial layer is formed but before the stress layer is formed.
38. The method of claim 21, further comprising removing the passivation layer after the doped epitaxial layer is formed.
39. The method of claim 21, wherein the MOS transistor is a PMOS transistor, and the doped epitaxial layer comprises P-doped SiGe.
40. The method of claim 21, wherein the MOS transistor is an NMOS transistor, and the doped epitaxial layer comprises N-doped Si\u2014C alloy.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-10. (canceled)
11. Pharmaceutical composition, comprising
at least two different antibiotics of group A\u2032 or pharmaceutically acceptable derivatives or salts thereof or
an antibiotic of group A1 and at least one antibiotic of group B1 or pharmaceutically acceptable derivatives or salts thereof, wherein
group A\u2032 comprises
ansamycins, particularly rifamycins such as rifampin, rifabutin, rifapentine or rifamixin,
fluoroquinolones, particularly moxifloxaci.n,
streptogramins, particularly quinupristin andor dalfopristin, and
group B\u2032 comprises
glycopeptides, particularly vancomycin or teicoplanin,
fosfomycin,
polypeptides, particularly bacitracin, polymyxin B, other polymyxins, and daptomycin,
aminoglycosides, particularly arbekacin,
wherein
glycopeptides cannot be the second antibiotic of a composition comprising only two antibiotics and comprising an ansamycin as first antibiotic.
12. Pharmaceutical composition according to claim 11 comprising at least one rifamycin and fosfomycin.
13. Pharmaceutical composition according to claim 12 comprising rifamycin and fosfomycin in such a concentration that the rifamycin reaches a concentration of 0.005 to 100 \u03bcgml, preferably 0.006 to 80 \u03bcgml, most preferably 0.0075 to 10 \u03bcgml at the site to be treated, and fosfomycin reaches a concentration of 1 to 1000 \u03bcgml, preferably 5 to 800 \u03bcgml, most preferably 10 to 200 \u03bcgml fosfomycin at the site to be treated.
14. Pharmaceutical composition according to claim 11 comprising at least one rifamycin and daptomycin.
15. Pharmaceutical composition according to claim 14 comprising rifamycin and daptomycin in such a concentration that the rifamycin reaches a concentration of 0.005 to 100 \u03bcgml, preferably 0.006 to 80 \u03bcgml, most preferably 0.0075 to 20 \u03bcgml at the site to be treated, and daptomycin reaches a concentration of 0.1 to 100 \u03bcgml, preferably 0.5 to 80 \u03bcgml, most preferably 1 to 20 \u03bcgml at the site to be treated.
16. Pharmaceutical composition for treatment of extracellular andor intracellular microbial infected cells andor for the prevention of microbial infections of cells comprising at least one antibiotic acting as an inhibitor of bacterial RNA polymerase, at least one antibiotic affecting the bacterial cell wall or its synthesis andor at least one antibiotic acting as a gyrase inhibitor.
17. Pharmaceutical composition according to claim 16 comprising ansamycins, particulary rifamycins such as rifampin, rifabutin, rifapentine or rifamixin as inhibitors of bacterial RNA polymerase.
18. Pharmaceutical composition according to claim 16 comprising glycopeptides, particularly vancomycin or teicoplanin, fosfomycin and polypeptides, particularly bacitracin and daptomycin as antibiotics affecting the bacterial cell wall or its synthesis.
19. Pharmaceutical composition according to claim 16 comprising fluoroquinolones, particularly moxifloxacin, as gyrase inhibitor.
20. Pharmaceutical composition according to claim 16, characterised in that the infected cells are osteoblasts, leucocytes, erythrocytes, keratinocytes, fibroblasts, fat cells, muscle cells andor endothelial cells.
21. Pharmaceutical composition according claim 16, characterised in that the microbial infection caused by gram-negative andor gram-positive bacteria, preferably by the Staphyloccoci type, most preferably by Staphylococcus aureus.
22. Substrate for medical purposes, comprising a pharmaceutical composition according to anyone of the claim 11.
23. Substrate according to claim 22, characterised in that it is arranged and provided for being used as pharmaceutical composition carrier for local antibiotic therapy of an acute or chronic infection of a tissue of a subject.
24. Substrate according to anyone of claim 22, characterised in that it comprises a fleece, a fabric, a polymethyl methacrylate, a copolymer of methylmethacrylate and methylacrylate, a biodegradable polymer, polyethylene, a metal, a ceramic, a bone cement andor a bone substitute.
25. Substrate according to claim 24, characterised in that the fleece or the fabric comprises a natural or synthetic fibre, particularly polylactide, andor collagen.
26. Substrate according to any of claim 22, characterised in that it comprises an implantable prosthesis, in particular a hip prosthesis, a shoulder prosthesis, an elbow prosthesis, a knee prosthesis or a vertebral implant or an implant for trauma surgery.
27. Implant coated with a pharmaceutical composition according to any one of the claim 11.
28-32. (canceled)

1. A lift for a vehicle comprising:
a base having a first end and a second end;
a ramp having an end and a connection point being pivotally connected to said first end of said base; and
a lifting mechanism adapted for raising said vehicle while said vehicle being on said ramp having a first end pivotally connected to said second end of said base and a second end pivotally connected to said end of said ramp;
said lifting mechanism comprising:
a lower arm having two ends, said first end being pivotally connected to said second end of said base and said second end being pivotally connected to an upper arm;
said upper arm having two ends, said first end being pivotally connected to said lower arm, and said second end being pivotally connected to said ramp;
a leverage arm rigidly connected to said lower arm;
when said leverage arm being rotated, then said
lower arm rotates upward forcing said ramp to raise from said lowered position to said raised position;

said lift being in a lowered position, when said lifting mechanism being collapsed; and
said lift being in a raised position when said lifting mechanism being extended.
2. The lift of claim 1 where said lifting mechanism being collapsed when said lower arm being approximately horizontal.
3. The lift of claim 1 where said lifting mechanism being extended when said lower arm being approximately vertical.
4. The lift of claim 1 where the lifting mechanism further comprising a stopping mechanism;
said stopping mechanism being adapted to stop said leverage arm from rotating said lower arm past a predetermined position.
5. The lift of claim 4 where said predetermined position being when said ramp being in said raised position.
6. The lift of claim 4 where said stopping mechanism being mounted on said base.
7. The lift of claim 1 where said lifting mechanism further comprising a first safety pin being adapted to fix said lower arm to said upper arm in said raised position.
8. The lift of claim 1 where said lifting mechanism further comprising a second safety pin being adapted to fix said lower arm to said upper arm in said lowered position.
9. The lift of claim 1 where said vehicle lift further comprising a lowering mechanism mounted to the exterior of said lifting mechanism;
when said lowering mechanism being moved in one direction, said lowering mechanism being adapted to cause said lifting mechanism to collapse from said raised position to said lowered position.
10. The lift of claim 1 where said ramp comprising:
a first platform;
a second platform; and
a third platform;
said first and second platforms being fixed at a first angular relationship;
said first angular relationship being at said connection point;
said second and third platforms being fixed at a second angular relationship; and
said ramp being pivotally connected to said lifting mechanism at the terminal end of said third platform.
11. The lift of claim 10 where said first platform and said third platform being parallel.
12. The lift of claim 10 being adapted to rise from said lowered position to an intermediate position when an external force is applied to a top side of said first platform.
13. The lift of claim 12 where said intermediate position being where said third platform being in contact with the undercarriage of the vehicle.
14. A lift for a vehicle comprising;
a base having a first end and a second end;
a ramp having an end and a connection point being pivotally connected to said first end of said base; and
a lifting mechanism adapted for raising said vehicle while said vehicle being on said ramp having a first end pivotally connected to said second end of said base and a second end pivotally connected to said end of said ramp;
said ramp comprising:
a first platform;
a second platform; and
a third platform;

said first and second platforms being fixed at a first angular relationship;
said first angular relationship being at said connection point;
said second and third platforms being fixed at a second angular relationship; and
said ramp being pivotally connected to said lifting mechanism at the terminal end of said third platform;
said lift being in a lowered position, when said lifting mechanism being collapsed; and
said lift being in a raised position when said lifting mechanism being extended.
15. The lift of claim 14 where said first platform and said third platform being parallel.
16. The lift of claim 14 being adapted to rise from said lowered position to an intermediate position when an external force is applied to a top side of said first platform.
17. The lift of claim 16 where said intermediate position being where said third platform being in contact with the undercarriage of the vehicle.
18. The lift of claim 14 where said lifting mechanism comprising:
a lower arm having two ends, said first end being pivotally connected to said second end of said base and said second end being pivotally connected to an upper arm;
said upper arm having two ends, said first end being pivotally connected to said lower arm, and said second end being pivotally connected to said ramp;
a leverage arm rigidly connected to said lower arm;
when said leverage arm being rotated, then said lower arm rotates upward forcing said ramp to raise from said lowered position to said raised position.
19. The lift of claim 14 where the lifting mechanism further comprising a stopping mechanism;
said stopping mechanism being adapted to stop said leverage arm from rotating said lower arm past a predetermined position.
20. The lift of claim 14 where said vehicle lift further comprising a lowering mechanism mounted to the exterior of said lifting mechanism;
when said lowering mechanism being moved in one direction, said lowering mechanism being adapted to cause said lifting mechanism to collapse from said raised position to said lowered position.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for controlling a power in a network on chip (NoC), comprising:
a storage for storing a status information of one or more links interconnecting a plurality of processing elements (PEs), a link configuration information for establishing paths between the processing elements, and a voltage and a clock information of the one or more links according to a bandwidth; and
a control device for establishing paths between the processing elements to transmit a data by checking the link configuration information in the storage, and for controlling the voltage and the clock of the links by determining a voltage and a clock of the links of the established paths according to a bandwidth required for a data transmission of the processing elements.
2. The apparatus of claim 1, wherein the storage stores the status information of the links by arranging a table which comprises at least one of a field indicative of a status of the links, a field indicative of a voltage level used to transmit data, a field indicative of a frequency level (clock) used to transmit data, and a field indicative of a bandwidth for the data transmission.
3. The apparatus of claim 1, wherein the storage stores the link configuration information for establishing the paths between the processing elements by arranging a table which comprises at least one of a field indicative of an origin processing element which sends data, a field indicative of a destination processing element which receives data, and links on a path interconnecting an origin processing element and a destination processing element.
4. The apparatus of claim 1, wherein the storage stores the voltage and the clock information of the links according to a bandwidth by arranging a table which comprises at least one of a voltage level field of the link for supporting the bandwidth and a frequency level (clock) field of the link for supporting the bandwidth.
5. The apparatus of claim 1, wherein the storage further stores a job information on the network on chip by arranging a table which comprises at least one of a field indicative of an origin processing element which sends data, a field indicative of a destination processing element which receives data, a field indicative of a bandwidth information for transmitting data between an origin processing element and a destination processing element, and a field indicative of paths transmitting data from an origin processing element to a destination processing element.
6. The apparatus of claim 1, wherein the control device controls the voltage and the clock of the links on the path for the data transmission of the processing elements according to a bandwidth required for the processing elements to transmit data by checking a voltage and a clock information of the link based on the bandwidth in the storage, and
the control device updates the status information of the links in the storage using the voltage, the clock, and the bandwidth information of the links changed through the controlling.
7. The apparatus of claim 1, wherein the control device comprises:
a controller for establishing paths between the processing elements using the information stored in the storage, and determining a voltage and a clock to change of the links on the path according to the bandwidth required for the processing elements to transmit data;
a power controller for controlling a voltage of the links under the control of the controller; and
a clock controller for controlling a clock of the links under the control of the controller.
8. The apparatus of claim 1, wherein the link comprises:
one or more synchronization parts disposed in proximity to the processing elements for synchronizing between the processing elements;
a driving unit for controlling a voltage and a clock of the link under the control of the control device; and
a receiving unit for converting a voltage and a clock of data received from the driving unit to synchronize a voltage and a clock level with the driving unit.
9. A method for controlling a power in a network on chip (NoC), the method comprising:
when a processing element (PE) requests data transmission, confirming a path for the processing element to send data;
confirming a bandwidth to be processed by one or more links on the confirmed path according to a bandwidth for the data transmission of the processing element; and
sending one or more control signals to control a voltage and a clock of the links according to the bandwidth to be processed by the links.
10. The method of claim 9, wherein confirming a bandwidth to be processed by the links comprises:
confirming a bandwidth processed by the links of the path;
confirming a bandwidth required for the data transmission requested by the processing element; and
calculating a sum of the bandwidth processed by the links and the bandwidth required for the data transmission requested by the processing element.
11. The method of claim 9, further comprising:
after confirming the bandwidth to be processed by the links, checking whether the links on the path are able to process the confirmed bandwidth; and
when at least one of the links is not able to process the bandwidth, confirming another path for the processing element to send the data.
12. The method of claim 11, wherein when the links are able to process the confirmed bandwidth, one or more control signals are transmitted to control a voltage and a clock of the links on the path according to the confirmed bandwidth.
13. The method of claim 9, wherein the sending of the control signals comprises:
checking whether the links on the path comprises an active link;
when there is inactive link, confirming voltage and the clock of the links on the path for processing the confirmed bandwidth; and
sending the control signals to control the voltage and the clock of the links based on the confirmed voltage and clock.
14. The method of claim 13, further comprising:
after confirming the voltage and the clock of the links, updating a status of the links on the path to an active mode in a link status table which arranges status information of the links; and
updating the voltage, the clock, and the bandwidth information of the links with the confirmed voltage, clock and bandwidth in the link status table.
15. The method of claim 13, further comprising:
when there exists an active link, aborting a data transmission processed by the active link;
confirming a voltage and a clock of the links on the path for processing the confirmed bandwidth;
sending one or more control signals to control the voltage and the clock of the links according to the confirmed voltage and clock; and
resuming the aborted data transmission.
16. The method of claim 15, further comprising:
after confirming the voltage and the clock of the links, updating a status of the inactive links to an active mode in the link status table which arranges the status information of the links; and
updating the voltage, the clock, and the bandwidth information of the links with the confirmed voltage, clock and bandwidth in the link status information.
17. The method of claim 9, further comprising:
after sending the control signals, adding a data transmission job requested by the processing element into an operation table which arranges operation information of the processing elements on the network on chip.
18. The method of claim 9, further comprising:
after sending the control signals, controlling the processing element to commence the data transmission.
19. A method for controlling a power in a Network on Chip (NoC), the method comprising:
when data transmission of processing elements (PEs) is completed, confirming a changed bandwidth of at least one link constituting a network of the network on chip according to the completion of the data transmission; and
when there exists a link not transmitting data according to the changed bandwidth, sending one or more control signals of voltage and clock to deactivate the corresponding link.
20. The method of claim 19, further comprising:
after sending the control signals, updating a status of links not transmitting data to an inactive mode in a link status table which arranges status information of links.
21. The method of claim 19, further comprises:
after sending the control signals, deleting a job of the completed data transmission in an operation table which arranges operation information of processing elements on the network on chip.
22. The method of claim 19, further comprising:
when there exists a link having a reduced bandwidth according to the changed bandwidth, aborting a data transmission processed by the link having the reduced bandwidth;
confirming a voltage and a clock of the link having the reduced bandwidth according to the reduced bandwidth;
sending one or more control signals to control a voltage and a clock of the link based on the confirmed voltage and clock; and
resuming the aborted data transmission.
23. The method of claim 22, further comprising:
after confirming a voltage and a clock of the links, updating the voltage and the clock of the link with the confirmed voltage, clock and bandwidth in a link status table which arranges status information of links.
24. The method of claim 22, further comprising:
after sending the control signals, deleting a job of the completed data transmission in an operation table which arranges operation information of processing elements on the network on chip.