Author: claimsbot

1. An integrated circuit comprising:
a plurality of leads, a sequence of black area pixel values being present on the plurality of leads; and
smear detect circuitry that receives the sequence of black area pixel values and outputs a smear detect signal.
2. The integrated circuit of claim 1, wherein the integrated circuit is coupled to an image sensor, the image sensor includes a transfer line and a black area, and the smear detect signal indicatives that a charge has leaked along the transfer line and into the black area.
3. The integrated circuit of claim 1, wherein the integrated circuit is an analog front end (AFE) integrated circuit of a digital camera.
4. The integrated circuit of claim 1, further comprising:
a black level generator that receives the smear detect signal and outputs a black level value.
5. The integrated circuit of claim 4, wherein the black level generator is disabled when the smear detect signal is asserted.
6. The integrated circuit of claim 1, further comprising:
a second plurality of leads that communicates a threshold value to the smear detect circuitry.
7. The integrated circuit of claim 6, wherein the smear detect circuitry comprises:
a comparator that receives the sequence of black area pixel values and the threshold value and outputs a logic signal; and
a state machine that receives the logic signal and outputs the smear detect signal.
8. The integrated circuit of claim 1, wherein the smear detect circuitry detects when a predetermined threshold value is exceeded by more than a predetermined number of consecutive black area pixel values.
9. The integrated circuit of claim 1, wherein the smear detect signal is output from the integrated circuit.
10. The integrated circuit of claim 1, wherein the integrated circuit is an image sensor integrated circuit.
11. The integrated circuit of claim 1, wherein the integrated circuit is part of a digital camera that produces a digital image, wherein the digital image is stored in the digital camera as a digital file, and wherein information from the smear detect signal is included in the digital file.
12. An image sensor integrated circuit that outputs a smear detect signal.
13. The image sensor integrated circuit of claim 12, wherein the image sensor integrated circuit includes an optical black area, and wherein the smear detect signal indicates that smear leakage has leaked into the optical black area.
14. An integrated circuit comprising:
a plurality of leads, a sequence of black area pixel values being present on the plurality of leads; and
means for outputting a smear detect signal in response to detecting smear resulting from a charge leaking along a transfer line of an image sensor and into a black area of the image sensor.
15. A method comprising:
(a) detecting a leakage charge that leaks from a first storage element to a second storage element of an image sensor, wherein the first storage element and the second storage element are located along a transfer line; and
(b) identifying the transfer line as exhibiting the leakage charge.
16. The method of claim 15, wherein the image sensor is a charge coupled device in an analog front end (AFE) of a digital camera.
17. The method of claim 15, wherein the first storage element has been exposed to bright light, and wherein the second storage element is located in an optical black area of the image sensor.
18. The method of claim 15, further comprising:
(c) indicating that the leakage charge has leaked.
19. The method of claim 18, wherein the image sensor is a charge coupled device in a digital camera, wherein the digital camera has a display, and wherein the leakage charge is indicated in (c) by displaying an icon on the display of the digital camera.
20. The method of claim 18, wherein the image sensor is part of a digital camera that produces a digital image, wherein the digital image is stored in the digital camera as a file with a filename, and wherein the leakage charge is indicated in (c) by including a code in the filename of the digital image.
21. The method of claim 15, wherein each storage element stores an amount of charge, wherein pixel data includes the amount of charge stored on each storage element, further comprising:
(c) performing black level calibration of the pixel data, wherein pixel data from the transfer line is excluded from the black level calibration.
22. The method of claim 15, wherein the image sensor includes a second transfer line adjacent to the first-mentioned transfer line, wherein plural storage elements are located along the second transfer line, wherein pixel data includes the amount of charge stored on each of the plural storage elements located along the second transfer line, further comprising:
(c) performing black level calibration of the image sensor, wherein pixel data from the second transfer line is excluded from the black level calibration.
23. The method of claim 15, wherein plural adjacent storage elements are located along the transfer line, wherein each of the plural adjacent storage elements stores an amount of charge, and wherein the leakage charge is detected in (a) when the amount of charge stored on each of N consecutive adjacent storage elements exceeds a threshold amount, wherein N is an integer greater than one.
24. The method of claim 15, wherein the image sensor includes plural transfer lines, and wherein each of the plural transfer lines is located partially within an optical black area.
25. The method of claim 15, wherein the image sensor is part of a digital camera, wherein the digital camera contains a microcontroller, further comprising:
(c) sending an interrupt signal to the microcontroller upon detecting the leakage current in (a).
26. A device comprising:
a first storage element located along a transfer line;
a second storage element located along the transfer line, wherein the first storage element and the second storage element are part of an image sensor; and
smear detect circuitry that detects when a leakage charge leaks from the first storage element to the second storage element.
27. The device of claim 26, wherein the image sensor is a charge coupled device in an analog front end (AFE) of a digital camera.
28. The device of claim 26, wherein plural adjacent storage elements are located along the transfer line, wherein each of the plural adjacent storage elements stores an amount of charge, and wherein the smear detect circuitry detects the leakage charge when the amount of charge stored on each of N consecutive adjacent storage elements exceeds a threshold amount, wherein N is an integer greater than one.
29. The device of claim 26, further comprising:
a black level generator that calculates a black level value of the image sensor.
30. The device of claim 29, wherein the image sensor includes a plurality of storage elements, wherein each storage element stores an amount of charge, wherein the amount of charge stored on each storage element constitutes pixel data, and wherein the black level generator calculates the black level value of the image sensor by excluding pixel data from the transfer line.
31. The device of claim 26, wherein the image sensor includes a plurality of storage elements, wherein each storage element stores an amount of charge, wherein the amount of charge stored on each storage element constitutes pixel data, wherein the black level generator receives pixel data from the image sensor, and wherein the black level generator is disabled when the image sensor outputs pixel data from the transfer line.
32-49. (canceled)

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated circuit layout, said integrated circuit layout comprising:
a plurality of circuit module designs;
a first interconnect line layer, said first interconnect line layer having a preferred horizontal direction of interconnect lines;
a second interconnect line layer, said second interconnect line layer having a preferred vertical direction of interconnect lines; and
a third interconnect line layer, said third interconnect line layer having a first diagonal preferred direction of interconnect lines;
wherein a plurality of interconnect lines on said first second, and third interconnect line layers couple said plurality of circuit module designs, said plurality of interconnect lines generated by using gridless routing, said gridless routing resulting in at least one pair of parallel interconnect lines on one of said interconnect line layers being closer than a minimum required line-to-via spacing.
2. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
3. The integrated circuit layout as claimed in claim 2, wherein said first diagonal preferred direction is approximately forty-five degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative forty-five degrees relative to said preferred horizontal direction.
4. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a preferred horizontal direction of interconnect lines.
5. The integrated circuit layout as claimed in claim 4, said integrated circuit layout further comprising:
a fifth interconnect line layer, said fifth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
6. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction.
7. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately positive thirty degrees relative to said preferred horizontal direction.
8. The integrated circuit layout as claimed in claim 1, wherein said integrated circuit layout is formed by compacting a gridded integrated circuit layout.
9. The integrated circuit layout as claimed in claim 1, wherein said pair of parallel interconnect lines may be placed as close together as can be manufactured reliably.
10. The integrated circuit layout as claimed in claim 1, wherein vias couple interconnect lines on different interconnect line layers.
11. A method of laying out an integrated circuit, said method comprising:
placing a plurality of circuit module designs;
routing a first interconnect line layer, said first interconnect line layer having a preferred horizontal direction of interconnect lines;
routing a second interconnect line layer, said second interconnect line layer having a preferred vertical direction of interconnect lines; and
routing a third interconnect line layer, said third interconnect line layer having a first diagonal preferred direction of interconnect lines;
wherein a plurality of interconnect lines on said first, second, and third interconnect line layers couple said plurality of circuit module designs, said plurality of interconnect lines generated by using gridless routing, said gridless routing resulting in at least one pair of parallel interconnect lines on one of said interconnect line layers being closer than a minimum required line-to-via spacing.
12. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising;
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
13. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said first diagonal preferred direction is approximately forty-five degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative forty-five degrees relative to said preferred horizontal direction.
14. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a preferred horizontal direction of interconnect lines.
15. The method of laying out said integrated circuit layout as claimed in claim 14, said method further comprising:
routing a fifth interconnect line layer, said fifth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
16. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction.
17. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately positive thirty degrees relative to said preferred horizontal direction.
18. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said integrated circuit layout is formed by compacting a gridded integrated circuit layout.
19. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said pair of parallel interconnect lines may be placed as close together as can be manufactured reliably.
20. The method of laying out said integrated circuit layout as claimed in claim 11, wherein vias couple interconnect lines on different interconnect line layers.
21. An integrated circuit layout, said integrated circuit layout comprising:
a plurality of circuit modules;
a first interconnect line layer, said first interconnect line layer having a first preferred direction of interconnect lines;
a second interconnect line layer, said second interconnect line layer having a second preferred direction of interconnect lines, wherein said first and second preferred directions of interconnect lines are neither orthogonal nor parallel; and
a plurality of interconnect lines on said first and second interconnect line layers;
wherein said plurality of interconnect lines couple said circuit modules;
wherein said plurality of interconnect lines are not aligned with any grid other than a manufacturing grid.
22. The integrated circuit layout of claim 21, wherein said plurality of interconnect lines coupling said circuit modules comprise a route.
23. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is less than ninety degrees.
24. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is forty-five degrees.
25. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is one hundred thirty-five degrees.

1. A write control method for a magnetoresistive random access memory including at least one memory cell, the memory cell including a magnetoresistive effect element as a storage element, the magnetoresistive effect element including a recording layer having an axis of easy magnetization and an axis of hard magnetization and of which magnetization direction is variable, a reference layer of which magnetization direction is invariable, and an insulation layer provided between the recording layer and the reference layer, the write control method comprising:
writing a datum into one memory cell, the writing of the datum including, applying a pulsative first magnetic field of a magnitude H1 substantially parallel
to the axis of easy magnetization of the recording layer and a pulsative second magnetic field of a magnitude H4 substantially parallel to the axis of hard magnetization to the recording layer so as to cause a period of the pulsative first magnetic field and a period of the pulsative second magnetic field to overlap each other,
reducing the magnitude H1 of the pulsative first magnetic field to be a magnitude H2 which is zero or more and which is less than the magnitude H1,
increasing the magnitude H2 of the pulsative first magnetic field to a magnitude H3 which is more than the magnitude H2 but equal to or less than the magnitude H1,
reducing the magnitude H4 of the pulsative second magnetic field to be zero, and
increasing the magnitude of the pulsative second magnetic field from zero to a magnitude H5 which is equal to the magnitude H4 so as to cause a period of the pulsative second magnetic field of the magnitude H5 and a period of the pulsative first magnetic field of the magnitude H3 to overlap each other.
2. The write control method according to claim 1, wherein while the pulsative first magnetic field of the magnitude H3 is applied, the pulsative second magnetic field is continuously applied to the recording layer.
3. The write control method according to claim 1, further comprising:
reducing the magnitude H4 of the pulsative second magnetic field to be zero,
wherein while the pulsative first magnetic field of the magnitude H3 is applied to the recording layer, the magnitude of the pulsative second magnetic field keeps zero.
4. A write control method for a magnetoresistive random access memory including at least one memory cell, the memory cell including a magnetoresistive effect element as a storage element, the magnetoresistive effect element including a recording layer of which magnetization direction is variable, a reference layer of which magnetization direction is invariable, and an insulation layer provided between the recording layer and the reference layer, the write control method comprising:
injecting a spin-polarized pulse current into the recording layer a plurality of times for writing a datum into one memory cell, when conducting writing by injecting a spin-polarized pulse current into the recording layer, wherein the pulses of the current are of a same polarity.
5. A magnetoresistive random access memory comprising:
a first wiring;
a second wiring;
a memory cell including a magnetoresistive effect element as a storage element, the magnetoresistive effect element being provided so as to be associated with an intersection region of the first wiring and the second wiring, the magnetoresistive effect element including a recording layer having an axis of easy magnetization and an axis of hard magnetization and of which magnetization direction is variable, a reference layer of which magnetization direction is invariable, and an insulation layer provided between the recording layer and the reference layer;
a first current generation circuit which generates a first pulse current and causes the first pulse current to flow through the first wiring in order to generate a first magnetic field substantially parallel to a direction of the axis of easy magnetization of the recording layer to be applied to the recording layer; and
a second current generation circuit which generates a second pulse current and causes the second pulse current to flow through the second wiring in order to generate a second magnetic field substantially parallel to a direction of the axis of hard magnetization of the recording layer to be applied to the recording layer, wherein
in order to write a datum into one memory cell,
the first and second current generation circuits generate the first and second pulse currents so as to cause periods of the first magnetic field and the second magnetic field to overlap each other,
then the first current generation circuit reduces a magnitude of the first pulse current so as to reduce a magnitude H1 of the first magnetic field to be a magnitude H2 which is zero or more and which is less than the magnitude H1, and increases the magnitude of the first pulse current so as to increase the magnitude H2 of the first magnetic field to a magnitude H3 and
the second current generation circuit reduces a magnitude of the second pulse current so as to reduce a magnitude H4 of the second magnetic field to be zero, and increases the magnitude of the second pulse current so as to increase the magnitude of the second magnetic field from zero to a magnitude H5 which is equal to the magnitude H4.
6. The magnetoresistive random access memory according to claim 5, comprising:
an array having a plurality of the memory cells; and
a selection circuit which selects at least one memory cell from the plurality of memory cells, wherein
the first current generation circuit generates the first pulse current so as to cause the first magnetic field to be applied to the recording layer in the selected memory cell, and
the second current generation circuit generates the second pulse current so as to cause the second magnetic field to be applied to the recording layer in the selected memory cell.
7. The magnetoresistive random access memory according to claim 5, wherein the second current generation circuit generates the second pulse current in order to cause the second magnetic field to continue to be applied to the recording layer, when the first magnetic field of the magnitude H3 is applied to the recording layer.
8. The magnetoresistive random access memory according to claim 5, wherein the second current generation circuit causes the magnitude of the second pulse current to be zero, when the first magnetic field of the magnitude H3 is applied to the recording layer.
9. The magnetoresistive random access memory according to claim 5, wherein the magnitude H3 of the first magnetic field is equal to or less than the magnitude H1 of the first magnetic field.
10. A magnetoresistive random access memory, comprising:
a first wiring;
a second wiring;
a memory cell including a magnetoresistive effect element as a storage element, the magnetoresistive effect element including a recording layer of which magnetization direction is variable, a reference layer of which magnetization direction is invariable, and an insulation layer provided between the recording layer and the reference layer, one end of the magnetoresistive effect element being electrically connected to the first wiring, the other end of the magnetoresistive effect element being electrically connected to the second wiring;
a first current generation circuit which generates a first pulse current a plurality of times and causes a spin-polarized pulse current to flow through the magnetoresistive effect element via the first wiring a plurality of times, when writing a first datum into one memory cell, wherein the pulses of the first current are of a same polarity; and
a second current generation circuit which generates a second pulse current a plurality of times and causes a spin-polarized pulse current to flow through the magnetoresistive effect element via the second wiring a plurality of times, when writing a second datum different from the first datum into one memory cell, wherein the pulses of the second current are of the same polarity.
11. The magnetoresistive random access memory according to claim 10, comprising:
an array having a plurality of the memory cells; and
a selection circuit which selects at least one memory cell from the plurality of memory cells, wherein
the first current generation circuit generates the first pulse current for the selected memory cell a plurality of times for writing the first datum into the memory cell, when conducting writing into the selected memory cell, and
the second current generation circuit generates the second pulse current for the selected memory cell a plurality of times for writing the second datum into the memory cell, when conducting writing into the selected memory cell.
12. The magnetoresistive random access memory according to claim 10, wherein a selection transistor is provided between the magnetoresistive effect element and one of the first wiring and the second wiring.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for operating a medical imaging examination apparatus comprising a plurality of apparatus subsystems, comprising:
providing a control protocol to control computer that is assigned to a scan sequence in which said control computer will control the plurality of apparatus subsystems in coordination to conduct the scan sequence to acquire medical imaging data from an examination subject;
in said control computer, determining sequence control data for said control protocol that define different functional sub-sequences of said scan sequence to be performed respectively by said apparatus subsystems;
in said control computer, assigning respectively different effective volumes of the examination subject to the respective functional sub-sequences;
in said control computer, determining current ambient conditions of said medical imaging examination apparatus that affect said sequence control data and said effective volumes;
in said control computer, calculating and storing control signals for said scan sequence dependent on said determined sequence control data, the determined effective volumes, and the determined current ambient conditions, by executing an algorithm in said control computer that optimizes the functional sub-sequences locally in the examination subject at least with regard to a sub-region of the respective effective volumes; and
in said control computer, starting said scan sequence using the stored control signals and, during said scan sequence, providing said control computer with a designation of at least one change of a sub-region of a respective effective volume, and automatically adapting said control signals for a remainder of said scan sequence dependent on said change, to maintain the optimization of the functional sub-sequences locally at least with regard to the changed sub-region.
2. A method as claimed in claim 1 comprising calculating and storing said control signals dependent on, for each sub-region to be optimized, a predetermined tolerance range that designates an amount by which the respective sub-region can be displaced, and adapting said control signals only when said change is larger than said tolerance region.
3. A method as claimed in claim 1 comprising adapting said control signals using control signals, among said stored control signals, that were calculated for a sub-region to be optimized that corresponds as closely as possible to the changed sub-region.
4. A method as claimed in claim 1 comprising calculating and storing said control signals for each functional subsequence for multiple, different effective volumes that are varies in a predetermined variation, at least with respect to sub-regions thereof, thereby producing stored control signals for respective, different variations of said sub-regions to be optimized in the respective effect volumes.
5. A method as claimed in claim 1 comprising adapting said control signals by interpolating control signals among said stored control signals.
6. A method as claimed in claim 1 comprising determining said at least one change of a sub-region of a respective effective volume continuously during said scan sequence, dependent on at least one of location and position changes of the examination subject.
7. A method as claimed in claim 1 comprising determining said at least one change of a sub-region of a respective effective volume during said scan sequence using at least one of information relating to said scan sequence, movement information detected by an external movement sensor, and movement information detected within said scan sequence.
8. A method as claimed in claim 1 comprising calculating said control signals together with a plausibility check.
9. A medical imaging examination apparatus comprising:
a plurality of apparatus subsystems;
a control computer provided with a control protocol that is assigned to a scan sequence in which said control computer is configured to control the plurality of apparatus subsystems in coordination to conduct the scan sequence to acquire medical imaging data from an examination subject;
said control computer being configured to determine sequence control data for said control protocol that define different functional sub-sequences of said scan sequence to be performed respectively by said apparatus subsystems;
said control computer being configured to assign respectively different effective volumes of the examination subject to the respective functional sub-sequences;
said control computer being configured to determine current ambient conditions of said medical imaging examination apparatus that affect said sequence control data and said effective volumes;
said control computer being configured to calculate and store control signals for said scan sequence dependent on said determined sequence control data, the determined effective volumes, and the determined current ambient conditions, by executing an algorithm in said control computer that optimizes the functional sub-sequences locally in the examination subject at least with regard to a sub-region of the respective effective volumes; and
said control computer being configured to start said scan sequence using the stored control signals and, during said scan sequence, receive a designation of at least one change of a sub-region of respective effective volume, and automatically adapt said control signals for a remainder of said scan sequence dependent on said change, to maintain the optimization of the functional sub-sequences locally at least with regard to the changed sub-region.
10. A medical imaging examination apparatus as claimed in claim 9 wherein said plurality of apparatus subsystems form a magnetic resonance scanner.
11. A non-transitory, computer-readable data storage medium encoded with programming instructions, said storage medium being loaded into a control computer of a medical imaging examination apparatus comprising a plurality of apparatus subsystems, said programming instructions causing said control computer to:
receive a control protocol that is assigned to a scan sequence in which said control computer will control the plurality of apparatus subsystems in coordination to conduct the scan sequence to acquire medical imaging data from an examination subject;
determine sequence control data for said control protocol that define different functional sub-sequences of said scan sequence to be performed respectively by said apparatus subsystems;
assign respectively different effective volumes of the examination subject to the respective functional sub-sequences;
determine current ambient conditions of said medical imaging examination apparatus that affect said sequence control data and said effective volumes;
calculate and store control signals for said scan sequence dependent on said determined sequence control data, the determined effective volumes, and the determined ambient conditions, by executing an algorithm that optimizes the functional sub-sequences locally in the examination subject at least with regard to a sub-region of the respective effective volumes; and
start said scan sequence using the stored control signals and, during said scan sequence, receive a designation of at least one change of a sub-region of a respective effective volume, and automatically adapt said control signals for a remainder of said scan sequence, dependent on said change, to maintain the optimization of the functional sub-sequences locally at least with regard to the changed sub-region.