Author: claimsbot

1. An apparatus for managing operations in a processor, said apparatus comprising:
a plurality of addressable registers, each of said registers partitioned into plurality of data entry fields;
a first comparison circuit operable to scan a like data entry field of said plurality of addressable registers and compare data in said like data entry fields to predetermined input data;
a second comparison circuit operable to compare a first register address of a first register in said plurality of addressable registers to a second register address of a second register in said plurality of addressable registers, wherein said first register address corresponds to a first register that has said data in said like data entry field that matches said predetermined input data; and
a dispatch circuit operable to dispatch data of a second data entry field of said second register to an operation unit in response to a decode of data in a third data entry field of said second register when said second comparison circuit indicates said second register address matches said first register address.
2. The apparatus of claim 1, wherein said operations are Load and Store operations within said processor.
3. The apparatus of claim 2, wherein said operation unit comprises a Storage Management Unit (SMU) said SMU comprising data cache memory and controller and a Storage Reference Buffer (SRB).
4. The apparatus of claim 3 wherein said addressable registers are configured as said Storage Reference Buffer (SRB).
5. The apparatus of claim 4, wherein said data entry fields, added to said SRB after a mis-predicted branch instruction occurs in said processor, are retired and said first pointer is indexed to first register address of a register with added register data entry bits which were added immediately prior to said mis-predicted branch instruction.
6. The apparatus of claim 3, wherein the SRB comprises the plurality of addressable registers.
7. The apparatus of claim 6, wherein a Load operation in one of the Load and Store operations comprises:
issuing concurrently a fetch instruction requesting a real address to a data cache and the Storage Reference Buffer (SRB), the real address corresponding to an address of multiple bytes of data;
scanning the addressable registers in the SRB for the real address;
receiving the multiple bytes of data from the SRB if the real address is available;
retrieving the multiple bytes of data first from the SRB if the real address is available and second from the data cache if the real address is not available in the SRB; and
updating a corresponding one of the addressable registers with the multiple bytes of data.
8. The apparatus of claim 6, wherein a Store operation in one of the Load and Store operations comprises:
issuing a real address generation instruction;
looking up the real address in a table lookup buffer;
sending the real address to a miss resolution processor if the real address is not in the table lookup buffer, the miss resolution processor determining a translated real address;
sending the real address from one of the miss resolution processors and the table lookup buffer to the SRB; and
updating corresponding data entry fields in one of the addressable registers in the SRB.
9. The apparatus of claim 6, wherein a Store operation in one of the Load and Store operations comprises:
issuing an address generation instruction by a first instruction unit generating a real address in memory;
updating the real address in a real address field of one of the addressable registers in the SRB;
sending concurrently, a request for a multiple byte word with the real address to the SRB and a data cache;
receiving the multiple byte word from one of the addressable registers in the Storage Reference Buffer and from a data cache;
updating the multiple byte word from the data cache with an operand mask;
receiving from the first instruction unit store data operand;
aligning the store data operand to the multiple bytes of data; and
updating the multiple bytes of data with a complement of the operand mask.
10. The apparatus of claim 6, wherein a Load operation in one of the Load and Store operations comprises:
issuing an address generation instruction by a first instruction unit generating a real address in a memory;
updating the real address in a real address field of one of the addressable registers in the SRB;
sending concurrently, a request for a multiple byte word with the real address to the SRB and a data cache;
receiving the multiple byte word from one of the addressable registers in the SRB and the data cache;
extracting selected bytes from the multiple byte word;
receiving the selected bytes by the first instruction unit; and
updating the multiple bytes of data with a complement of the operand mask.
11. The apparatus of claim 1, wherein said predetermined input data is a real address requesting particular data corresponding to one of a Load and a Store operation.
12. The apparatus of claim 1, wherein said first comparison circuit comprises multiple like entry comparison circuits, each of said multiple like entry comparison circuits operable concurrently in parallel.
13. The apparatus of claim 1, wherein said operation unit comprises an Instruction Management Unit (IMU).
14. The apparatus of claim 1, wherein one of said data entry fields is a Valid bit field, said Valid bit field indicating whether other data entry fields are valid.
15. The apparatus of claim 1, wherein one of said data entry fields is an Instruction Identification (ID) field corresponding to a particular Load and Store operation.
16. The apparatus of claim 1, wherein one of said data entry fields is an Instruction status field corresponding to a status of one of said Load and Store operations.
17. The apparatus of claim 1, wherein one of said data entry fields is a LoadStore field having a LoadStore bit, said LoadStore bit corresponding to a Load operation if said LoadStore bit has a first logic state and corresponding to a Store operation if said LoadStore bit has a second logic state.
18. The apparatus of claim of claim 1, wherein one of said data entry fields comprises Real Address field, said Real Address field corresponding to a particular Real Address of memory data.
19. The apparatus of claim 1, wherein one of said data entry fields is a Quadword field, said Quadword field comprising multiple bytes of data.
20. The apparatus of claim 1, wherein one of said data entry fields is an Operand Mask field, said Operand Mask field defining selected bytes of data within a selected one of said data entry fields.
21. The apparatus of claim 1, wherein said operation unit is a pipeline execution unit operating concurrently on a plurality of said data entry fields.
22. The apparatus of claim 1, wherein said addressable registers are addressed using a plurality of address pointers.
23. The apparatus of claim 22, wherein one of said address pointers is a third pointer, said third pointer, said third pointer pointing to one of said addressable registers whose data entry fields contain data defining an earliest Store operation that is either unresolved or that matches a register address of a current Load operation.
24. The apparatus of claim 22, wherein said address pointers comprise a fourth and a fifth pointer, said fourth and fifth pointers defining a window of register addresses from which a Load operation may be satisfied without having to access other memory storage.
25. The apparatus of claim 22, wherein said second register address is selected from registers addresses which fall within a window of register addresses, said window of addresses defined by said address pointers.
26. The apparatus of claim 25, wherein said window of register addresses defines active Load and Store operations.
27. The apparatus of claim 22, wherein one of said address pointers is a first pointer, said first pointer pointing to an IN register address of a first available register into which data may be added.
28. The apparatus of claim 27, wherein said first pointer is indexed by one when said register data has been added, said first pointer having a minimum and a maximum value wherein a decrement down from a minimum value results in said maximum value and an increment up from said maximum value results in said minimum value.
29. The apparatus of claim 22, wherein one of said address pointers is a second pointer, said second pointer pointing to an OUT register address of a first available register from which register data may be retired.
30. The apparatus of claim 29, wherein said second pointer is indexed by one when register entry bits have been deleted, said second pointer having a minimum and a maximum value wherein a decrement down from said minimum value results in said maximum value and an increment up from said maximum value results in said minimum value.
31. A data processing system, comprising:
a central processing unit (CPU);
random access memory (RAM);
read only memory (ROM);
an IO adapter; and
a bus system coupling devices internal to said CPU, said CPU comprising an apparatus for managing operations within a processor of said CPU, said apparatus comprising:
a first comparison circuit operable to scan a like data entry field of said plurality of addressable registers and compare data in said like data entry fields to predetermined input data;
a second comparison circuit operable to compare a first register address of a first register in said plurality of addressable registers; to a second register address of a second register in said plurality of addressable registers, wherein said first register address corresponds to a first register that has said data in said like data entry field that matches said predetermined input data; and
a dispatch circuit operable to dispatch data of a second data entry field of said second register to an operation unit in response to a decode of data in a third data entry field of said second register when said second comparison circuit indicates said second register address matches said first register address.
32. The data processing system of claim 31, wherein said operations are Load and Store operations within said processor.
33. The data processing system of claim 32, wherein said operation unit comprises a Storage Management Unit (SMU) said SMU comprising data cache memory and controller and a Storage Reference Buffer (SRB).
34. The data processing system of claim 33 wherein said addressable registers are configured as said Storage Reference Buffer (SRB).
35. The data processing system of claim 34, wherein said data entry fields, added to said SRB after a mis-predicted branch instruction occurs in said processor, are retired and said first painter is indexed to first register address of a register with added register data entry bits which were added immediately prior to said mis-predicted branch instruction.
36. The data processing system of claim 31, wherein said predetermined input data is a real address requesting particular data corresponding to one of a Load and a Store operation.
37. The data processing system of claim 31, wherein said first comparison circuit comprises multiple like entry comparison circuits, each of said multiple like entry comparison circuits operable concurrently in parallel.
38. The data processing system of claim 31, wherein said operation unit comprises an Instruction Management Unit (IMU).
39. The data processing system of claim 31, wherein one of said data entry fields is a Valid bit field, said Valid bit field indicating whether other data entry fields are valid.
40. The data processing system of claim 31, wherein one of said data entry fields is an Instruction Identification (ID) field corresponding to a particular Load and Store operation.
41. The data processing system of claim 31, wherein one of said data entry fields is an Instruction status field corresponding to a status of one of said Load and Store operations.
42. The data processing system of claim 31, wherein one of said data entry fields is a LoadStore field having a LoadStore bit, said LoadStore bit corresponding to a Load operation if said LoadStore bit has a first logic state and corresponding to a Store operation if said LoadStore bit has a second logic state.
43. The data processing system of claim of claim 31, wherein one of said data entry fields comprises Real Address field, said Real Address field corresponding to a particular Real Address of memory data.
44. The data processing system of claim 31, wherein one of said data entry fields is a Quadword field, said Quadword field comprising multiple bytes of data.
45. The data processing system of claim 31, wherein one of said data entry fields is an Operand Mask field, said Operand Mask field defining selected bytes of data within a selected one of said data entry fields.
46. The data processing system of claim 31, wherein said operation unit is a pipeline execution unit operating concurrently on a plurality of said data entry fields.
47. The data processing system of claim 31, wherein said addressable registers are addressed using a plurality of address pointers.
48. The data processing system of claim 47, wherein one of said address pointers is a third pointer, said third pointer, said third pointer pointing to one of said addressable registers whose data entry fields contain data defining an earliest Store operation that is either unresolved or that matches a register address of a current Load operation.
49. The data processing system of claim 47, wherein said address painters comprise a fourth and a fifth pointer, said fourth and fifth pointers defining a window of register addresses from which a Load operation may be satisfied without having to access other memory storage.
50. The data processing system of claim 47, wherein said second register address is selected from registers addresses which fall within a window of register addresses, said window of addresses defined by said address pointers.
51. The data processing system of claim 37, wherein said window of register addresses defines active Load and Store operations.
52. The data processing system of claim 47, wherein one of said address pointers is a first pointer, said first pointer pointing to an IN register address of a first available register into which data may be added.
53. The data processing system of claim 52, wherein said first pointer is indexed by one when said register data has been added, said first pointer having a minimum and a maximum value wherein a decrement down from a minimum value results in said maximum value and an increment up from said maximum value results in said minimum valve.
54. The data processing system of claim 47, wherein one of said address pointers is a second pointer, said second painter pointing to an OUT register address of a first available register from which register data may be retired.
55. The data processing system of claim 54, wherein said second pointer is indexed by one when register entry bits have been deleted, said second pointer having a minimum and a maximum value wherein a decrement down from said minimum value results in said maximum value and an increment up from said maximum value results in said minimum value.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A network switch for network communications, said network switch comprising:
a first data port interface, said first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate;
a second data port interface, said second data port interface supporting a plurality of data ports transmitting and receiving data at a second data rate;
a CPU interface, said CPU interface configured to communicate with a CPU;
an internal memory, said internal memory communicating with said first data port interface and said at least one second data port interface;
a memory management unit, said memory management unit including an external memory interface for communicating data from at least one of said first data port interface and said second data port interface and an external memory; and
a communication channel, said communication channel for communicating data and messaging information between said first data port interface, said second data port interface, said internal memory, and said memory management unit,
wherein said memory management unit directs data from one of said first data port and said second data port to one of said internal memory and said external memory interface according to a predetermined algorithm.
2. A network switch as recited in claim 1, wherein said memory management unit directs data to said internal memory and said external memory interface according to the predetermined algorithm wherein the internal memory and external memory interface results in a distributed hierarchical shared memory configuration, with a hierarchy between the internal memory and the external memory interface, and hierarchies within the internal memory.
3. A network switch as recited in claim 2, wherein said memory management unit dynamically allocates internal memory space to selected ports of said plurality of data ports in the first data port interface and in the second data port interface based upon traffic flow through the network switch.
4. A network switch as recited in claim 1, wherein said first data port interface includes a packet slicing unit for slicing variable length packets into a plurality of equal length cells, said packet slicing unit including a padding unit for including padding bits into a last cell of the plurality of equal length cells if the last cell does not include a sufficient number of bits to match a length of the equal length cells.
5. A network switch as recited in claim 1, wherein said communication channel comprises three communication channels.
6. A network switch as recited in claim 5, wherein said three communication channels include a first channel for communicating cell data between the plurality of data ports in the first data port interface, the plurality of data ports in the second data port interface, the internal memory, and the external memory interface, and a second channel, synchronously locked with the first channel, for communicating message information corresponding to the cell data on the first channel, and a third channel, independent from said first and second channel, for communicating sideband message information.
7. A network switch as recited in claim 1, wherein said first data port interface is an ethernet data port interface.
8. A network switch as recited in claim 1, wherein said second data port interface is a gigabit ethernet data port interface.
9. A network switch as recited in claim 1, wherein said first data port interface, said second data port interface, said CPU interface, said internal memory, said memory management unit, and said communication channel are integrated on a single application specific integrated circuit (ASIC) chip.
10. A network switch as recited in claim 1, wherein said internal memory is static random access memory (SRAM).
11. The network switch as recited in claim wherein said external memory interface is configured to interface to external dynamic random access memory (DRAM).
12. A network switch as recited in claim 1, wherein said first data port interface, said second data port interface, said CPU interface, said internal memory, said memory management unit, and said communication channel are configured to perform layer two switching at wirespeed.
13. A network switch as recited in claim 1, wherein said at least one first data port interface, said at least one second data port interface, said CPU interface, said internal memory, said memory management unit, and said communication channel are configured to perform layer three switching at wirespeed.
14. A network switch as recited in claim 1, wherein said CPU interface is configured to provide communication between a remote CPU and the communication channel, wherein said remote CPU can program operations of the memory management unit while one of the first and second data port interfaces are receiving or transmitting data.
15. A network switch as recited in claim 14, wherein said CPU interface is configured to provide communication between the remote CPU and a sideband channel of the communication channel.
16. A network switch as recited in claim 1, said network switch including a plurality of semiconductor-implemented lookup tables therein, said plurality of lookup tables including address resolution lookuplayer three lookup, rules tables, and VLAN tables.
17. A network switch as recited in claim 16, wherein said first data port interface communicates table information with said second data port interface, such that incoming address information can be updated at a plurality of data port interfaces while the information is received at one data port interface.
18. A network switch as recited in claim 1, wherein said first data port interface includes an auto-negotiating unit for negotiating a maximum communication speed between a source data port and a destination data port.
19. A network switch as recited in claim 1, wherein said first data rate is a maximum of 100 Mbps.
20. A network switch as recited in claim 19, wherein said first data rate is a maximum of 10 Mbps.
21. A network switch as recited in claim 1, wherein said second data rate is a maximum of 1000 Mbps.
22. A network switch as recited in claim 16, wherein said first data port interface and said second data port interface share a common address lookuplayer three table, and a common VLAN table, and wherein each of the first data port interface and the second data port interface has a unique rules table associated therewith.
23. A network switch as recited in claim 1, further comprising a priority assignment unit for assigning a weighted priority value to untagged packets entering one of the first data port interface and the second data port interface.
24. A network switch as recited in claim 23, wherein said weighted priority is one of eight weighted priorities which are defined by a priority queue, said priority queue being provided in one of the first and second data port interfaces.
25. A network switch as recited in claim 23, wherein the priority assignment unit assigns priority based upon one of a source priority field or a destination priority field, said source priority field and said destination priority field being determined by a lookup table, said lookup table being dynamically configured based upon traffic flow.
26. A network switch as recited in claim 25, wherein said priority assignment unit assigns priority based upon the setting and unsetting of a priority bit in the lookup table entry for the packet.
27. A network switch as recited in claim 4, wherein said memory management unit includes an internal memory counting unit and an external memory counting unit, said internal memory counting unit keeping a running count of the number of cells in the internal memory, and the external memory counting unit keeping track of the number of cells sent to the external memory through the external memory interface.
28. A network switch as recited in claim 1, said system further comprising a priority assignment unit for assigning a weighted priority value to untagged packets entering one of the first data port interface and the second data port interface.
29. A network switch as recited in claim 28, wherein said weighted priority is one of eight weighted priorities which are defined by a priority queue, said priority queue being provided in one of the first and second data port interfaces.
30. A method of switching data in a communications network, said method comprising:
a) receiving an incoming data packet on a first data port;
b) slicing said data packet into a plurality of equal length data cells;
c) estimating a packet length as an estimated cell count based upon an incoming cell count and egress information;
d) determining whether a cell count in an external memory is equal to zero;
e) if said cell count in the external memory is equal to zero, said method further comprising determining whether the estimated cell count is greater than an admission low watermark for an internal memory;
f) admitting the plurality of equal length cells representing the packet into the internal memory if the estimated cell count is below the admission low watermark, and if the estimated cell count is above the admission high watermark, the cell is sent to the external memory, and if the estimated cell count is above the admission low watermark but below the admission high watermark, performing a determination to determine whether to admit the plurality of equal length cells into internal or external memory, such that if sufficient internal memory is available, the plurality of equal length cells is admitted into the internal memory, and if sufficient memory is not available, routing the plurality of equal length cells representing the packet to the external memory;
g) if it is determined in d) that the cell count external memory is not equal to zero, then the method comprises determining whether the estimated cell count is below an admission high watermark for said internal memory, and if the estimated cell count is above the admission high watermark for said internal memory, then determining whether the estimated cell count is below an external memory admission low watermark, and if so, then determining whether or not a cell count of the cells in the external memory is less than or equal to a reroute limit value;
h) if the external memory cell count is less than or equal to the reroute limit value, then the estimated cell count is added to the external memory cell count, and it is then determined whether a sum of these counts is less than an estimated cell count low watermark, and if so, the plurality of equal length cells representing the packet is admitted to the internal memory, and if not, the plurality of equal length cells representing the packet is admitted to the external memory;
i) if it is determined that the estimated cell count is less than the admission high watermark, the plurality of equal length cells representing the packet is admitted to the external memory;
j) if it is determined that the estimated cell count is less than the external memory admission low watermark, the plurality of equal length cells representing the packet is admitted to the external memory; and
k) if the cell count of the external memory is determined to be greater than the reroute limit value, admitting the plurality of equal length cells representing the packet into the external memory.
31. A method as recited in claim 30, said method further comprising applying a weighted priority value to untagged packets entering one of the first data port interface and the second data port interface.
32. A method as recited in claim 31, wherein said weighted priority is one of eight weighted priorities which are defined by a priority queue, said priority queue being provided in one of the first and second data port interfaces.

1. A gaming system comprising:
at least one display device adapted to display a game;
at least one input device;
at least one processor; and
at least one memory device which stores a plurality of instructions, which when executed by the at least one processor, cause the at least one processor to operate with the at least one display device and the at least one input device to control a play of the game by:
(a) displaying a quantity of modifiers, wherein said quantity of displayed modifiers is at least two and said quantity of displayed modifiers is independent of any wagers placed by a player;
(b) for each displayed modifier, enabling the player to apply said modifier to a first game component, a second, different game component or a combination of the first game component and the second game component;
(c) if the player applied said modifiers to the first game component:
(i) modifying said first game component by each applied modifier, and
(ii) generating and displaying a first game outcome, wherein said generated game outcome is based on said modified first game component and said second game component;

(d) if the player applied said modifiers to the second game component:
(i) modifying said second game component by each applied modifier, and
(ii) generating and displaying a second game outcome, wherein said generated game outcome is based on said first game component and said modified second game component;

(e) if the player applied said modifiers to the combination of the first game component and the second game component:
(i) modifying said first game component by each modifier applied to said first game component,
(ii) modifying said second game component by each modifier applied to said second game component, and
(iii) generating and displaying a third game outcome, wherein said generated game outcome is based on said modified first game component and said modified second game component; and

(f) determining and displaying any award based on any generated game outcome.
2. The gaming system of claim 1, wherein the quantity of modifiers in the game is based on a game triggering event.
3. The gaming system of claim 1, wherein said first and second game components are selected from the group consisting of: a quantity of free spins, an multiplier for at least one free spin, a starting credit amount, a quantity of picks, a quantity of selections, a quantity of wild symbols, a quantity of retrigger symbols, a quantity of termination symbols, a quantity of anti-terminators, a quantity of locking reels, a quantity of locking symbol positions, a quantity of expanding symbols, a quantity of rounds, a quantity of award opportunities, a quantity of progressive awards, a range of awards, a maximum award, a minimum award, an average expected award, a quantity of active reels, a quantity of active paylines, a quantity of offers, a paytable, and a quantity of hands of playing cards.
4. The gaming system of claim 1, wherein a plurality of said modifiers are different.
5. The gaming system of claim 1, wherein when executed by the at least one processor, said plurality of instructions cause the at least one processor to control the play of the game by enabling the player to apply a plurality, but not all, of the modifiers the first game component.
6. The gaming system of claim 1, wherein the at least one processor resides remote from a housing which supports said at least one display device and said at least one input device.
7. A method of operating a gaming system, said method comprising:
(a) causing at least one display device to display a quantity of modifiers, wherein said quantity of displayed modifiers is at least two and said quantity of displayed modifiers is independent of any wagers placed by a player;
(b) for each displayed modifier, enabling the player to apply said modifier to a first game component, a second, different game component or a combination of the first game component and the second game component;
(c) if the player applied said modifiers to the first game component:
(i) causing at least one processor to execute a plurality of instructions to modify said first game component by each applied modifier,
(ii) causing the at least one processor to execute the plurality of instructions to generate a first game outcome, wherein said generated game outcome is based on said modified first game component and said second game component, and
(iii) causing the at least one display device to display the first game outcome;

(d) if the player applied said modifiers to the second game component:
(i) causing the at least one processor to execute the plurality of instructions to modify said second game component by each applied modifier,
(ii) causing the at least one processor to execute the plurality of instructions to generate a second game outcome, wherein said generated game outcome is based on said first game component and said modified second game component, and
(iii) causing the at least one display device to display the second game outcome;

(e) if the player applied said modifiers to the combination of the first game component and the second game component:
(i) causing the at least one processor to execute the plurality of instructions to modify said first game component by each modifier applied to said first game component,
(ii) causing the at least one processor to execute the plurality of instructions to modify said second game component by each modifier applied to said second game component,
(iii) causing the at least one processor to execute the plurality of instructions to generate a third game outcome, wherein said generated game outcome is based on said modified first game component and said modified second game component, and
(iv) causing the at least one display device to display the third game outcome;

(f) causing the at least one processor to execute the plurality of instructions to determine any award based on any generated game outcome; and
(g) causing the at least one display device to display the determined award.
8. The method of claim 7, wherein the quantity of modifiers in a game is based on a game triggering event.
9. The method of claim 7, wherein said first and second game components are selected from the group consisting of: a quantity of free spins, an multiplier for at least one free spin, a starting credit amount, a quantity of picks, a quantity of selections, a quantity of wild symbols, a quantity of retrigger symbols, a quantity of termination symbols, a quantity of anti-terminators, a quantity of locking reels, a quantity of locking symbol positions, a quantity of expanding symbols, a quantity of rounds, a quantity of award opportunities, a quantity of progressive awards, a range of awards, a maximum award, a minimum award, an average expected award, a quantity of active reels, a quantity of active paylines, a quantity of offers, a paytable, and a quantity of hands of playing cards.
10. The method of claim 7, wherein a plurality of said modifiers are different.
11. The method of claim 7, which includes enabling the player to apply a plurality, but not all, of the modifiers the first game component.
12. The method of claim 7, which is provided through a data network.
13. The method of claim 12, wherein the data network is an Internet.
14. A gaming system server comprising:
at least one processor; and
at least one memory device which stores a plurality of instructions, which when executed by the at least one processor, cause the at least one processor to:
(a) cause at least one display device to display a quantity of modifiers, wherein said quantity of displayed modifiers is at least two and said quantity of displayed modifiers is independent of any wagers placed by a player;
(b) for each displayed modifier, enable the player to apply said modifier to a first game component, a second, different game component or a combination of the first game component and the second game component;
(c) if the player applied said modifiers to the first game component:
(i) modify said first game component by each applied modifier,
(ii) generate a first game outcome, wherein said generated game outcome is based on said modified first game component and said second game component, and
(iii) cause the at least one display device to display the first game outcome;

(d) if the player applied said modifiers to the second game component:
(i) modify said second game component by each applied modifier,
(ii) generate a second game outcome, wherein said generated game outcome is based on said first game component and said modified second game component, and
(iii) cause the at least one display device to display the second game outcome;

(e) if the player applied said modifiers to the combination of the first game component and the second game component:
(i) modify said first game component by each modifier applied to said first game component,
(ii) modify said second game component by each modifier applied to said second game component, and
(iii) generate a third game outcome, wherein said generated game outcome is based on said modified first game component and said modified second game component, and
(iv) cause the at least one display device to display the third game outcome;

(f) determine any award based on any generated game outcome; and
(g) cause the at least one display device to display the determined award.
15. The gaming system server of claim 14, wherein the quantity of modifiers in a game is based on a game triggering event.
16. The gaming system server of claim 14, wherein said first and second game components are selected from the group consisting of: a quantity of free spins, an multiplier for at least one free spin, a starting credit amount, a quantity of picks, a quantity of selections, a quantity of wild symbols, a quantity of retrigger symbols, a quantity of termination symbols, a quantity of anti-terminators, a quantity of locking reels, a quantity of locking symbol positions, a quantity of expanding symbols, a quantity of rounds, a quantity of award opportunities, a quantity of progressive awards, a range of awards, a maximum award, a minimum award, an average expected award, a quantity of active reels, a quantity of active paylines, a quantity of offers, a paytable, and a quantity of hands of playing cards.
17. The gaming system server of claim 14, wherein a plurality of said modifiers are different.
18. The gaming system server of claim 14, wherein when executed by the at least one processor, said plurality of instructions cause the at least one processor to enable the player to apply a plurality, but not all, of the modifiers the first game component.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
receiving, by a network device of a content provider, a request for a first secret key and a second secret key,
the first secret key being used to encrypt the second secret key,
the second secret key being used to encrypt content being sent to a wireless user device, and
the content including one of an audio stream or a video stream;

generating, by the first network device and based on the request, the first secret key and the second secret key;
sending, by the network device and by using a multimedia Internet KEYing (MIKEY) protocol, the first secret key and the second secret key to a first broadcastmulticast service (BM-SC) device that provides service in a first coverage area of a network,
the first BM-SC device sending a first portion of the content, encrypted with the second secret key, to the wireless user device when the wireless user device is located in the first coverage area of the network;

sending, by the first network device and by using the MIKEY protocol, the first secret key and the second secret key to a second BM-SC device that provides service in a second coverage area of the network,
the second BM-SC device sending a second portion of the content, encrypted with the second secret key, to the wireless user device when the wireless user device is located in the second coverage area of the network, and
the first coverage area of the network being different than the second coverage area of the network; and

sending, by the first network device and by using the MIKEY protocol, the first secret key and the second secret key to the wireless user device,
the wireless user device using the second secret key to decrypt the first portion of the content received from the first BM-SC device and the second portion of the content received from the second BM-SC device, and
a user of the wireless user device being provided with the first portion of the content and the second portion of the content without interruption detectable by the user during a time when the wireless user device moves from the first coverage area of the network to the second coverage area of the network.
2. The method of claim 1, where sending the first secret key to the first BM-SC device and the second BM-SC device allows the wireless user device to continue receiving the content when the wireless user device moves from the first coverage area to the second coverage area.
3. The method of claim 1, where generating the first secret key includes:
generating the first secret key based on a bearer functional layer, a delivery method functional layer, and a user serviceapplication functional layer.
4. The method of claim 3, where generating the first secret key based on the bearer functional layer, the delivery method functional layer, and the user serviceapplication functional layer includes:
using variables, associated with the bearer functional layer, the delivery method functional layer, and the user serviceapplication functional layer, to generate the first secret key.
5. The method of claim 1, where sending the first secret key and the second secret key to the wireless user device includes:
sending the first secret key and the second secret key to a universal integrated circuit card located in the wireless user device.
6. The method of claim 1,
where the first secret key and the second secret key are associated with an identifier,
where the identifier associates the first secret key and the second secret key with a type of content, and
where the method further comprises:
storing the identifier associated with the first secret key and the second secret key.
7. The method of claim 1, where the first secret key permits the wireless user device to decrypt the second secret key.
8. A system comprising:
a device to:
receive a request for a secret key,
the secret key being used to encrypt a delivery of content being sent to a wireless user device;

generate the secret key based on receiving the request;
send, by using a multimedia Internet KEYing (MIKEY) protocol, the secret key to a first broadcastmulticast service (BM-SC) device associated with a first coverage area of a network,
the first BM-SC device sending a first portion of the content, encrypted with the secret key, to the wireless user device when the wireless user device is located in the first coverage area of the network;

send, by using the MIKEY protocol, the secret key to a second BM-SC device associated with a second coverage area of the network,
the second BM-SC device sending a second portion of the content, encrypted with the secret key, to the wireless user device when the wireless user device is located in the second coverage area of the network; and

send, by using the MIKEY protocol, the secret key to the wireless user device,
the wireless user device using the secret key to decrypt the first portion of the content received from the first BM-SC device and the second portion of the content received from the second BM-SC device, and
a user of the wireless user device being provided with the first portion of the content and the second portion of the content without interruption detectable by the user during a time when the wireless user device moves from the first coverage area of the network to the second coverage area of the network.
9. (canceled)
10. The system of claim 8, where the secret key is generated based on variables associated with a bearer layer, a delivery method layer, or a user serviceapplication layer.
11. The system of claim 8,
where the device:
generates a second secret key based on receiving the request; and
encrypts messages that include the secret key by using the second secret key, and

where sending the secret key to the first BM-SC device, the second BM-SC device, and the wireless user device includes sending the encrypted messages.
12. The system of claim 8,
where the device sends the secret key to a particular device, and
where the particular device sends a third portion of the content, encrypted with the secret key, to the wireless user device when the first BM-SC device and the second BM-SC device are not sending content to the wireless user device.
13. The system of claim 8,
where the secret key is associated with an identifier,
where the identifier associates the secret key with a type of content sent from the first BM-SC device to the wireless user device, and
where the device stores the identifier.
14. The system of claim 8, where the secret key is generated based on a bearer functional layer, a delivery method functional layer, or a user serviceapplication functional layer.
15. A non-transitory computer-readable medium storing instructions, the instructions comprising:
a plurality of instructions, that when executed by one or more processors of one or more network devices, cause the one or more processors to:
receive a request for a secret key,
the secret key being used to encrypt content sent to a wireless user device;

generate the secret key based on receiving the request;
send the secret key to a first broadcastmulticast service (BM-SC) device associated with a first coverage area of a network,
the first BM-SC device sending a first portion of the content, encrypted with the secret key, to the wireless user device when the wireless user device is located in the first coverage area of the network;

send the secret key to a second BM-SC device associated with a second coverage area of the network,
the second BM-SC device sending a second portion of the content, encrypted with the secret key, to the wireless user device when the wireless user device is located in the second coverage area of the network; and

send the secret key to the wireless user device,
the wireless user device using the secret key to decrypt the first portion of the content received from the first BM-SC device and using the secret key to decrypt the second portion of the content received from the second BM-SC device, and
a user of the wireless user device being provided with the first portion of the content and the second portion of the content without interruption detectable by the user during a time when the wireless user device moves from the first coverage area of the network to the second coverage area of the network.
16. The non-transitory computer-readable medium of claim 15, further comprising:
one or more instructions that, when executed by the one or more processors, cause the one or more processors to:
send the secret key to a third BM-SC device associated with a third coverage area of the network,
the third BM-SC device sending content, encrypted with the secret key, to the wireless user device when the wireless user device is located in the third coverage area of the network, and
the third coverage area of the network being different than the first coverage area of the network and the second coverage area of the network.
17. The non-transitory computer-readable medium of claim 15, where one or more instructions, of the plurality of instructions, to generate the secret key include one or more instructions to:
generate the secret key using variables associated with a type of content, a type of delivery associated with the content, or a type of bearer associated with the content.
18. The non-transitory computer-readable medium of claim 15, where one or more instructions, of the plurality of instructions, to generate the secret key include one or more instructions to:
generate the secret key as a multimedia broadcast multi-cast transport key.
19. The non-transitory computer-readable medium of claim 15, where one or more instructions, of the plurality of instructions, to generate the secret key include one or more instructions to:
generate the secret key using a boot-strapping transaction identifier associated with the wireless user device.
20. The non-transitory computer-readable medium of claim 15, further comprising:
one or more instructions that, when executed by the one or more processors, cause the one or more processors to:
terminate the secret key after a finite amount of time; and
prevent the wireless user device from using the secret key to decrypt the content after the finite amount of time.
21. The method of claim 1, where the method further comprises:
terminating the secret key after a finite amount of time; and
preventing the wireless user device from using the secret key to decrypt the content after the finite amount of time.