Author: claimsbot

1. A component comprising:
a longitudinal axle, having a plurality of keybars extending outward from a surface of the longitudinal axle, wherein each of the plurality of keybars are disposed axially along and circumferentially around the longitudinal axle, further wherein an axis of the plurality of keybars is parallel to the longitudinal axle.
2. The component of claim 1, wherein a profile of all midpoints of the plurality of keybars is helicoidal around the longitudinal axle.
3. The component of claim 1, wherein each of the plurality of keybars are straight.
4. The component of claim 1, wherein each of the plurality of keybars are configured to receive a corresponding key on a corresponding rotor section of a plurality of rotor sections, thereby defining a stacked rotor assembly having a step-skewed configuration.
5. The component of claim 4, wherein each of the plurality of rotor sections comprises a plurality of rotor laminations.
6. The component of claim 4, wherein each of the plurality of rotor sections comprises a solid core section.
7. The component of claim 1, wherein each of the plurality of keybars are helicoidal.
8. The component of claim 1, wherein each of the plurality of keybars are configured to receive a corresponding key on a corresponding rotor section of a plurality of rotor sections, thereby defining a stacked rotor assembly having a continuously skewed configuration, wherein the stacked rotor assembly is configured for use in one of an interior permanent magnet (IPM) machine and a Synchronous Reluctance motor.
9. The component of claim 3, the longitudinal axle comprising a plurality of sequential longitudinal sections, wherein each of the plurality of keybars correspond to a longitudinal section of the longitudinal axle.
10. The component of claim 9, wherein each of the plurality of keybars extend partially longitudinally from its corresponding longitudinal section to an adjacent longitudinal section.
11. The component of claim 4, wherein the plurality of keybars are disposed circumferentially around the longitudinal axis, wherein a skew angle, \u03b8sect, is an angle between adjacent rotor sections.
12. The component of claim 11, wherein the skew angle, \u03b8sect, is selected to provide a shift in a torque vs. rotor position profile of the plurality of rotor sections, thereby reducing torque ripple.
13. The component of claim 11, wherein an offset \u03b8key between adjacent keybars comprises \u03b8sect+\u03b80, wherein \u03b80 comprises an additional mechanical offset for clearance for adjacent rotor sections.
14. The component of claim 1, wherein the plurality of keybars comprises a first set of keybars, the component further comprising a second set of keybars, wherein each of the keybars of the second set of keybars is located circumferentially opposite a keybar of the first set of keybars.
15. An assembly comprising:
a plurality of motor rotor sections; and
a rotor bar extending through the plurality of motor rotor sections, wherein the rotor bar and the plurality of motor rotor sections are configured to step-skew the plurality of motor rotor sections from each other.
16. The assembly of claim 15, further comprising a plurality of end plates having the plurality of motor rotor sections located therebetween.
17. The assembly of claim 15, further comprising a plurality of magnets located within the motor rotor sections.
18. The assembly of claim 17, wherein the plurality of magnets comprise a material of at least one of ferrite, alnico, and a rare earth metal.
19. The assembly of claim 15, wherein each of the plurality of motor rotor sections comprise a solid rotor core section.
20. The assembly of claim 15, wherein each of the plurality of motor rotor sections comprise a plurality of rotor laminations.
21. An interior permanent magnet (IPM) machine comprising the assembly of claim 17; and, a stator surrounding the assembly.
22. The IPM machine of claim 21, wherein the assembly is configured to reduce torque ripple in the IPM machine.
23. A Synchronous Reluctance motor comprising the assembly of claim 15; and, a stator surrounding the assembly.
24. The Synchronous Reluctance motor of claim 23, wherein the assembly is configured to reduce torque ripple in the Synchronous Reluctance motor.
25. A method comprising:
providing a longitudinal axle shaft; and
removing material from the longitudinal shaft to define one of:
a plurality of recesses configured to receive a plurality of keybar protrusions; and
a plurality of keybar protrusions, wherein the plurality of keybar protrusions are disposed circumferentially around the longitudinal axis.
26. An Interior Permanent Magnet (IPM) machine rotor comprising:
a plurality of motor rotor sections, wherein the plurality of motor rotor sections are step-skewed.
27. The IPM machine rotor of claim 25, wherein the plurality of motor rotor sections are laminated.
28. The IPM machine rotor of claim 25, wherein the plurality of motor rotor sections are solid core.
29. A Synchronous Reluctance motor rotor comprising:
a plurality of motor rotor sections, wherein the plurality of motor rotor sections are step-skewed.
30. The Synchronous Reluctance motor rotor of claim 29, wherein the plurality of motor rotor sections are laminated.
31. The Synchronous Reluctance motor rotor of claim 29, wherein the plurality of motor rotor sections are solid core.
32. A method of assembly comprising:
providing a plurality of rotor core sections; and
assembling each of the plurality of rotor core sections on a keyed axle shaft, said keyed axle shaft includes at least one key thereon, wherein the at least one key accommodates the plurality of rotor core sections, thereby defining a skewed rotor core stack assembly.
33. The method of claim 32, further comprising applying a compressive force to the skewed rotor core stack assembly.
34. The method of claim 33, further comprising, before applying the compressive force, adjoining at least one compression plate to at least one end of the skewed rotor core stack.
35. The method of claim 32, further comprising:
inserting a plurality of magnets through the plurality of rotor core sections; and
affixing the plurality of magnets to the plurality of rotor core sections.
36. The method of claim 32, the keyed axle shaft including a plurality of keys there, thereby defining a step-skewed rotor core stack.
37. The method of claim 34, the affixing comprising one of:
infusing a resin on the plurality of rotor core sections;
clamping the plurality of magnets with a filler or wedge material; and
shrinking the plurality of magnets into the rotor core sections.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed:

1. A digital signal processor comprising:
first means for selecting a transport stream corresponding to any channel from a transport stream containing a plurality of multiplexed channels,
second means for separating video data and audio data in any desired program from said transport stream by referring to supplementary data in said selected transport stream,
third means for decoding said separated video and audio data,
fourth means for sending video data, audio data and supplementary data from external devices to said second means, and detecting data indicating a program discontinuity, and
fifth means for initializing said third means when said fourth means detects data indicating said program discontinuity.
2. A digital signal processor as defined in claim 1, wherein supplementary data in said second means is updated when said fourth means detects data indicating a program discontinuity.
3. A digital signal processing method, in a digital signal processor comprising first means for selecting a transport stream corresponding to any channel from a transport stream containing a plurality of multiplexed channels, second means for separating video data and audio data in any desired program from said transport stream by referring to supplementary data in said selected transport stream, third means for decoding said separated video and audio data, and fourth means for sending video data, audio data and supplementary data from external devices to said second means, and detecting data indicating a program discontinuity,
said third means is initialized when said fourth means detects data indicating a program discontinuity.
4. A digital signal recordingplayback device comprising:
first means for inputtingoutputting a digital signal coded by a predetermined coding scheme,
second means for recording said digital signal transmitted by said first means in a recording medium,
third means for reproducing said digital signal recorded on said recording medium, and
fourth means for detecting a program change in said digital signal played back by said third means,
wherein said fourth means adds a first identifying data to the digital signal output by said first means when a program change is detected.
5. A digital signal recordingplayback device as defined in claim 1, further comprising fifth means for inputting an operating mode, and adding a second identifying data to the digital signal output by said first means when a speed change playback mode is specified.
6. A digital signal playback method, wherein first identifying data is added to said digital signal when a program in said playback digital signal has changed, when a digital signal coded by a predetermined coding scheme is played back from a recording medium and output to an external device.
7. A digital signal playback method as defined in claim 3 wherein a second identifying data is further added to said digital signal when speed change playback is performed.

1. An expandable drug-eluting catheter, comprising:
an expandable portion having a surface;
a first coating on the surface of the expandable portion, the first coating comprising a negatively charged resin; and
a second coating on the surface of the expandable portion, wherein the first coating is between the surface and the second coating, the second coating comprises a polymeric surface active agent and biocompatible nanoparticles, the biocompatible nanoparticles are formed in layers and in contact with each other, and the nanoparticles are positively charged and entrap a bioactive substance.
2. The drug-eluting catheter of claim 1, wherein the negatively charged resin is formed from any compound selected from the group consisting of a polycarboxylic acid, an acid anhydride of a polycarboxylic acid, or an ester of a polycarboxylic acid.
3. The drug-eluting catheter of claim 2, wherein the polycarboxylic acid is one or more selected from the group consisting of polymers of acrylic acid, methacrylic acid, maleic acid, fumaric acid, aspartic acid and glutamic acid; a carboxymethyl substituted starch, cellulose or polyvinyl alcohol; alginic acid; and pectin.
4. The drug-eluting catheter of claim 2, wherein the acid anhydride or ester of polycarboxylic acid is an acid anhydride or ester of a polymer of acrylic acid, methacrylic acid or maleic acid.
5. The drug-eluting catheter of claim 4, wherein the acid anhydride of polycarboxylic acid is a maleic anhydride copolymer.
6. The drug-eluting catheter of claim 5, wherein the maleic anhydride copolymer is one or more selected from the group consisting of a maleic anhydride-methyl vinyl ether copolymer, a maleic anhydride-styrene copolymer and a maleic anhydride-ethylene copolymer.
7. The drug-eluting catheter of claim 1, wherein the biocompatible nanoparticles are positively charged by adhering a cationic polymer to the surface.
8. The drug-eluting catheter of claim 7, wherein the cationic polymer is a chitosan.
9. The drug-eluting catheter of claim 1, wherein the biocompatible nanoparticles are formed of any compound selected from the group consisting of polylactic acid, polyglycolic acid, a lactic acid-glycolic acid copolymer and a lactic acid-aspartic acid copolymer.
10. The drug-eluting catheter of claim 1, wherein the bioactive substance is a nucleic acid compound.
11. The drug-eluting catheter of claim 10, wherein the nucleic acid compound is one or more selected from the group consisting of a plasmid DNA, a gene, a decoy, an siRNA, an oligonucleotide, an antisense oligonucleotide, a ribozyme and an aptamer.
12. The drug-eluting catheter of claim 11, wherein the nucleic acid compound is an NF\u03baB decoy oligonucleotide.
13. The drug-eluting catheter of claim 12, wherein the NF\u03baB decoy oligonucleotide is one selected from SEQ ID NO. 1, SEQ ID NO. 2 and SEQ ID NO. 3.
14. A method of treating a vascular stenosis or a dialysis shunt stenosis, comprising:
inserting the drug-eluting catheter of claim 12 into the stenosis in a blood vessel, and
expanding the expandable portion,
wherein the bioactive substance is subsequently released from the expandable portion, thereby treating the vascular stenosis or dialysis shunt stenosis.
15. The drug-eluting catheter of claim 1, wherein the drug-eluting catheter is a balloon catheter having a balloon as the expandable portion.
16. The drug-eluting catheter of claim 15, wherein a recess is formed in a surface of the balloon.
17. The drug-eluting catheter of claim 16, wherein the recess is circular or elliptical.
18. A method of manufacturing the drug-eluting catheter of claim 1, the method comprising:
a nanoparticle formation step of
adding a mixed solution of at least a solution of bioactive substance and a solution obtained by dissolving a biocompatible polymer in an organic solvent to an aqueous solution obtained by dissolving at least a cationic polymer;
entrapping the bioactive substance into the biocompatible polymer and generating a suspension of a biocompatible nanoparticle whose surface is positive-charge-modified by adding the mixed solution into an aqueous solution comprising a cationic polymer and a surface active agent;
a negative-charge-modification step of negative charge-modifying an expandable portion of a catheter main body by coating the expandable portion surface with a negatively-charged resin;
a nanoparticle adherence step of forming a nanoparticle layer by adhering the biocompatible nanoparticle to the negative-charge-modified expandable portion; and
a drying step of drying the nanoparticle layer.
19. The method of claim 18, wherein the negative-charge-modification step is performed by dipping the expandable portion in a solution of a polycarboxylic acid or a polycarboxylic acid derivative.
20. The method of claim 18, wherein an anionic bioactive substance is further added to the suspension of the biocompatible nanoparticle.
21. The method of claim 18, wherein the nanoparticle adherence step is repeated a plurality of times to further place a nanoparticle layer on the nanoparticle layer formed on the expandable portion.
22. The method of claim 21, wherein the nanoparticle adherence step is repeated a plurality of times to form the nanoparticle layers of biocompatible nanoparticles entrapping different bioactive substances one on top of another or in a mosaic pattern.
23. The method of claim 18, the method further comprising:
an impregnation step of impregnating the nanoparticle layer with a solution of a biodegradable polymer.
24. The method of claim 23, wherein, in the impregnation step, the bioactive substance is further added to the solution of the biodegradable polymer.
25. The method of claim 23, wherein the biodegradable polymer with which the nanoparticle layer is impregnated in the impregnation step degrades in vivo more rapidly than the biocompatible polymer forming the biocompatible nanoparticle.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

I claim:

1. A hybrid frequency synthesizer, comprising:
a reference source configured to generate a reference frequency signal;
a direct digital frequency synthesizer (DDFS) configured to generate a DDFS output signal;
a mixer coupled to the DDFS and the reference source, and configured to combine the reference frequency signal and the DDFS output signal to generate a mixer output signal; and
a phase locked loop frequency synthesizer (PLL) coupled to the mixer, and configured to generate a frequency synthesizer output that is a multiple of the mixer output signal.
2. The hybrid frequency synthesizer of claim 1, wherein the DDFS includes a frequency control word input that modulates the DDFS output signal.
3. The hybrid frequency synthesizer of claim 1, wherein the reference frequency signal is also a clock input to the DDFS.
4. The hybrid frequency synthesizer of claim 1, wherein the reference source is a crystal oscillator.
5. The hybrid frequency synthesizer of claim 4 wherein the crystal oscillator is a temperature controlled crystal oscillator.
6. The hybrid frequency synthesizer of claim 1, further comprising:
a band pass filter coupled between the mixer and the PLL that reduces phase noise in the mixer output signal.
7. The hybrid frequency synthesizer of claim 1, wherein the PLL has a division ratio in the range of about 32 to about 39.
8. The hybrid frequency synthesizer of claim 1, wherein the DDFS comprises:
a phase accumulator configured to generate a discrete phase signal;
a sine lookup ROM addressed by the discrete phase signal that generates a discrete waveform;
a digital to analog converter (DAC) coupled to the sine lookup ROM that converts the discrete waveform into a continuous waveform of substantially equal frequency; and
a low pass filter coupled to the DAC that smoothes the continuous waveform.
9. The hybrid frequency synthesizer of claim 8, wherein the DDFS further comprises:
a deglitcher coupled between the DAC and the low pass filter that reduces spurious signals generated by the DAC.
10. The hybrid frequency synthesizer of claim 1, wherein the PLL comprises:
a feedback loop system including a divider;
a phase detector configured to compare the mixer output signal and a feedback signal from the feedback loop system, and to generate an error signal as a function of a phase difference between the mixer output signal and the feedback signal;
a charge pump coupled to the phase detector that generates a current pulse having a polarity which is determined by the error signal;
a loop filter coupled to the charge pump that converts the current pulse into a DC voltage; and
a voltage controlled oscillator coupled to the loop filter and the feedback loop system for generating the frequency synthesizer output as a function of the DC voltage.
11. The hybrid frequency synthesizer of claim 1, wherein the DDFS comprises:
a phase accumulator configured to generate a discrete phase signal;
a noise shaper that reduces spurious phase modulation in the discrete phase signal, and which generates a discrete noise shaper output; and
a phase-to-amplitude translator addressed by the discrete noise shaper output for generating a discrete waveform that comprises the DDFS output signal.
12. The hybrid frequency synthesizer of claim 11, wherein the noise shaper is a first order noise shaper.
13. The hybrid frequency synthesizer of claim 11, wherein the noise shaper is a second order noise shaper.
14. The hybrid frequency synthesizer of claim 11, further comprising:
a half-band filter coupled to the phase-to-amplitude translator that reduces noise in the discrete waveform.
15. The hybrid frequency synthesizer of claim 11, wherein the phase-to-amplitude translator generates both a discrete sine waveform and a discrete cosine waveform that collectively comprise the DDFS output signal.
16. The hybrid frequency synthesizer of claim 15, further comprising:
a first half-band filter coupled to the phase-to-amplitude translator that reduces noise in the discrete sine waveform; and
a second half-band filter coupled to the phase-to-amplitude translator that reduces noise in the discrete cosine waveform.
17. The hybrid frequency synthesizer of claim 11, wherein the phase-to-amplitude translator comprises:
a ones complementor coupled to the discrete noise shaper output, and configured to sequentially generate a pass-through output and an inverted output;
a read only memory (ROM) coupled to the ones complementor and configured to generate a first quadrant of the discrete waveform when addressed by the pass-through output and a second quadrant of the discrete waveform when addressed by the inverted output; and
a means for inverting the first and second quadrants of the discrete waveform to generate a third and fourth quadrant of the discrete waveform.
18. The hybrid frequency synthesizer of claim 17, wherein the means for inverting the first and second quadrants of the discrete waveform comprises a most significant bit (MSB) from the discrete noise shaper output appended to the discrete waveform, whereby the MSB acts as a sign bit for the discrete waveform.
19. The hybrid frequency synthesizer of claim 17, wherein the ones complementor is controlled by a second most significant bit (MSB-1) from the discrete noise shaper output.
20. The hybrid frequency synthesizer of claim 17, wherein the ROM is a 2516 bit ROM.
21. The hybrid frequency synthesizer of claim 15, wherein the phase-to-amplitude translator comprises:
a first ones complementor coupled to the discrete noise shaper output, and configured to sequentially generate a first pass-through output and a first inverted output;
a first read only memory (ROM) coupled to the first ones complementor, and configured to generate a first quadrant of the discrete sine waveform when addressed by the first pass-through output and a second quadrant of the discrete sine waveform when addressed by the first inverted output;
a means for inverting the first and second quadrants of the discrete sine waveform to generate a third and fourth quadrants of the discrete sine waveform;
a second ones complementor coupled to the discrete noise shaper output, configured to sequentially generate a second pass-through output and a second inverted output;
a second read only memory (ROM) coupled to the second ones complementor, and configured to generate a first quadrant of the discrete cosine waveform when addressed by the second pass-through output and a second quadrant of the discrete cosine waveform when addressed by the second inverted output; and
a means for inverting the first and second quadrants of the discrete cosine waveform to generate a third and fourth quadrant of the discrete cosine waveform;
22. The hybrid frequency synthesizer of claim 21, wherein:
the means for inverting the first and second quadrants of the discrete sine waveform comprises a most significant bit (MSB) from the discrete noise shaper output appended to the discrete sine waveform, whereby the MSB acts as a sign bit for the discrete sine waveform; and
the means for inverting the first and second quadrants of the discrete cosine waveform comprises the most significant bit (MSB) from the discrete noise shaper output appended to the discrete cosine waveform, whereby the MSB acts as the sign bit for the discrete cosine waveform.
23. The hybrid frequency synthesizer of claim 21, wherein the first and second ones complementors are controlled by a second most significant bit (MSB-1) from the discrete noise shaper output.
24. The hybrid frequency synthesizer of claim 21, wherein the first and second ROMs are 2516 bit ROMs.
25. The hybrid frequency synthesizer of claim 15, wherein the phase-to-amplitude translator comprises:
a read only memory (ROM) that generates a first quadrant of the discrete sine waveform and a first quadrant of the discrete cosine waveform;
a means for reversing the order of the first quadrant of the discrete sine and cosine waveforms, producing a second quadrant of the discrete sine and cosine waveforms; and
a means for inverting the first and second quadrants of the discrete sine and cosine waveforms, producing a third and fourth quadrant of the sine and cosine waveforms.
26. A hybrid frequency synthesizer, comprising:
a reference source configured to generate a reference frequency signal;
a phase accumulator configured to generate a discrete phase signal;
a noise shaper that reduces spurious phase modulation in the discrete phase signal, and which generates a discrete noise shaper output;
a phase-to-amplitude translator addressed by the discrete noise shaper output that generates a discrete sine waveform and a discrete cosine waveform;
a digital image reject mixer coupled to the phase-to-amplitude translator and the reference source, and configured to combine the reference frequency signal and the discrete sine and cosine waveforms to generate a mixer output signal having a most significant bit (MSB); and
a phase locked loop frequency synthesizer (PLL) having an input which is coupled to the MSB of the mixer output signal, and which is configured to generate a frequency synthesizer output that is a multiple of the mixer output signal.
27. The hybrid frequency synthesizer of claim 26, wherein the phase accumulator includes a frequency control word input that modulates the discrete phase signal.
28. The hybrid frequency synthesizer of claim 26, wherein the reference frequency signal is also a clock input to the phase accumulator.
29. The hybrid frequency synthesizer of claim 26, wherein the reference source is a crystal oscillator.
30. The hybrid frequency synthesizer of claim 29, wherein the reference source is a temperature controlled crystal oscillator.
31. The hybrid frequency synthesizer of claim 26, wherein the PLL comprises:
a feedback loop system including a divider;
a phase detector configured to compare the mixer output signal and a feedback signal from the feedback loop system, and to generate an error signal as a function of a phase difference between the mixer output signal and the feedback signal;
a charge pump coupled to the phase detector that generates a current pulse having a polarity that is determined by the error signal;
a loop filter coupled to the charge pump that converts the current pulse into a DC voltage; and
a voltage controlled oscillator coupled to the loop filter and the feedback loop system for generating the frequency synthesizer output as a function of the DC voltage.
32. The hybrid frequency synthesizer of claim 26, wherein the noise shaper is a first order noise shaper.
33. The hybrid frequency synthesizer of claim 26, wherein the noise shaper is a second order noise shaper.
34. The hybrid frequency synthesizer of claim 26, further comprising:
a first half-band filter coupled between the phase-to-amplitude translator and the digital image reject mixer for reducing noise in the discrete sine waveform; and
a second half-band filter coupled between the phase-to-amplitude translator and the digital image reject mixer for reducing noise in the discrete cosine waveform.
35. The hybrid frequency synthesizer of claim 26, wherein the phase-to-amplitude translator comprises a read only memory (ROM).
36. The hybrid frequency synthesizer of claim 26, wherein the phase-to-amplitude translator comprises:
a first ones complementor coupled to the discrete noise shaper output that sequentially generates a first pass-through output and a first inverted output;
a first ROM coupled to the first ones complementor that generates a first quadrant of the discrete sine waveform when addressed by the first pass-through output and a second quadrant of the discrete sine waveform when addressed by the first inverted output;
a means for inverting the first and second quadrants of the discrete sine waveform to generate a third and fourth quadrant of the discrete sine waveform;
a second ones complementor coupled to the discrete noise shaper output that sequentially generates a second pass-through output and a second inverted output;
a second ROM coupled to the second ones complementor that generates a first quadrant of the discrete cosine waveform when addressed by the second pass-through output and a second quadrant of the discrete cosine waveform when addressed by the second inverted output; and
a means for inverting the first and second quadrants of the discrete cosine waveform to generate a third and fourth quadrant of the discrete cosine waveform.
37. The hybrid frequency synthesizer of claim 36, wherein
the means for inverting the first and second quadrants of the discrete sine waveform comprises a most significant bit (MSB) from the discrete noise shaper output appended to the discrete sine waveform, whereby the MSB acts as a sign bit for the discrete sine waveform; and
the means for inverting the first and second 90 quadrants of the discrete cosine waveform comprises the most significant bit (MSB) from the discrete noise shaper output appended to the discrete cosine waveform, whereby the MSB acts as the sign bit for the discrete cosine waveform.
38. The hybrid frequency synthesizer of claim 36, wherein the first and second ones complementors are controlled by a second most significant bit (MSB-1) from the discrete noise shaper output.
39. The hybrid frequency synthesizer of claim 36, wherein the first and second ROMs are 2516 bit ROMs.
40. The hybrid frequency synthesizer of claim 26, wherein the phase-to-amplitude translator comprises:
a read only memory (ROM) that generates a first quadrant of the discrete sine waveform and a first quadrant of the discrete cosine waveform;
a means for reversing the order of the first quadrant of the discrete sine and cosine waveforms, producing a second quadrant of the discrete sine and cosine waveforms; and
a means for inverting the first and second quadrants of the discrete sine and cosine waveforms, producing a third and fourth quadrant of the sine and cosine waveforms.
41. The hybrid frequency synthesizer of claim 26, wherein the digital image reject mixer comprises:
a divider coupled to the reference source that generates a 0 phased clock signal and a 90 phased clock signal;
a first ones complementor coupled to the discrete sine waveform that generates an inverted discrete sine waveform;
a first multiplexer having a first state and a second state controlled by the 0 phased clock signal, which multiplies the 0 phased clock signal with the discrete sine waveform to generate a first multiplexer output when in the first state, and multiplies the 0 phased clock signal with the inverted discrete sine waveform to generate the first multiplexer output when in the second state;
a second ones complementor coupled to the discrete cosine waveform that generates an inverted discrete cosine waveform;
a second multiplexer having a first state and a second state, which multiplies the 90 phased clock signal with the discrete cosine waveform to generate a second multiplexer output when in the first state, and multiplies the 90 phased clock signal with the inverted discrete cosine waveform to generate the second multiplexer output when in the second state; and
an adder that sums the first multiplexer output and the second multiplexer output to generate the mixer output signal.
42. A hybrid frequency synthesizer, comprising:
a reference source configured to generate a reference frequency signal;
a phase accumulator configured to generate a discrete phase signal;
a noise shaper that reduces spurious phase modulation in the discrete phase signal and which generates a discrete noise shaper output;
a phase-to-amplitude translator addressed by the discrete noise shaper output that generates a discrete sine waveform and a discrete cosine waveform;
a digital image reject mixer coupled to phase-to-amplitude translator and the reference source, and configured to combine the reference frequency signal and the discrete sine and cosine waveforms to generate a mixer output signal;
a band pass sigma delta modulator coupled to the image reject mixer that converts the mixer output signal into a modulated one bit signal; and
a phase locked loop frequency synthesizer (PLL) having an input coupled to the modulated one bit signal, and configured to generate a frequency synthesizer output that is a multiple of the modulated one bit signal.
43. The hybrid frequency synthesizer of claim 42, wherein the phase accumulator includes a frequency control word input that modulates the discrete phase signal.
44. The hybrid frequency synthesizer of claim 42, wherein the reference frequency signal is also a clock input to the phase accumulator.
45. The hybrid frequency synthesizer of claim 42, wherein the reference source is a crystal oscillator.
46. The hybrid frequency synthesizer of claim 45, wherein the reference source is a temperature controlled crystal oscillator.
47. The hybrid frequency synthesizer of claim 42, wherein the PLL comprises:
a feedback loop system including a divider;
a phase detector configured to compare the mixer output signal and a feedback signal from the feedback loop system, and to generate an error signal as a function of a phase difference between the mixer output signal and the feedback signal;
a charge pump coupled to the phase detector that generates a current pulse having a polarity that is determined by the error signal;
a loop filter coupled to the charge pump that converts the current pulse into a DC voltage; and
a voltage controlled oscillator coupled to the loop filter and the feedback loop system for generating the frequency synthesizer output as a function of the DC voltage.
48. The hybrid frequency synthesizer of claim 42, wherein the noise shaper is a first order noise shaper.
49. The hybrid frequency synthesizer of claim 42, wherein the noise shaper is a second order noise shaper.
50. The hybrid frequency synthesizer of claim 42, further comprising:
a first half-band filter coupled between the phase-to-amplitude translator and the digital image reject mixer, and configured to reduce noise in the discrete sine waveform; and
a second half-band filter coupled between the phase-to-amplitude translator and the digital image reject mixer, and configured to reduce noise in the discrete cosine waveform.
51. The hybrid frequency synthesizer of claim 42, wherein the phase-to-amplitude translator comprises a read only memory (ROM).
52. The hybrid frequency synthesizer of claim 42, wherein the phase-to-amplitude translator comprises:
a first ones complementor coupled to the discrete noise shaper output, and configured to sequentially generate a first pass-through output and a first inverted output;
a first ROM coupled to the first ones complementor, and configured to generate a first quadrant of the discrete sine waveform when addressed by the first pass-through output and a second quadrant of the discrete sine waveform when addressed by the first inverted output;
a means for inverting the first and second quadrants of the discrete sine waveform to generate a third and fourth quadrant of the discrete sine waveform;
a second ones complementor coupled to the discrete noise shaper output, and configured to sequentially generate a second pass-through output and a second inverted output;
a second ROM coupled to the second ones complementor, and configured to generate a first quadrant of the discrete cosine waveform when addressed by the second pass-through output and a second quadrant of the discrete cosine waveform when addressed by the second inverted output; and
a means for inverting the first and second quadrants of the discrete cosine waveform to generate a third and fourth quadrant of the discrete cosine waveform.
53. The hybrid frequency synthesizer of claim 52, wherein
the means for inverting the first and second quadrants of the discrete sine waveform comprises a most significant bit (MSB) from the discrete noise shaper output appended to the discrete sine waveform, whereby the MSB acts as a sign bit for the discrete sine waveform; and
the means for inverting the first and second quadrants of the discrete cosine waveform comprises the most significant bit (MSB) from the discrete noise shaper output appended to the discrete cosine waveform, whereby the MSB acts as the sign bit for the discrete cosine waveform.
54. The hybrid frequency synthesizer of claim 52, wherein the first and second ones complementors are controlled by a second most significant bit (MSB-1) from the discrete noise shaper output.
55. The hybrid frequency synthesizer of claim 52, wherein the first and second ROMs are 2516 bit ROMs.
56. The hybrid frequency synthesizer of claim 42, wherein the phase-to-amplitude translator comprises:
a read only memory (ROM) that generates a first quadrant of the discrete sine waveform and a first quadrant of the discrete cosine waveform;
a means for reversing the order of the first quadrant of the discrete sine and cosine waveforms, producing a second quadrant of the discrete sine and cosine waveforms; and
a means for inverting the first and second quadrants of the discrete sine and cosine waveforms, producing a third and fourth quadrant of the sine and cosine waveforms.
57. The hybrid frequency synthesizer of claim 42, wherein the digital image reject mixer comprises:
a divider coupled to the reference source that generates a 0 phased clock signal and a 90 phased clock signal;
a first ones complementor coupled to the discrete sine waveform that generates an inverted discrete sine waveform;
a first multiplexer having a first state and a second state controlled by the 0 phased clock signal, which multiplies the 0 phased clock signal with the discrete sine waveform to generate a first multiplexer output when in the first state, and multiplies the 0 phased clock signal with the inverted discrete sine waveform to generate the first multiplexer output when in the second state;
a second ones complementor coupled to the discrete cosine waveform that generates an inverted discrete cosine waveform;
a second multiplexer having a first state and a second state, which multiplies the 90 phased clock signal with the discrete cosine waveform to generate a second multiplexer output when in the first state, and multiplies the 90 phased clock signal with the inverted discrete cosine waveform to generate the second multiplexer output when in the second state; and
an adder that sums the first multiplexer output and the second multiplexer output to generate the mixer output signal.
58. The hybrid frequency synthesizer of claim 42, further comprising:
an analog filter coupled between the band pass sigma delta modulator and the PLL that removes spurious signals from the modulated one bit signal.
59. A direct digital frequency synthesizer, comprising:
a phase accumulator configured to generate a discrete phase signal;
a noise shaper that reduces spurious phase modulation in the discrete phase signal, and which generates a discrete noise shaper output;
a phase-to-amplitude translator addressed by the discrete noise shaper output that generates a discrete waveform; and
a digital to analog converter (DAC) coupled to the phase-to-amplitude translator that converts the discrete waveform to a continuous waveform.
60. The direct digital frequency synthesizer of claim 59, wherein the phase accumulator includes a frequency control word input that modulates the discrete phase signal.
61. The direct digital frequency synthesizer of claim 59, further comprising:
a reference source coupled to a clock input of the phase accumulator.
62. The direct digital frequency synthesizer of claim 61, wherein the reference source is a crystal oscillator.
63. The direct digital frequency synthesizer of claim 62, wherein the reference source is a temperature controlled crystal oscillator.
64. The direct digital frequency synthesizer of claim 59, wherein the noise shaper is a first order noise shaper.
65. The direct digital frequency synthesizer of claim 59 wherein the noise shaper is a second order noise shaper.
66. The direct digital frequency synthesizer of claim 59, further comprising:
a half-band filter coupled between the phase-to-amplitude translator and the DAC that reduces noise in the discrete waveform.
67. The direct digital frequency synthesizer of claim 59, wherein the phase-to-amplitude translator comprises a read only memory (ROM).
68. The direct digital frequency synthesizer of claim 59, wherein the phase-to-amplitude translator comprises:
a ones complementor coupled to the discrete noise shaper output, and configured to sequentially generate a pass-through output and an inverted output;
a ROM coupled to the ones complementor, and configured to generate a first quadrant of the discrete waveform when addressed by the pass-through output and a second quadrant of the discrete waveform when addressed by the inverted output; and
a means for inverting the first and second quadrants of the discrete waveform to generate a third and fourth quadrant of the discrete waveform.
69. The direct digital frequency synthesizer of claim 68, wherein the means for inverting the first and second quadrants of the discrete waveform comprises a most significant bit (MSB) from the discrete noise shaper output appended to the discrete waveform, whereby the MSB acts as a sign bit for the discrete waveform.
70. The direct digital frequency synthesizer of claim 68, wherein the ones complementor is controlled by a second most significant bit (MSB-1) from the discrete noise shaper output.
71. The direct digital frequency synthesizer of claim 68, wherein the ROM is a 2516 bit ROM.
72. The direct digital frequency synthesizer of claim 59, further comprising:
a low pass filter coupled to the DAC that smoothes the continuous waveform.