Author: claimsbot

1. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a low impedance driver coupled to the memory cell and generating an output signal indicative of the contents of said memory cell; and
a comparator coupled to the output of the low impedance driver and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
2. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a wide output gain stage coupled to the memory cell and generating an output signal indicative of the contents of said memory cell; and
a comparator coupled to the output of the wide output gain stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
3. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a feedback cascode circuit coupled to the memory cell via a bitline and having an output generating an output signal indicative of the contents of said memory cell in response to a signal on the bitline; and
a comparator coupled to the output of the feedback cascode circuit and to at least one voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
4. A sense amplifier for reading the contents of the memory cell, the sense amplifier comprising:
a replica precharge stage coupled to the memory cell via a bit line to precharge the bitline at a level replicating a bias level applied to the bitline; and
a comparator coupled of the replica precharge circuit and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
5-45. (canceled)
46. A sense amplifier for reading memory cells storing data having multilevel voltages, the sense amplifier comprising:
a high speed load stage coupled to the memory cells to sense the content of the memory cells;
a wide output gain stage coupled to the high speed load stage to provide a first detected voltage signal in response to the sensed content;
a low impedance output stage to provide a second detected voltage signal in response to the first detected voltage signal;
a comparator stage for comparing the data to at least one reference voltage level and generating corresponding comparison signals for the at least one reference voltage levels;
a latch for storing the comparison signals.
47. The sense amplifier of claim 46 wherein the high speed load stage comprises a load and a cascode circuit.
48. The sense amplifier of claim 46 wherein the comparator stage comprises a differential amplifier.
49. The sense amplifier of claim 48 wherein the comparator stage comprises a latch.
50. The sense amplifier of claim 48 wherein the comparator stage comprises a latch including an initial latching amplification circuit.
51. The sense amplifier of claim 50 wherein the initial latching amplification circuit includes an analog bootstrap circuit.
52. The sense amplifier of claim 50 wherein the comparator stage comprises a post latching amplification circuit.
53. The sense amplifier of claim 46 further comprising a precharge circuit to precharge a voltage on a bit line coupling the memory cell to the high speed load stage.
54. A sense amplifier comprising:
means for sensing at high speed content of a memory cell;
means for driving a load independent of the sensed current of the memory cell;
means for comparing the sensed content to at least one reference voltage.
55. A sense amplifier of claim 54 further comprising means for matching at least one compared data.
56. The sense amplifier of claim 55 further comprising means for decoding the latched content.
57. The sense amplifier of claim 54 further comprising means for precharging a line connecting said loading means and said memory cell.
58. The sense amplifier of claim 54 further comprising means for amplifying the sensed content of the memory cell, and wherein the means for driving further drives the load in response to the amplified sensed content.
59. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels;
a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels;
a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells; and
a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells, the data sense amplifiers and the reference sense amplifiers having a similar circuit structure.
60. The memory of claim 59 wherein each data sense amplifier comprises:
an input stage coupled to said group of data memory cells and having an output for providing a low impedance driver signal indicative of the contents of a selected one of said group of data memory cells; and
a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage,
wherein each reference sense comprises:
an input stage coupled to said group of data memory cells and having an output for providing a low impedance driver signal indicative of the contents of a selected one of said group of data memory cells, the input stage of the reference sense amplifier having a similar circuit structure as the input stage of the data sense amplifier; and
a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage, the comparator of the reference sense amplifier having a similar circuit structure as comparator of the data sense amplifier.
61. The memory of claim 59 further comprising:
a plurality of redundant memory cells, each redundant memory cell configurable to store one of a plurality of signal levels, the redundant memory cells being coupled to one of the plurality of reference sense amplifiers.
62. The memory of claim 61 wherein the reference sense amplifier comprises a feedback and precharge circuit to multiplex the reference memory cells and the redundant memory cells to a comparator for detecting the contents therein.
63. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels;
a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels;
a plurality of redundant memory cells, each redundant memory cell configurable to store one of a plurality of signal levels;
a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells; and
a plurality of first sense amplifiers, each first sense amplifier being coupled to one of said reference cells and to at least one redundant memory cells.
64. The memory of claim 63 wherein the first sense amplifiers comprise a feedback and precharge circuit to multiplex the reference memory cells and the redundant memory cells to a comparator for detecting the contents therein.
65. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels;
a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels;
a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said memory cells;
a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells; and
a plurality of reference cascode pull up circuits, each reference cascode pull up circuit being coupled to a corresponding one of said reference memory cells and one of said plurality of data memory cells.
66. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels;
a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels;
a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells;
a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells;
a reference cascode circuit coupled to the reference sense amplifiers for controlling the reference sense amplifiers, the reference cascode circuit comprising a low impedance stage for providing a low impedance drivers signal to the reference sense amplifier, the data sense amplifiers including an input stage for loading a bitline coupled to the memory cell and having an output providing a low impedance driver signal indicative of the contents of a corresponding data memory cell, the sizing of the low impedance stage of the reference cascode circuit and the input stage of the data sense amplifier being in a relation to maintain a DC operating condition substantially the same for said input stages.
67. The memory of claim 66 wherein the reference cascode circuit includes a selectable pull-up circuit for selectable pull-up ratios, the reference levels.
68. A memory array comprising:
a plurality of memory cells arranged in a plurality of columns, a plurality of bit lines coupled to a corresponding one of said plurality of columns of memory cells;
a plurality of sense amplifiers, each amplifier being disposed adjacent a group of said memory cells;
each sense amplifier comprising:
an input stage for loading of a bit line coupled to the memory cell and having an output for providing a low impedance driver signal indicative of the contents of said memory cell; and
a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage signal.
69. The memory of claim 68 further comprising a plurality of current sources disposed in a direction substantially perpendicular to the direction of the bit line to compensate for current changes in said direction.
70. A method for setting reference voltage levels in a multilevel memory system, the method comprising:
programming a first plurality of memory cells with global reference voltage levels; and
programming a second plurality of memory cells with local reference voltage levels, each of the second plurality of memory cells being adjacent a corresponding plurality of data memory cells.
71. The method of claim 70 wherein said programming said second plurality of memory cells includes incremental programming.
72. The method of claim 71 wherein said incremental programming includes incrementally increasing a voltage to program in one of said plurality of memory cells and comparing said programmed voltage to a corresponding global reference voltage level, and repeating said increasing and comparison until the comparison indicates a match.
73. The method of claim 70 wherein said programming a first plurality of memory cells comprises verifying a programmed voltage in said memory cells by reading said memory cell and comparing said memory cell to sequentially comparing the read memory cell to a plurality of different voltage levels to determine the voltage level stored in said memory cell.
74. A method for reading a memory cell in a multilevel memory system, the method comprising:
comparing a voltage detected in said memory cell to a voltage stored in one of a plurality of local reference memory cells in series; and
indicating the data stored in said read memory cell in the event that the said comparison indicates a read voltage of the memory cell above one above the local reference voltage levels and below the next highest local reference voltage level.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data transfer unit, comprising:
a first interface coupled to a computer;
a second interface coupled to an external device; and
a control unit for transferring data between the first interface and the second interface,
the control unit comprising at least one memory transaction issuing unit for issuing, when one of the first interface and the second interface receives an access request to a main memory of the computer, a memory transaction for the main memory to the first interface, wherein:

the first interface comprises a plurality of interfaces coupled in parallel to the computer; and
the control unit is configured to:
extract an address of the main memory, which is contained in the memory transaction issued by the at least one memory transaction issuing unit; and
transmit the memory transaction to one of the plurality of interfaces according to the extracted address.
2. The data transfer unit according to claim 1, wherein the control unit further comprises a memory transaction distribution unit for selecting, based on correspondence between a preset transfer destination address of the memory transaction and the plurality of interfaces, an interface having address designation information set therein, which corresponds to the extracted address from the plurality of interfaces, and transmitting the memory transaction to the selected interface.
3. The data transfer unit according to claim 2, wherein:
the control unit further comprises a distribution information storage unit for storing the address designation information describing the correspondence; and
the memory transaction distribution unit selects, by referring to the distribution information storage unit based on the address of the main memory, which has been extracted from the memory transaction, the interface having the address designation information set therein, which corresponds to the address.
4. The data transfer unit according to claim 2, wherein the control unit further comprises a completion guaranteeing unit for notifying, if the received access request contains a completion guaranteeing request of the memory transaction, when completion of access to the main memory for the memory transaction transmitted by the memory transaction distribution unit is detected, one of the computer and a transmission source of the access request of the completion of the memory transaction.
5. The data transfer unit according to claim 4, wherein:
the control unit further comprises a completion status storage unit for storing information for identifying one of the completion and noncompletion of the memory transaction for each of the plurality of interfaces to which the memory transaction distribution unit has transmitted the memory transaction; and
the completion guaranteeing unit is configured to:
issue, if the received access request contains the completion guaranteeing request of the memory transaction, a completion guaranteeing transaction to the one of the plurality of interfaces for which the information of the completion status storage unit indicates the noncompletion; and
detect, when all responses to the completion guaranteeing transaction are received, the completion of the access to the main memory for the memory transaction.
6. The data transfer unit according to claim 2, wherein:
the control unit further comprises a distribution method setting unit for setting a condition for selecting, by the memory transaction distribution unit, the one of the plurality of interfaces; and
the memory transaction distribution unit selects the one of the plurality of interfaces under the condition set by the distribution method setting unit.
7. The data transfer unit according to claim 6, wherein the distribution method setting unit comprises a storage unit for setting one of validity and invalidity of data transfer for the each of the plurality of interfaces.
8. The data transfer unit according to claim 1, wherein the second interface is a network interface, which is coupled to a network, for transmitting and receiving a signal.
9. The data transfer unit according to claim 8, wherein the second interface performs DMA transfer between a computer coupled to the network and the main memory of the computer coupled to the first interface.
10. The data transfer unit according to claim 1, wherein the first interface is configured by PCI Express.
11. The data transfer unit according to claim 5, wherein, for the completion guaranteeing transaction, a memory read request transaction is used.

1. A method for cleaning an article comprising:
providing an article comprising a substrate having a surface and a contaminate disposed on said surface;
contacting said contaminate with a cleaning composition comprising 1-chloro-3,3,3-trifluoropropene while said contaminate is disposed on said surface;
solvating at least a portion of said contaminate in said cleaning composition; and
separating said contaminate from said article.
2. The method of claim 1 wherein said cleaning composition further comprises at least one haloolefin selected from the group consisting of dichloro-tetrafluoro-propene; chloro-trifluoro-propene; and tetrafluorobutene.
3. The method of claim 1 wherein said cleaning composition further comprises at least one co-solvent selected from the group consisting of include linear, branched and cyclic hydrocarbons, halocarbons, alcohols, ketones, esters, ethers, and acetals.
4. The method of claim 2 wherein said cleaning composition further comprises at least one co-solvent selected from the group consisting of include linear, branched and cyclic hydrocarbons, halocarbons, alcohols, ketones, esters, ethers, and acetals.
5. The method of claim 3 wherein said co-solvent is a chlorinated halocarbon.
6. The method of claim 3 wherein said co-solvent is an alcohol selected from the group consisting of methanol, ethanol, propanol, isopropanol, and butanol.
7. The method of claim 1 wherein said cleaning composition comprises at least about 10 wt. % of said 1-chloro-3,3,3-trifluoropropene.
8. The method of claim 1 wherein said cleaning composition comprises at least about 30 wt. % of said 1-chloro-3,3,3-trifluoropropene.
9. The method of claim 1 wherein said contaminate is selected from the group consisting of grease, oil, wax, and photoresist residue.
10. The method of claim 1 wherein said substrate is selected from metal and printed circuit boards.
11. The method of claim 1 wherein said separating step involves separating a majority of said contaminant from said article.
12. The method of claim 1 wherein said contacting involves spraying said cleaning composition on said article.
13. The method of claim 12 wherein said cleaning composition is an aerosol.
14. The method of claim 1 wherein said contacting involves wiping said article with said cleaning composition.
15. A method for cleaning an article comprising:
exposing an article having a contaminate disposed thereon to vapors of a boiling cleaning composition comprising 1-chloro-3,3,3-trifluoropropene;
condensing at least a portion of said cleaning composition on said article; and
separating said cleaning composition from said article, wherein said condensed cleaning composition comprises at least a portion of said contaminate.
16. The method of claim 15 wherein said exposing step is performed at about ambient temperature.
17. The method of claim 15 wherein said exposing step is performed at a temperature greater than about ambient temperature.
18. The method of claim 15 wherein said exposing step is performed at a temperature that is about the boiling point of said cleaning solvent.
19. A method for cleaning an article comprising:
immersing an article having a contaminate disposed thereon in a cleaning composition comprising 1-chloro-3,3,3-trifluoropropene;
solvating at least a portion of said contaminate in said cleaning composition; and
removing said article from said cleaning composition.
20. The method of claim 19 wherein said cleaning composition is boiling during said immersion step.
21. The method of claim 17 wherein said removing step involves flushing said cleaning composition from said article.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for testing performance of a constrained resources computing device (CRCD), comprising:
a) determining that a data sample was generated, wherein the determining includes receiving a notification from a testing application that the data sample was generated;
b) generating a time stamp corresponding to when the data sample was generated;
c) defining a plurality of time intervals, each of the plurality of time intervals being of a size to enable human perception to perceive processing as substantially instantaneous when processing occurs during each of the plurality of time intervals;
d) assigning the data sample having the time stamp to one of the plurality of time intervals, the time stamp of the data sample being analyzed to enable the assigning of the data sample to a corresponding time interval that can accept the data sample having the generated time stamp, wherein each of the plurality of time intervals defines a runtime of the testing application; and
e) incrementing a counter associated with the defined time interval corresponding to the time stamp when the data sample is assigned to the defined time interval, wherein a memory within the CRCD is used in storing the counter representing the number of data samples generated for each of the defined time intervals, the counters from each of the plurality of time intervals used in performing statistical analysis of the data sample to determine the performance of the CRCD.
2. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein a length of time of the defined time interval is between about 50 to about 200 ms in time.
3. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein the data sample is a data packet.
4. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein the data sample is one of a frame of graphics, an algorithm data, a user interface event processing data, a network data packet.
5. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein the counter defines a number of data samples generated during the defined time interval.
6. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein a length of time of the defined time interval is at most about 50 ms.
7. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, further comprising:
determining a number of data samples associated with each one of a plurality of defined time intervals.
8. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, wherein the defined time interval is one of a plurality of time intervals, each one of the plurality of time intervals being between about 50 ms and about 200 ms.
9. A method for testing performance of a constrained resources computing device (CRCD) as recited in claim 1, further comprising:
repeating operations a\u2013e.
10. A computer readable media having program instructions for testing performance of a constrained resources computing device (CRCD), the computer readable media comprising:
program instructions for determining that a data sample was generated, wherein the determining includes receiving a notification from a testing application that the data sample was generated;
program instructions for generating a time stamp corresponding to when the data sample was generated;
program instructions for defining a plurality of time intervals, each of the plurality of time intervals being 50 ms in size to enable human perception to perceive processing as substantially instantaneous when processing occurs during each of the plurality of time intervals;
program instructions for assigning the data sample having the time stamp to one of the plurality of time intervals, the time stamp of the data sample being analyzed to enable the assigning of the data sample to a corresponding time interval that can accept the data sample having the generated time stamp each of the plurality of time intervals defines a runtime of the testing application; and
program instructions for incrementing a counter associated with the defined time interval corresponding to the time stamp when the data sample is assigned to the defined time interval, wherein a memory within the CRCD is used in storing the counter representing the number of data samples generated for each of the defined time intervals, the counters from each of the plurality of time intervals used in performing statistical analysis of the data sample to determine the performance of the CRCD.
11. A computer readable media as recited in claim 10, wherein the data sample is a data packet.
12. A computer readable media as recited in claim 10, wherein the data sample is one of a frame of graphics, an algorithm data, a user interface event processing data, a network data packet.
13. A computer readable media as recited in claim 10, wherein the counter defines a number of data samples completed within the defined time interval.